Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	710455	1			T1	1		T2	229		T3	2
all_values[1]	710455	1			T1	1		T2	229		T3	2
all_values[2]	710455	1			T1	1		T2	229		T3	2
all_values[3]	710455	1			T1	1		T2	229		T3	2
all_values[4]	710455	1			T1	1		T2	229		T3	2
all_values[5]	710455	1			T1	1		T2	229		T3	2
all_values[6]	710455	1			T1	1		T2	229		T3	2
all_values[7]	710455	1			T1	1		T2	229		T3	2
all_values[8]	710455	1			T1	1		T2	229		T3	2
all_values[9]	710455	1			T1	1		T2	229		T3	2
all_values[10]	710455	1			T1	1		T2	229		T3	2
all_values[11]	710455	1			T1	1		T2	229		T3	2
all_values[12]	710455	1			T1	1		T2	229		T3	2
all_values[13]	710455	1			T1	1		T2	229		T3	2
all_values[14]	710455	1			T1	1		T2	229		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8758979

1

T1

15

T2

2927

T3

30

auto[1]

1897846

1

T2

508

T4

6

T5

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10383319

1

T1

15

T2

3435

T3

30

auto[1]

273506

1

T21

283

T180

111

T181

124

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	94687	1			T1	1		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	343	1			T21	18		T181	6		T234	150
all_values[0]	auto[1]	auto[0]	598965	1			T2	227		T4	2		T5	2
all_values[0]	auto[1]	auto[1]	16460	1			T21	2		T180	9		T181	3
all_values[1]	auto[0]	auto[0]	691681	1			T1	1		T2	229		T3	2
all_values[1]	auto[0]	auto[1]	18370	1			T21	16		T180	4		T181	5
all_values[1]	auto[1]	auto[0]	276	1			T266	10		T94	7		T267	2
all_values[1]	auto[1]	auto[1]	128	1			T21	4		T180	5		T181	4
all_values[2]	auto[0]	auto[0]	691759	1			T1	1		T2	229		T3	2
all_values[2]	auto[0]	auto[1]	18362	1			T21	14		T180	6		T181	4
all_values[2]	auto[1]	auto[0]	189	1			T235	2		T264	1		T64	1
all_values[2]	auto[1]	auto[1]	145	1			T21	2		T180	3		T181	5
all_values[3]	auto[0]	auto[0]	691938	1			T1	1		T2	229		T3	2
all_values[3]	auto[0]	auto[1]	18370	1			T21	15		T180	5		T181	6
all_values[3]	auto[1]	auto[1]	147	1			T21	5		T180	4		T181	2
all_values[4]	auto[0]	auto[0]	691927	1			T1	1		T2	229		T3	2
all_values[4]	auto[0]	auto[1]	18374	1			T21	19		T180	6		T181	4
all_values[4]	auto[1]	auto[0]	23	1			T13	1		T268	1		T269	1
all_values[4]	auto[1]	auto[1]	131	1			T21	1		T180	3		T181	2
all_values[5]	auto[0]	auto[0]	694374	1			T1	1		T2	229		T3	2
all_values[5]	auto[0]	auto[1]	15927	1			T21	17		T180	2		T181	4
all_values[5]	auto[1]	auto[1]	154	1			T21	3		T180	2		T181	5
all_values[6]	auto[0]	auto[0]	691939	1			T1	1		T2	229		T3	2
all_values[6]	auto[0]	auto[1]	18360	1			T21	14		T180	6		T181	6
all_values[6]	auto[1]	auto[1]	156	1			T21	6		T180	3		T181	2
all_values[7]	auto[0]	auto[0]	668609	1			T1	1		T2	190		T3	2
all_values[7]	auto[0]	auto[1]	17958	1			T21	19		T180	5		T181	4
all_values[7]	auto[1]	auto[0]	23332	1			T2	39		T4	1		T5	1
all_values[7]	auto[1]	auto[1]	556	1			T21	1		T180	1		T181	5
all_values[8]	auto[0]	auto[0]	691977	1			T1	1		T2	229		T3	2
all_values[8]	auto[0]	auto[1]	18332	1			T21	14		T180	7		T181	3
all_values[8]	auto[1]	auto[1]	146	1			T21	5		T180	1		T181	6
all_values[9]	auto[0]	auto[0]	157097	1			T1	1		T2	214		T3	2
all_values[9]	auto[0]	auto[1]	4906	1			T21	14		T181	6		T236	1705
all_values[9]	auto[1]	auto[0]	534843	1			T2	15		T4	1		T5	1
all_values[9]	auto[1]	auto[1]	13609	1			T21	5		T181	3		T236	18
all_values[10]	auto[0]	auto[0]	691926	1			T1	1		T2	229		T3	2
all_values[10]	auto[0]	auto[1]	18387	1			T21	17		T180	6		T181	4
all_values[10]	auto[1]	auto[1]	142	1			T21	2		T180	3		T181	5
all_values[11]	auto[0]	auto[0]	2303	1			T1	1		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	194	1			T21	15		T181	3		T236	8
all_values[11]	auto[1]	auto[0]	689640	1			T2	227		T4	2		T5	2
all_values[11]	auto[1]	auto[1]	18318	1			T21	4		T180	9		T181	2
all_values[12]	auto[0]	auto[0]	691893	1			T1	1		T2	229		T3	2
all_values[12]	auto[0]	auto[1]	18360	1			T21	14		T180	3		T181	4
all_values[12]	auto[1]	auto[0]	65	1			T64	1		T65	1		T68	2
all_values[12]	auto[1]	auto[1]	137	1			T21	3		T180	2		T181	3
all_values[13]	auto[0]	auto[0]	691944	1			T1	1		T2	229		T3	2
all_values[13]	auto[0]	auto[1]	18369	1			T21	13		T180	6		T181	7
all_values[13]	auto[1]	auto[1]	142	1			T21	3		T180	2		T181	2
all_values[14]	auto[0]	auto[0]	691932	1			T1	1		T2	229		T3	2
all_values[14]	auto[0]	auto[1]	18381	1			T21	13		T180	7		T181	8
all_values[14]	auto[1]	auto[1]	142	1			T21	5		T180	1		T181	1