Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.18 97.23 89.50 97.22 72.02 94.23 98.47 89.58


Total tests in report: 1848
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
61.14 61.14 84.09 84.09 59.28 59.28 60.79 60.79 18.45 18.45 75.41 75.41 87.77 87.77 42.21 42.21 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_host_stretch_timeout.1516401695
74.46 13.31 92.12 8.03 72.68 13.40 90.14 29.35 39.29 20.83 86.03 10.62 90.83 3.06 50.11 7.89 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_bad_addr.4107381473
79.41 4.96 94.37 2.25 79.79 7.11 91.76 1.62 42.86 3.57 88.45 2.42 91.70 0.87 66.95 16.84 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_host_stress_all.3281781287
83.53 4.12 94.74 0.37 81.41 1.62 92.23 0.46 66.67 23.81 89.02 0.57 91.92 0.22 68.74 1.79 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_glitch.3076280949
84.85 1.32 94.77 0.03 82.65 1.24 93.16 0.93 66.67 0.00 89.09 0.07 95.63 3.71 72.00 3.26 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.3523584887
85.62 0.77 95.17 0.40 84.38 1.73 93.62 0.46 67.86 1.19 90.38 1.28 95.85 0.22 72.11 0.11 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_nack_txstretch.954788285
86.19 0.57 95.20 0.03 84.49 0.11 96.52 2.90 67.86 0.00 90.45 0.07 96.07 0.22 72.74 0.63 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_sec_cm.2098998768
86.73 0.54 95.20 0.00 84.57 0.08 96.52 0.00 67.86 0.00 90.45 0.00 96.07 0.00 76.42 3.68 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/16.i2c_host_stress_all.1024225485
87.23 0.51 95.60 0.40 85.70 1.13 96.52 0.00 67.86 0.00 91.30 0.86 96.07 0.00 77.58 1.16 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_host_may_nack.2299788596
87.71 0.47 95.72 0.12 86.30 0.60 96.75 0.23 67.86 0.00 91.87 0.57 96.29 0.22 79.16 1.58 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_acq.717591605
88.18 0.47 96.00 0.28 86.86 0.56 96.75 0.00 67.86 0.00 92.66 0.78 96.51 0.22 80.63 1.47 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_host_override.2232494633
88.50 0.31 96.21 0.22 87.09 0.23 96.75 0.00 69.05 1.19 93.01 0.36 96.51 0.00 80.84 0.21 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_stress_all.2707035876
88.80 0.31 96.65 0.43 87.09 0.00 96.75 0.00 70.24 1.19 93.44 0.43 96.51 0.00 80.95 0.11 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull_addr.1738176304
89.02 0.22 96.65 0.00 87.09 0.00 96.75 0.00 70.24 0.00 93.44 0.00 98.03 1.53 80.95 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.85877044
89.22 0.20 96.80 0.15 87.32 0.23 96.75 0.00 70.83 0.60 93.66 0.21 98.03 0.00 81.16 0.21 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull.1070500049
89.41 0.18 96.80 0.00 87.43 0.11 96.98 0.23 70.83 0.00 93.66 0.00 98.03 0.00 82.11 0.95 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_rx.1156240611
89.57 0.16 96.80 0.00 87.73 0.30 96.98 0.00 70.83 0.00 93.66 0.00 98.03 0.00 82.95 0.84 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.2569777685
89.71 0.14 96.83 0.03 87.77 0.04 96.98 0.00 70.83 0.00 93.73 0.07 98.03 0.00 83.79 0.84 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_host_perf.205914595
89.85 0.14 96.92 0.09 87.92 0.15 96.98 0.00 71.43 0.60 93.87 0.14 98.03 0.00 83.79 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/34.i2c_host_error_intr.2862223773
89.97 0.12 97.05 0.12 87.92 0.00 96.98 0.00 72.02 0.60 94.01 0.14 98.03 0.00 83.79 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull.1831416770
90.09 0.12 97.05 0.00 88.03 0.11 96.98 0.00 72.02 0.00 94.01 0.00 98.03 0.00 84.53 0.74 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_fmt.2643914771
90.20 0.11 97.05 0.00 88.03 0.00 96.98 0.00 72.02 0.00 94.01 0.00 98.03 0.00 85.26 0.74 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.3839714296
90.30 0.11 97.05 0.00 88.03 0.00 96.98 0.00 72.02 0.00 94.01 0.00 98.03 0.00 86.00 0.74 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_acq.2384347897
90.39 0.09 97.05 0.00 88.03 0.00 96.98 0.00 72.02 0.00 94.01 0.00 98.03 0.00 86.63 0.63 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_host_may_nack.2416707017
90.48 0.09 97.05 0.00 88.11 0.08 96.98 0.00 72.02 0.00 94.01 0.00 98.03 0.00 87.16 0.53 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_smoke.3255378745
90.55 0.07 97.17 0.12 88.22 0.11 97.22 0.23 72.02 0.00 94.01 0.00 98.03 0.00 87.16 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_alert_test.2253940076
90.61 0.06 97.20 0.03 88.37 0.15 97.22 0.00 72.02 0.00 94.16 0.14 98.03 0.00 87.26 0.11 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_intr_stress_wr.39665941
90.66 0.05 97.20 0.00 88.37 0.00 97.22 0.00 72.02 0.00 94.16 0.00 98.25 0.22 87.37 0.11 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_acq.1388205912
90.70 0.05 97.20 0.00 88.37 0.00 97.22 0.00 72.02 0.00 94.16 0.00 98.25 0.00 87.68 0.32 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.4079997262
90.74 0.04 97.20 0.00 88.45 0.08 97.22 0.00 72.02 0.00 94.16 0.00 98.47 0.22 87.68 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_watermark.3145740061
90.78 0.04 97.20 0.00 88.52 0.08 97.22 0.00 72.02 0.00 94.16 0.00 98.47 0.00 87.89 0.21 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.241310108
90.82 0.04 97.20 0.00 88.67 0.15 97.22 0.00 72.02 0.00 94.16 0.00 98.47 0.00 88.00 0.11 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/10.i2c_host_mode_toggle.254167940
90.85 0.03 97.20 0.00 88.78 0.11 97.22 0.00 72.02 0.00 94.16 0.00 98.47 0.00 88.11 0.11 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_overflow.2351849778
90.88 0.03 97.20 0.00 88.78 0.00 97.22 0.00 72.02 0.00 94.16 0.00 98.47 0.00 88.32 0.21 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/14.i2c_host_may_nack.3037981134
90.91 0.03 97.20 0.00 88.78 0.00 97.22 0.00 72.02 0.00 94.16 0.00 98.47 0.00 88.53 0.21 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_fmt.1524900572
90.94 0.03 97.20 0.00 88.78 0.00 97.22 0.00 72.02 0.00 94.16 0.00 98.47 0.00 88.74 0.21 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_host_may_nack.3769098128
90.97 0.03 97.20 0.00 88.78 0.00 97.22 0.00 72.02 0.00 94.16 0.00 98.47 0.00 88.95 0.21 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_stress_all.2122100378
91.00 0.03 97.20 0.00 88.78 0.00 97.22 0.00 72.02 0.00 94.16 0.00 98.47 0.00 89.16 0.21 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_host_may_nack.2302787504
91.02 0.02 97.20 0.00 88.93 0.15 97.22 0.00 72.02 0.00 94.16 0.00 98.47 0.00 89.16 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.2913626171
91.04 0.02 97.20 0.00 89.09 0.15 97.22 0.00 72.02 0.00 94.16 0.00 98.47 0.00 89.16 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_host_error_intr.1383891884
91.06 0.02 97.20 0.00 89.20 0.11 97.22 0.00 72.02 0.00 94.16 0.00 98.47 0.00 89.16 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.2542372597
91.08 0.02 97.20 0.00 89.24 0.04 97.22 0.00 72.02 0.00 94.23 0.07 98.47 0.00 89.16 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/32.i2c_host_perf.3869875971
91.09 0.02 97.20 0.00 89.24 0.00 97.22 0.00 72.02 0.00 94.23 0.00 98.47 0.00 89.26 0.11 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.3472720713
91.11 0.02 97.20 0.00 89.24 0.00 97.22 0.00 72.02 0.00 94.23 0.00 98.47 0.00 89.37 0.11 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_stress_rd.3577945410
91.12 0.02 97.20 0.00 89.24 0.00 97.22 0.00 72.02 0.00 94.23 0.00 98.47 0.00 89.47 0.11 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_tx_stretch_ctrl.2177269364
91.14 0.02 97.20 0.00 89.24 0.00 97.22 0.00 72.02 0.00 94.23 0.00 98.47 0.00 89.58 0.11 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/10.i2c_host_stretch_timeout.3181243593
91.15 0.01 97.20 0.00 89.31 0.08 97.22 0.00 72.02 0.00 94.23 0.00 98.47 0.00 89.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/12.i2c_host_may_nack.2306540231
91.16 0.01 97.23 0.03 89.35 0.04 97.22 0.00 72.02 0.00 94.23 0.00 98.47 0.00 89.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.3214821087
91.16 0.01 97.23 0.00 89.39 0.04 97.22 0.00 72.02 0.00 94.23 0.00 98.47 0.00 89.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.3369710160
91.17 0.01 97.23 0.00 89.42 0.04 97.22 0.00 72.02 0.00 94.23 0.00 98.47 0.00 89.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_hrst.3728041739
91.17 0.01 97.23 0.00 89.46 0.04 97.22 0.00 72.02 0.00 94.23 0.00 98.47 0.00 89.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/12.i2c_host_mode_toggle.2961658879
91.18 0.01 97.23 0.00 89.50 0.04 97.22 0.00 72.02 0.00 94.23 0.00 98.47 0.00 89.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/15.i2c_host_mode_toggle.4123939103

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.262404167
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.1234186290
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2646044429
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.3436580714
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.3857426837
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2691027847
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.3997899685
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.843522017
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.4095284171
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.2716315976
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.129456944
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.678510219
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.3568507533
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3045834776
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.1080175107
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.1891189240
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2112239793
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.2471367963
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.1783666774
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1282340149
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.2438491815
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1944793175
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.807657371
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.1253065058
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2424359189
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.2378918786
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.1688578156
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.751666384
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.4042590618
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.797479731
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.724903533
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.1552518428
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1904299253
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.1877559553
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.2840470385
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1203493797
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.1314523490
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.115482398
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2743959574
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.1386180344
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3994997227
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.415897112
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3370467277
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.3662784373
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Total test records in report: 1848
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_host_override.3391092205 Oct 09 08:05:14 AM UTC 24 Oct 09 08:05:16 AM UTC 24 38847053 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_host_smoke.3813437578 Oct 09 08:05:11 AM UTC 24 Oct 09 08:05:53 AM UTC 24 13013452808 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_fmt.1613952771 Oct 09 08:05:54 AM UTC 24 Oct 09 08:05:57 AM UTC 24 832335823 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_rx.2121916466 Oct 09 08:06:01 AM UTC 24 Oct 09 08:06:10 AM UTC 24 340585078 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_fmt_empty.1074900210 Oct 09 08:05:58 AM UTC 24 Oct 09 08:06:12 AM UTC 24 497174048 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_overflow.601309742 Oct 09 08:05:28 AM UTC 24 Oct 09 08:06:17 AM UTC 24 3189896460 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_host_perf_precise.4214702645 Oct 09 08:06:15 AM UTC 24 Oct 09 08:06:21 AM UTC 24 83837947 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_host_error_intr.3325407428 Oct 09 08:06:22 AM UTC 24 Oct 09 08:06:26 AM UTC 24 121719133 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_host_stretch_timeout.1516401695 Oct 09 08:06:18 AM UTC 24 Oct 09 08:06:31 AM UTC 24 2637929196 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_glitch.3076280949 Oct 09 08:06:32 AM UTC 24 Oct 09 08:06:46 AM UTC 24 4469888481 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_host_perf.3450370867 Oct 09 08:06:13 AM UTC 24 Oct 09 08:07:00 AM UTC 24 6779884434 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_smoke.3255378745 Oct 09 08:06:47 AM UTC 24 Oct 09 08:07:07 AM UTC 24 1344696426 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_intr_smoke.3670938457 Oct 09 08:07:08 AM UTC 24 Oct 09 08:07:24 AM UTC 24 4494434012 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_full.802768525 Oct 09 08:06:11 AM UTC 24 Oct 09 08:07:24 AM UTC 24 2425141404 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_acq.717591605 Oct 09 08:07:30 AM UTC 24 Oct 09 08:07:34 AM UTC 24 433168187 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_stretch.1393175776 Oct 09 08:07:01 AM UTC 24 Oct 09 08:07:35 AM UTC 24 3737623936 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_tx.849029527 Oct 09 08:07:33 AM UTC 24 Oct 09 08:07:36 AM UTC 24 166006645 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_timeout.568595729 Oct 09 08:07:25 AM UTC 24 Oct 09 08:07:37 AM UTC 24 5328284187 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_hrst.3728041739 Oct 09 08:07:37 AM UTC 24 Oct 09 08:07:42 AM UTC 24 1163505379 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_perf.3809224970 Oct 09 08:07:35 AM UTC 24 Oct 09 08:07:45 AM UTC 24 849828082 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_bad_addr.4107381473 Oct 09 08:07:37 AM UTC 24 Oct 09 08:07:46 AM UTC 24 1443286038 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_fmt.1978178366 Oct 09 08:10:13 AM UTC 24 Oct 09 08:10:15 AM UTC 24 371337486 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_stress_wr.3563054211 Oct 09 08:06:59 AM UTC 24 Oct 09 08:07:50 AM UTC 24 23884179820 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_tx.666265714 Oct 09 08:07:58 AM UTC 24 Oct 09 08:08:00 AM UTC 24 293244704 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_smbus_maxlen.2973799546 Oct 09 08:07:58 AM UTC 24 Oct 09 08:08:02 AM UTC 24 1704414027 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_tx_stretch_ctrl.2177269364 Oct 09 08:07:58 AM UTC 24 Oct 09 08:08:03 AM UTC 24 175431512 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_acq.1264963920 Oct 09 08:07:58 AM UTC 24 Oct 09 08:08:03 AM UTC 24 1965804999 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull.1070500049 Oct 09 08:07:58 AM UTC 24 Oct 09 08:08:04 AM UTC 24 556680959 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_watermark.134715897 Oct 09 08:05:17 AM UTC 24 Oct 09 08:08:06 AM UTC 24 94423275212 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_alert_test.2253940076 Oct 09 08:08:04 AM UTC 24 Oct 09 08:08:06 AM UTC 24 43179543 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull_addr.3284589273 Oct 09 08:08:01 AM UTC 24 Oct 09 08:08:07 AM UTC 24 7175523535 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_sec_cm.2098998768 Oct 09 08:08:04 AM UTC 24 Oct 09 08:08:07 AM UTC 24 404123848 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_nack_txstretch.954788285 Oct 09 08:08:03 AM UTC 24 Oct 09 08:08:07 AM UTC 24 168523888 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_intr_stress_wr.1755014977 Oct 09 08:07:19 AM UTC 24 Oct 09 08:08:07 AM UTC 24 20131277167 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_host_override.3062162851 Oct 09 08:08:06 AM UTC 24 Oct 09 08:08:08 AM UTC 24 39321592 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_host_may_nack.2299788596 Oct 09 08:07:57 AM UTC 24 Oct 09 08:08:09 AM UTC 24 421312776 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_fmt.2643914771 Oct 09 08:08:08 AM UTC 24 Oct 09 08:08:10 AM UTC 24 498090820 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_host_override.2040547351 Oct 09 08:10:10 AM UTC 24 Oct 09 08:10:13 AM UTC 24 26411230 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_rx.2591470834 Oct 09 08:08:09 AM UTC 24 Oct 09 08:08:18 AM UTC 24 409490908 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_fmt_empty.4027097097 Oct 09 08:08:08 AM UTC 24 Oct 09 08:08:22 AM UTC 24 205188947 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_stress_rd.3577945410 Oct 09 08:07:00 AM UTC 24 Oct 09 08:08:22 AM UTC 24 7771968509 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_host_error_intr.1383891884 Oct 09 08:08:19 AM UTC 24 Oct 09 08:08:23 AM UTC 24 180445171 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_glitch.3329415874 Oct 09 08:08:23 AM UTC 24 Oct 09 08:08:37 AM UTC 24 10427916084 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_smoke.1819052301 Oct 09 08:08:24 AM UTC 24 Oct 09 08:08:47 AM UTC 24 9758975802 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_host_smoke.2114564872 Oct 09 08:08:05 AM UTC 24 Oct 09 08:08:51 AM UTC 24 1673948537 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_host_stretch_timeout.3371197680 Oct 09 08:08:19 AM UTC 24 Oct 09 08:09:06 AM UTC 24 734248114 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_intr_smoke.618656583 Oct 09 08:09:07 AM UTC 24 Oct 09 08:09:14 AM UTC 24 2298967293 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_watermark.306634881 Oct 09 08:08:07 AM UTC 24 Oct 09 08:09:40 AM UTC 24 54761545574 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_timeout.2071071259 Oct 09 08:09:32 AM UTC 24 Oct 09 08:09:43 AM UTC 24 1226634358 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_full.2650971387 Oct 09 08:08:10 AM UTC 24 Oct 09 08:09:43 AM UTC 24 7150524395 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_acq.48121549 Oct 09 08:09:41 AM UTC 24 Oct 09 08:09:44 AM UTC 24 446715871 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_tx.2380832444 Oct 09 08:09:43 AM UTC 24 Oct 09 08:09:46 AM UTC 24 252768674 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_stress_wr.3634550192 Oct 09 08:08:38 AM UTC 24 Oct 09 08:09:46 AM UTC 24 25917049851 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_hrst.2000166769 Oct 09 08:09:47 AM UTC 24 Oct 09 08:09:51 AM UTC 24 234770820 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_perf.740505559 Oct 09 08:09:44 AM UTC 24 Oct 09 08:09:54 AM UTC 24 1756531788 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_bad_addr.3510418725 Oct 09 08:09:45 AM UTC 24 Oct 09 08:09:55 AM UTC 24 1037190199 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_stress_rd.1836084648 Oct 09 08:08:49 AM UTC 24 Oct 09 08:10:01 AM UTC 24 4819461270 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_acq.2797125507 Oct 09 08:09:57 AM UTC 24 Oct 09 08:10:02 AM UTC 24 1572799668 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_tx.4088597045 Oct 09 08:10:00 AM UTC 24 Oct 09 08:10:03 AM UTC 24 284782644 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull_addr.1130350637 Oct 09 08:10:08 AM UTC 24 Oct 09 08:10:13 AM UTC 24 3025394339 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_smbus_maxlen.318971094 Oct 09 08:10:03 AM UTC 24 Oct 09 08:10:07 AM UTC 24 662420997 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_tx_stretch_ctrl.2307428625 Oct 09 08:10:02 AM UTC 24 Oct 09 08:10:08 AM UTC 24 136534718 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_overflow.3340358850 Oct 09 08:08:07 AM UTC 24 Oct 09 08:10:08 AM UTC 24 3364493156 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_host_perf.4014909040 Oct 09 08:08:10 AM UTC 24 Oct 09 08:10:08 AM UTC 24 29458670808 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull.3241195758 Oct 09 08:10:04 AM UTC 24 Oct 09 08:10:09 AM UTC 24 598314023 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_perf.2452253761 Oct 09 08:11:33 AM UTC 24 Oct 09 08:11:42 AM UTC 24 635503887 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_intr_stress_wr.39665941 Oct 09 08:09:15 AM UTC 24 Oct 09 08:10:11 AM UTC 24 21085278299 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_alert_test.2316894544 Oct 09 08:10:09 AM UTC 24 Oct 09 08:10:11 AM UTC 24 14877393 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_nack_txstretch.1616263873 Oct 09 08:10:08 AM UTC 24 Oct 09 08:10:11 AM UTC 24 496354567 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_sec_cm.87382082 Oct 09 08:10:09 AM UTC 24 Oct 09 08:10:12 AM UTC 24 39152901 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_rx.1156240611 Oct 09 08:10:14 AM UTC 24 Oct 09 08:10:26 AM UTC 24 888410046 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_host_may_nack.3661462224 Oct 09 08:09:57 AM UTC 24 Oct 09 08:10:28 AM UTC 24 2037691386 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_fmt_empty.3786816859 Oct 09 08:10:13 AM UTC 24 Oct 09 08:10:28 AM UTC 24 476237246 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_host_error_intr.839514023 Oct 09 08:10:29 AM UTC 24 Oct 09 08:10:33 AM UTC 24 326081025 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_host_perf_precise.3447432552 Oct 09 08:10:27 AM UTC 24 Oct 09 08:10:37 AM UTC 24 412211863 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_smoke.3128957384 Oct 09 08:10:34 AM UTC 24 Oct 09 08:10:52 AM UTC 24 2473082030 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_host_smoke.1909841314 Oct 09 08:10:09 AM UTC 24 Oct 09 08:10:58 AM UTC 24 32845209126 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_intr_smoke.2153657860 Oct 09 08:10:59 AM UTC 24 Oct 09 08:11:09 AM UTC 24 1589237784 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_stretch.1986165173 Oct 09 08:10:53 AM UTC 24 Oct 09 08:11:19 AM UTC 24 3208350444 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_host_stretch_timeout.3258947241 Oct 09 08:10:28 AM UTC 24 Oct 09 08:11:24 AM UTC 24 816873072 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_acq.1022620019 Oct 09 08:11:29 AM UTC 24 Oct 09 08:11:32 AM UTC 24 157733044 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_stress_rd.2083159353 Oct 09 08:10:38 AM UTC 24 Oct 09 08:11:32 AM UTC 24 922373731 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_timeout.1029899474 Oct 09 08:11:20 AM UTC 24 Oct 09 08:11:33 AM UTC 24 6272899696 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_tx.1318234073 Oct 09 08:11:32 AM UTC 24 Oct 09 08:11:35 AM UTC 24 259348333 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_bad_addr.4119965058 Oct 09 08:11:35 AM UTC 24 Oct 09 08:11:46 AM UTC 24 943710873 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_hrst.1693586059 Oct 09 08:11:43 AM UTC 24 Oct 09 08:11:48 AM UTC 24 1177251359 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/1.i2c_target_stress_all.3370951454 Oct 09 08:09:44 AM UTC 24 Oct 09 08:11:54 AM UTC 24 49105967697 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_host_may_nack.2416707017 Oct 09 08:12:00 AM UTC 24 Oct 09 08:12:08 AM UTC 24 837899040 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_stress_all.2334090848 Oct 09 08:11:33 AM UTC 24 Oct 09 08:12:09 AM UTC 24 10825127190 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_overflow.2505007686 Oct 09 08:10:13 AM UTC 24 Oct 09 08:12:11 AM UTC 24 5854013962 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_acq.3959625549 Oct 09 08:12:09 AM UTC 24 Oct 09 08:12:13 AM UTC 24 924185076 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_tx.291766582 Oct 09 08:12:10 AM UTC 24 Oct 09 08:12:13 AM UTC 24 601190711 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_smbus_maxlen.1423381108 Oct 09 08:12:14 AM UTC 24 Oct 09 08:12:19 AM UTC 24 415562482 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_tx_stretch_ctrl.3856075888 Oct 09 08:12:11 AM UTC 24 Oct 09 08:12:19 AM UTC 24 403119026 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull.3715125305 Oct 09 08:12:14 AM UTC 24 Oct 09 08:12:20 AM UTC 24 6068701790 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_alert_test.38160622 Oct 09 08:12:21 AM UTC 24 Oct 09 08:12:22 AM UTC 24 37376190 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_sec_cm.3071300615 Oct 09 08:12:20 AM UTC 24 Oct 09 08:12:23 AM UTC 24 74533093 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_host_override.2232494633 Oct 09 08:12:24 AM UTC 24 Oct 09 08:12:26 AM UTC 24 30947054 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull_addr.4179097145 Oct 09 08:12:20 AM UTC 24 Oct 09 08:12:27 AM UTC 24 931286536 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_fmt.714767884 Oct 09 08:12:27 AM UTC 24 Oct 09 08:12:30 AM UTC 24 88548938 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_rx.744635307 Oct 09 08:12:30 AM UTC 24 Oct 09 08:12:37 AM UTC 24 132108068 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_target_stress_all.2765898624 Oct 09 08:07:35 AM UTC 24 Oct 09 08:12:44 AM UTC 24 35716743222 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_stress_wr.1761532109 Oct 09 08:10:37 AM UTC 24 Oct 09 08:12:45 AM UTC 24 46935000247 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_fmt_empty.3719251429 Oct 09 08:12:27 AM UTC 24 Oct 09 08:12:45 AM UTC 24 574291787 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_host_smoke.1876044803 Oct 09 08:12:22 AM UTC 24 Oct 09 08:12:45 AM UTC 24 5150276887 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_host_error_intr.1282625202 Oct 09 08:12:46 AM UTC 24 Oct 09 08:12:50 AM UTC 24 181725548 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_host_perf_precise.2378939704 Oct 09 08:12:45 AM UTC 24 Oct 09 08:12:51 AM UTC 24 235460583 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_full.4050249802 Oct 09 08:10:14 AM UTC 24 Oct 09 08:12:54 AM UTC 24 4618379519 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_target_intr_stress_wr.1061667654 Oct 09 08:11:10 AM UTC 24 Oct 09 08:13:00 AM UTC 24 15018490935 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_host_stretch_timeout.2752857688 Oct 09 08:12:46 AM UTC 24 Oct 09 08:13:06 AM UTC 24 694507146 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_timeout.1789648351 Oct 09 08:13:02 AM UTC 24 Oct 09 08:13:14 AM UTC 24 7128131724 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_stretch.2872898364 Oct 09 08:13:00 AM UTC 24 Oct 09 08:13:14 AM UTC 24 1951752869 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_acq.3088423989 Oct 09 08:13:11 AM UTC 24 Oct 09 08:13:15 AM UTC 24 184647035 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_intr_smoke.797489933 Oct 09 08:13:00 AM UTC 24 Oct 09 08:13:16 AM UTC 24 30096202555 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_tx.142064944 Oct 09 08:13:14 AM UTC 24 Oct 09 08:13:17 AM UTC 24 238664672 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_overflow.1980309447 Oct 09 08:12:25 AM UTC 24 Oct 09 08:13:18 AM UTC 24 8161952650 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_smoke.3023833059 Oct 09 08:12:51 AM UTC 24 Oct 09 08:13:21 AM UTC 24 7682774884 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_perf.4164330472 Oct 09 08:13:16 AM UTC 24 Oct 09 08:13:22 AM UTC 24 947574715 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_bad_addr.2966770397 Oct 09 08:13:17 AM UTC 24 Oct 09 08:13:28 AM UTC 24 1260441622 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_tx.1972719152 Oct 09 08:13:29 AM UTC 24 Oct 09 08:13:33 AM UTC 24 617629265 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_stress_wr.2112025833 Oct 09 08:12:52 AM UTC 24 Oct 09 08:13:34 AM UTC 24 31886283673 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_host_may_nack.3457854802 Oct 09 08:13:26 AM UTC 24 Oct 09 08:13:34 AM UTC 24 385001926 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_acq.2384347897 Oct 09 08:13:29 AM UTC 24 Oct 09 08:13:36 AM UTC 24 522883409 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_smbus_maxlen.608339697 Oct 09 08:13:35 AM UTC 24 Oct 09 08:13:40 AM UTC 24 547672677 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull_addr.3195901818 Oct 09 08:13:37 AM UTC 24 Oct 09 08:13:40 AM UTC 24 1492643477 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull.2214702874 Oct 09 08:13:35 AM UTC 24 Oct 09 08:13:40 AM UTC 24 495193408 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_tx_stretch_ctrl.507183746 Oct 09 08:13:34 AM UTC 24 Oct 09 08:13:41 AM UTC 24 199431942 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_intr_stress_wr.1208359398 Oct 09 08:13:01 AM UTC 24 Oct 09 08:13:42 AM UTC 24 21860559114 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_alert_test.1197235091 Oct 09 08:13:41 AM UTC 24 Oct 09 08:13:43 AM UTC 24 14780739 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_sec_cm.597032848 Oct 09 08:15:04 AM UTC 24 Oct 09 08:15:06 AM UTC 24 270917026 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_sec_cm.3779132137 Oct 09 08:13:41 AM UTC 24 Oct 09 08:13:43 AM UTC 24 123050127 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_overflow.2351849778 Oct 09 08:13:44 AM UTC 24 Oct 09 08:15:08 AM UTC 24 10475117235 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_host_override.1527756946 Oct 09 08:13:43 AM UTC 24 Oct 09 08:13:45 AM UTC 24 29688837 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_host_perf.2693678758 Oct 09 08:15:12 AM UTC 24 Oct 09 08:15:28 AM UTC 24 1029913286 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_fmt.3452355296 Oct 09 08:13:44 AM UTC 24 Oct 09 08:13:47 AM UTC 24 121879845 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_host_perf_precise.1473779020 Oct 09 08:13:49 AM UTC 24 Oct 09 08:13:53 AM UTC 24 311608671 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_stress_rd.2778434107 Oct 09 08:12:55 AM UTC 24 Oct 09 08:13:55 AM UTC 24 1295503042 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_host_error_intr.1784791875 Oct 09 08:13:59 AM UTC 24 Oct 09 08:14:02 AM UTC 24 90217793 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/0.i2c_host_stress_all.3281781287 Oct 09 08:06:26 AM UTC 24 Oct 09 08:14:06 AM UTC 24 22951330014 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_rx.935067333 Oct 09 08:13:48 AM UTC 24 Oct 09 08:14:06 AM UTC 24 216182927 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_host_stretch_timeout.3129135215 Oct 09 08:13:59 AM UTC 24 Oct 09 08:14:09 AM UTC 24 1797961144 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_fmt_empty.3507251702 Oct 09 08:13:48 AM UTC 24 Oct 09 08:14:11 AM UTC 24 612897825 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_stress_wr.3152106045 Oct 09 08:14:07 AM UTC 24 Oct 09 08:14:18 AM UTC 24 8816880786 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_target_stress_all.2707035876 Oct 09 08:13:16 AM UTC 24 Oct 09 08:14:19 AM UTC 24 33156147184 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_intr_smoke.2923616591 Oct 09 08:14:11 AM UTC 24 Oct 09 08:14:19 AM UTC 24 2941592327 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull.4227432890 Oct 09 08:15:02 AM UTC 24 Oct 09 08:15:08 AM UTC 24 2152272816 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_watermark.909496373 Oct 09 08:10:11 AM UTC 24 Oct 09 08:14:26 AM UTC 24 9466246010 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_stretch.1477887977 Oct 09 08:14:10 AM UTC 24 Oct 09 08:14:29 AM UTC 24 3033061590 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_acq.2131814348 Oct 09 08:14:27 AM UTC 24 Oct 09 08:14:29 AM UTC 24 187613848 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_tx.4250620793 Oct 09 08:14:27 AM UTC 24 Oct 09 08:14:30 AM UTC 24 442249650 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_timeout.419180739 Oct 09 08:14:19 AM UTC 24 Oct 09 08:14:33 AM UTC 24 1219977012 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_bad_addr.645745832 Oct 09 08:14:31 AM UTC 24 Oct 09 08:14:38 AM UTC 24 1207519044 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_full.4102117838 Oct 09 08:13:49 AM UTC 24 Oct 09 08:14:41 AM UTC 24 8692984944 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_perf.3470240163 Oct 09 08:14:30 AM UTC 24 Oct 09 08:14:42 AM UTC 24 1309491114 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_host_smoke.1952284969 Oct 09 08:13:42 AM UTC 24 Oct 09 08:15:30 AM UTC 24 7391178812 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_host_may_nack.1394679473 Oct 09 08:14:50 AM UTC 24 Oct 09 08:14:56 AM UTC 24 1479719479 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_smoke.331470593 Oct 09 08:14:03 AM UTC 24 Oct 09 08:15:00 AM UTC 24 1198748787 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_tx.2059562425 Oct 09 08:14:58 AM UTC 24 Oct 09 08:15:01 AM UTC 24 336908845 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_host_perf.124210263 Oct 09 08:12:43 AM UTC 24 Oct 09 08:15:02 AM UTC 24 6493140749 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_acq.3143773284 Oct 09 08:14:58 AM UTC 24 Oct 09 08:15:03 AM UTC 24 439640369 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_tx_stretch_ctrl.3898624729 Oct 09 08:14:58 AM UTC 24 Oct 09 08:15:03 AM UTC 24 152064764 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_stress_rd.494778200 Oct 09 08:14:07 AM UTC 24 Oct 09 08:15:04 AM UTC 24 887465368 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_smbus_maxlen.2722125 Oct 09 08:15:01 AM UTC 24 Oct 09 08:15:06 AM UTC 24 2119296464 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_alert_test.1645688202 Oct 09 08:15:05 AM UTC 24 Oct 09 08:15:07 AM UTC 24 26382982 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_nack_txstretch.3746970840 Oct 09 08:15:04 AM UTC 24 Oct 09 08:15:08 AM UTC 24 263936821 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull_addr.756618153 Oct 09 08:15:03 AM UTC 24 Oct 09 08:15:08 AM UTC 24 1945509312 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_host_override.3930079872 Oct 09 08:15:07 AM UTC 24 Oct 09 08:15:10 AM UTC 24 50090102 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_fmt.2950380502 Oct 09 08:15:09 AM UTC 24 Oct 09 08:15:11 AM UTC 24 63950026 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_rx.1609985426 Oct 09 08:15:10 AM UTC 24 Oct 09 08:15:21 AM UTC 24 167475756 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_host_smoke.40715912 Oct 09 08:16:02 AM UTC 24 Oct 09 08:17:47 AM UTC 24 7492811953 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_host_perf_precise.1071861150 Oct 09 08:15:19 AM UTC 24 Oct 09 08:15:23 AM UTC 24 165952671 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_fmt_empty.3224752041 Oct 09 08:15:09 AM UTC 24 Oct 09 08:15:24 AM UTC 24 820344684 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_watermark.895177009 Oct 09 08:12:24 AM UTC 24 Oct 09 08:15:25 AM UTC 24 19692958070 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_full.4197778982 Oct 09 08:12:38 AM UTC 24 Oct 09 08:15:27 AM UTC 24 28856942639 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_host_error_intr.1067479242 Oct 09 08:15:23 AM UTC 24 Oct 09 08:15:33 AM UTC 24 720193950 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_host_stretch_timeout.2019285198 Oct 09 08:15:21 AM UTC 24 Oct 09 08:15:36 AM UTC 24 603940247 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_host_smoke.2858389851 Oct 09 08:15:07 AM UTC 24 Oct 09 08:15:36 AM UTC 24 2828363483 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_target_smoke.1063201619 Oct 09 08:15:24 AM UTC 24 Oct 09 08:15:38 AM UTC 24 3743334690 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_target_intr_smoke.927597771 Oct 09 08:15:31 AM UTC 24 Oct 09 08:15:39 AM UTC 24 691852317 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_target_hrst.2791219451 Oct 09 08:17:51 AM UTC 24 Oct 09 08:17:55 AM UTC 24 289237850 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_acq.2273943129 Oct 09 08:15:38 AM UTC 24 Oct 09 08:15:41 AM UTC 24 240612610 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_tx.1555507456 Oct 09 08:15:39 AM UTC 24 Oct 09 08:15:42 AM UTC 24 599939586 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_target_stretch.3986968847 Oct 09 08:15:29 AM UTC 24 Oct 09 08:15:44 AM UTC 24 1717013667 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_target_intr_stress_wr.1807498388 Oct 09 08:15:34 AM UTC 24 Oct 09 08:15:48 AM UTC 24 20297576737 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_target_hrst.4030785408 Oct 09 08:15:43 AM UTC 24 Oct 09 08:15:49 AM UTC 24 339004924 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_target_perf.727703634 Oct 09 08:15:42 AM UTC 24 Oct 09 08:15:49 AM UTC 24 1273052864 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_target_timeout.2524441509 Oct 09 08:15:37 AM UTC 24 Oct 09 08:15:51 AM UTC 24 2820473478 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_target_bad_addr.1703717890 Oct 09 08:15:42 AM UTC 24 Oct 09 08:15:55 AM UTC 24 1531815811 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_tx.3700269591 Oct 09 08:15:55 AM UTC 24 Oct 09 08:15:58 AM UTC 24 416565130 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_target_timeout.1070919167 Oct 09 08:17:45 AM UTC 24 Oct 09 08:17:55 AM UTC 24 1321203748 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_acq.277693870 Oct 09 08:15:55 AM UTC 24 Oct 09 08:15:58 AM UTC 24 226901405 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_intr_stress_wr.2544234836 Oct 09 08:14:18 AM UTC 24 Oct 09 08:15:59 AM UTC 24 24241030225 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_target_tx_stretch_ctrl.3278282083 Oct 09 08:15:56 AM UTC 24 Oct 09 08:16:00 AM UTC 24 54297636 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_alert_test.2965456326 Oct 09 08:16:00 AM UTC 24 Oct 09 08:16:02 AM UTC 24 45930314 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_host_may_nack.2541086992 Oct 09 08:15:55 AM UTC 24 Oct 09 08:16:02 AM UTC 24 554345468 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_target_stress_rd.635375399 Oct 09 08:15:28 AM UTC 24 Oct 09 08:16:02 AM UTC 24 17394747534 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_target_smbus_maxlen.163683602 Oct 09 08:15:59 AM UTC 24 Oct 09 08:16:03 AM UTC 24 884535307 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull.942054460 Oct 09 08:15:59 AM UTC 24 Oct 09 08:16:03 AM UTC 24 424675003 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_target_stress_rd.2918397038 Oct 09 08:17:35 AM UTC 24 Oct 09 08:17:45 AM UTC 24 200003724 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_target_stretch.3275061713 Oct 09 08:17:42 AM UTC 24 Oct 09 08:17:51 AM UTC 24 1284355551 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull_addr.661755932 Oct 09 08:15:59 AM UTC 24 Oct 09 08:16:04 AM UTC 24 817583675 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_host_override.4176817572 Oct 09 08:16:03 AM UTC 24 Oct 09 08:16:05 AM UTC 24 38348542 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_fmt.662520043 Oct 09 08:16:04 AM UTC 24 Oct 09 08:16:07 AM UTC 24 97820667 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_rx.3421609778 Oct 09 08:16:05 AM UTC 24 Oct 09 08:16:14 AM UTC 24 199869074 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_fmt_empty.191243821 Oct 09 08:16:04 AM UTC 24 Oct 09 08:16:15 AM UTC 24 809701939 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_full.1468941272 Oct 09 08:15:11 AM UTC 24 Oct 09 08:16:16 AM UTC 24 4605144914 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_target_stress_wr.1316423917 Oct 09 08:15:26 AM UTC 24 Oct 09 08:16:16 AM UTC 24 68958839473 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_host_error_intr.2953998026 Oct 09 08:16:15 AM UTC 24 Oct 09 08:16:18 AM UTC 24 339909957 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_target_stretch.3304913623 Oct 09 08:16:22 AM UTC 24 Oct 09 08:16:27 AM UTC 24 1441944842 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_host_stretch_timeout.3896136862 Oct 09 08:16:09 AM UTC 24 Oct 09 08:16:28 AM UTC 24 7623744130 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_overflow.2469877165 Oct 09 08:15:09 AM UTC 24 Oct 09 08:16:32 AM UTC 24 9169104521 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_target_stress_rd.3600175718 Oct 09 08:16:19 AM UTC 24 Oct 09 08:16:35 AM UTC 24 2921646121 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_target_intr_smoke.2279235595 Oct 09 08:16:28 AM UTC 24 Oct 09 08:16:36 AM UTC 24 821450060 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_acq.813445812 Oct 09 08:16:36 AM UTC 24 Oct 09 08:16:39 AM UTC 24 112564668 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_target_perf.4129760155 Oct 09 08:17:49 AM UTC 24 Oct 09 08:17:56 AM UTC 24 586445572 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_tx.1039148740 Oct 09 08:16:37 AM UTC 24 Oct 09 08:16:40 AM UTC 24 288091064 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_target_perf.1675827057 Oct 09 08:16:39 AM UTC 24 Oct 09 08:16:47 AM UTC 24 2691767821 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_target_bad_addr.3768794785 Oct 09 08:16:41 AM UTC 24 Oct 09 08:16:48 AM UTC 24 1458044535 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_target_timeout.2846990318 Oct 09 08:16:36 AM UTC 24 Oct 09 08:16:50 AM UTC 24 20349393550 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_target_smoke.591522194 Oct 09 08:16:17 AM UTC 24 Oct 09 08:16:54 AM UTC 24 1010083500 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_watermark.2187012122 Oct 09 08:15:09 AM UTC 24 Oct 09 08:16:55 AM UTC 24 10243393360 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_acq.47861386 Oct 09 08:16:56 AM UTC 24 Oct 09 08:17:00 AM UTC 24 535399895 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_target_intr_stress_wr.238429028 Oct 09 08:17:44 AM UTC 24 Oct 09 08:17:48 AM UTC 24 567217726 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_host_may_nack.567548241 Oct 09 08:16:55 AM UTC 24 Oct 09 08:17:06 AM UTC 24 1995524497 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_target_stress_all.2492199775 Oct 09 08:16:41 AM UTC 24 Oct 09 08:17:07 AM UTC 24 14017557185 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_target_tx_stretch_ctrl.3955758003 Oct 09 08:17:01 AM UTC 24 Oct 09 08:17:09 AM UTC 24 336488603 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_target_intr_smoke.3524926389 Oct 09 08:17:42 AM UTC 24 Oct 09 08:17:50 AM UTC 24 608142569 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_target_smbus_maxlen.1339061437 Oct 09 08:17:04 AM UTC 24 Oct 09 08:17:10 AM UTC 24 607478456 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_acq.29243666 Oct 09 08:17:47 AM UTC 24 Oct 09 08:17:50 AM UTC 24 158671845 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull_addr.3021537838 Oct 09 08:17:07 AM UTC 24 Oct 09 08:17:11 AM UTC 24 2223502659 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull.3402872367 Oct 09 08:17:07 AM UTC 24 Oct 09 08:17:12 AM UTC 24 598674774 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_alert_test.1355062944 Oct 09 08:17:10 AM UTC 24 Oct 09 08:17:12 AM UTC 24 129149078 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_host_override.143203660 Oct 09 08:17:11 AM UTC 24 Oct 09 08:17:13 AM UTC 24 106139579 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_fmt.2229958553 Oct 09 08:17:12 AM UTC 24 Oct 09 08:17:15 AM UTC 24 93428928 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_watermark.3868618440 Oct 09 08:13:44 AM UTC 24 Oct 09 08:17:21 AM UTC 24 3893254409 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_fmt_empty.1417811153 Oct 09 08:17:13 AM UTC 24 Oct 09 08:17:22 AM UTC 24 2567063498 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_rx.135160564 Oct 09 08:17:14 AM UTC 24 Oct 09 08:17:30 AM UTC 24 211250596 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_full.3613615352 Oct 09 08:16:05 AM UTC 24 Oct 09 08:17:31 AM UTC 24 17868681690 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_host_perf.4157400312 Oct 09 08:17:22 AM UTC 24 Oct 09 08:17:33 AM UTC 24 804189563 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_host_error_intr.1919765512 Oct 09 08:17:31 AM UTC 24 Oct 09 08:17:34 AM UTC 24 77198300 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_host_stretch_timeout.1107502680 Oct 09 08:17:31 AM UTC 24 Oct 09 08:17:41 AM UTC 24 2318846467 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_target_intr_stress_wr.1008539755 Oct 09 08:16:36 AM UTC 24 Oct 09 08:17:43 AM UTC 24 22614919521 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_host_perf.205914595 Oct 09 08:16:05 AM UTC 24 Oct 09 08:17:44 AM UTC 24 27855974453 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_target_smoke.1880108808 Oct 09 08:17:32 AM UTC 24 Oct 09 08:17:47 AM UTC 24 861886348 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_target_bad_addr.1409423703 Oct 09 08:17:51 AM UTC 24 Oct 09 08:18:00 AM UTC 24 1221437254 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_tx.4169934592 Oct 09 08:17:48 AM UTC 24 Oct 09 08:17:51 AM UTC 24 235509581 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/6.i2c_target_stress_wr.336425919 Oct 09 08:16:18 AM UTC 24 Oct 09 08:17:59 AM UTC 24 33808686616 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_acq.3650054076 Oct 09 08:17:57 AM UTC 24 Oct 09 08:18:01 AM UTC 24 1441940893 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_tx.546497766 Oct 09 08:17:59 AM UTC 24 Oct 09 08:18:02 AM UTC 24 614394932 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_target_tx_stretch_ctrl.3303805369 Oct 09 08:18:00 AM UTC 24 Oct 09 08:18:04 AM UTC 24 131473010 ps
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