Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	710455	1			T1	1		T2	229		T3	2
all_pins[1]	710455	1			T1	1		T2	229		T3	2
all_pins[2]	710455	1			T1	1		T2	229		T3	2
all_pins[3]	710455	1			T1	1		T2	229		T3	2
all_pins[4]	710455	1			T1	1		T2	229		T3	2
all_pins[5]	710455	1			T1	1		T2	229		T3	2
all_pins[6]	710455	1			T1	1		T2	229		T3	2
all_pins[7]	710455	1			T1	1		T2	229		T3	2
all_pins[8]	710455	1			T1	1		T2	229		T3	2
all_pins[9]	710455	1			T1	1		T2	229		T3	2
all_pins[10]	710455	1			T1	1		T2	229		T3	2
all_pins[11]	710455	1			T1	1		T2	229		T3	2
all_pins[12]	710455	1			T1	1		T2	229		T3	2
all_pins[13]	710455	1			T1	1		T2	229		T3	2
all_pins[14]	710455	1			T1	1		T2	229		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8765567	1			T1	15		T2	2924		T3	30
values[0x1]	1891258	1			T2	511		T4	6		T5	6
transitions[0x0=>0x1]	1890647	1			T2	511		T4	6		T5	6
transitions[0x1=>0x0]	1889338	1			T2	510		T4	5		T5	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98811	1			T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	611644	1			T2	227		T4	2		T5	2
all_pins[0]	transitions[0x0=>0x1]	611297	1			T2	227		T4	2		T5	2
all_pins[0]	transitions[0x1=>0x0]	52	1			T94	9		T21	2		T180	2
all_pins[1]	values[0x0]	710056	1			T1	1		T2	229		T3	2
all_pins[1]	values[0x1]	399	1			T266	13		T94	9		T21	2
all_pins[1]	transitions[0x0=>0x1]	384	1			T266	13		T94	9		T21	2
all_pins[1]	transitions[0x1=>0x0]	104	1			T264	1		T272	1		T273	1
all_pins[2]	values[0x0]	710336	1			T1	1		T2	229		T3	2
all_pins[2]	values[0x1]	119	1			T264	1		T272	1		T273	1
all_pins[2]	transitions[0x0=>0x1]	102	1			T264	1		T272	1		T273	1
all_pins[2]	transitions[0x1=>0x0]	51	1			T180	1		T181	2		T236	2
all_pins[3]	values[0x0]	710387	1			T1	1		T2	229		T3	2
all_pins[3]	values[0x1]	68	1			T180	1		T181	2		T236	2
all_pins[3]	transitions[0x0=>0x1]	54	1			T181	2		T236	1		T234	1
all_pins[3]	transitions[0x1=>0x0]	72	1			T13	1		T21	1		T268	2
all_pins[4]	values[0x0]	710369	1			T1	1		T2	229		T3	2
all_pins[4]	values[0x1]	86	1			T13	1		T21	1		T268	2
all_pins[4]	transitions[0x0=>0x1]	69	1			T13	1		T21	1		T268	2
all_pins[4]	transitions[0x1=>0x0]	58	1			T21	1		T181	2		T234	3
all_pins[5]	values[0x0]	710380	1			T1	1		T2	229		T3	2
all_pins[5]	values[0x1]	75	1			T21	1		T181	2		T236	1
all_pins[5]	transitions[0x0=>0x1]	58	1			T181	2		T236	1		T234	2
all_pins[5]	transitions[0x1=>0x0]	60	1			T21	4		T180	1		T236	6
all_pins[6]	values[0x0]	710378	1			T1	1		T2	229		T3	2
all_pins[6]	values[0x1]	77	1			T21	5		T180	1		T236	6
all_pins[6]	transitions[0x0=>0x1]	58	1			T21	5		T180	1		T236	6
all_pins[6]	transitions[0x1=>0x0]	26176	1			T2	42		T4	1		T5	1
all_pins[7]	values[0x0]	684260	1			T1	1		T2	187		T3	2
all_pins[7]	values[0x1]	26195	1			T2	42		T4	1		T5	1
all_pins[7]	transitions[0x0=>0x1]	26178	1			T2	42		T4	1		T5	1
all_pins[7]	transitions[0x1=>0x0]	60	1			T21	1		T181	1		T234	1
all_pins[8]	values[0x0]	710378	1			T1	1		T2	229		T3	2
all_pins[8]	values[0x1]	77	1			T21	1		T181	1		T234	3
all_pins[8]	transitions[0x0=>0x1]	56	1			T21	1		T181	1		T234	2
all_pins[8]	transitions[0x1=>0x0]	548388	1			T2	15		T4	1		T5	1
all_pins[9]	values[0x0]	162046	1			T1	1		T2	214		T3	2
all_pins[9]	values[0x1]	548409	1			T2	15		T4	1		T5	1
all_pins[9]	transitions[0x0=>0x1]	548395	1			T2	15		T4	1		T5	1
all_pins[9]	transitions[0x1=>0x0]	59	1			T180	1		T181	2		T274	2
all_pins[10]	values[0x0]	710382	1			T1	1		T2	229		T3	2
all_pins[10]	values[0x1]	73	1			T21	1		T180	1		T181	3
all_pins[10]	transitions[0x0=>0x1]	49	1			T181	3		T275	1		T274	2
all_pins[10]	transitions[0x1=>0x0]	703735	1			T2	227		T4	2		T5	2
all_pins[11]	values[0x0]	6696	1			T1	1		T2	2		T3	2
all_pins[11]	values[0x1]	703759	1			T2	227		T4	2		T5	2
all_pins[11]	transitions[0x0=>0x1]	703721	1			T2	227		T4	2		T5	2
all_pins[11]	transitions[0x1=>0x0]	98	1			T64	1		T65	1		T68	2
all_pins[12]	values[0x0]	710319	1			T1	1		T2	229		T3	2
all_pins[12]	values[0x1]	136	1			T64	1		T65	1		T68	2
all_pins[12]	transitions[0x0=>0x1]	124	1			T64	1		T65	1		T68	2
all_pins[12]	transitions[0x1=>0x0]	63	1			T180	1		T236	2		T234	2
all_pins[13]	values[0x0]	710380	1			T1	1		T2	229		T3	2
all_pins[13]	values[0x1]	75	1			T180	1		T236	2		T234	4
all_pins[13]	transitions[0x0=>0x1]	63	1			T180	1		T236	2		T234	1
all_pins[13]	transitions[0x1=>0x0]	54	1			T21	2		T236	2		T234	1
all_pins[14]	values[0x0]	710389	1			T1	1		T2	229		T3	2
all_pins[14]	values[0x1]	66	1			T21	2		T236	2		T234	4
all_pins[14]	transitions[0x0=>0x1]	39	1			T21	1		T236	2		T234	1
all_pins[14]	transitions[0x1=>0x0]	610308	1			T2	226		T4	1		T5	1