Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	333	1			T21	7		T180	7		T181	7
all_values[1]	333	1			T21	7		T180	7		T181	7
all_values[2]	333	1			T21	7		T180	7		T181	7
all_values[3]	333	1			T21	7		T180	7		T181	7
all_values[4]	333	1			T21	7		T180	7		T181	7
all_values[5]	333	1			T21	7		T180	7		T181	7
all_values[6]	333	1			T21	7		T180	7		T181	7
all_values[7]	333	1			T21	7		T180	7		T181	7
all_values[8]	333	1			T21	7		T180	7		T181	7
all_values[9]	333	1			T21	7		T180	7		T181	7
all_values[10]	333	1			T21	7		T180	7		T181	7
all_values[11]	333	1			T21	7		T180	7		T181	7
all_values[12]	333	1			T21	7		T180	7		T181	7
all_values[13]	333	1			T21	7		T180	7		T181	7
all_values[14]	333	1			T21	7		T180	7		T181	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2762

1

T21

55

T180

52

T181

66

auto[1]

2233

1

T21

50

T180

53

T181

39

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

961

1

T21

17

T180

22

T181

11

auto[1]

4034

1

T21

88

T180

83

T181

94

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2964

1

T21

61

T180

61

T181

57

auto[1]

2031

1

T21

44

T180

44

T181

48

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	33	1			T236	6		T234	2		T275	4
all_values[0]	auto[0]	auto[0]	auto[1]	81	1			T21	4		T180	4		T181	2
all_values[0]	auto[0]	auto[1]	auto[0]	27	1			T236	5		T276	2		T277	1
all_values[0]	auto[0]	auto[1]	auto[1]	53	1			T21	1		T180	1		T181	2
all_values[0]	auto[1]	auto[0]	auto[1]	82	1			T180	1		T181	1		T234	3
all_values[0]	auto[1]	auto[1]	auto[1]	57	1			T21	2		T180	1		T181	2
all_values[1]	auto[0]	auto[0]	auto[0]	45	1			T234	1		T274	1		T276	2
all_values[1]	auto[0]	auto[0]	auto[1]	69	1			T21	1		T180	1		T181	2
all_values[1]	auto[0]	auto[1]	auto[0]	28	1			T234	1		T274	1		T278	1
all_values[1]	auto[0]	auto[1]	auto[1]	66	1			T21	2		T180	1		T181	1
all_values[1]	auto[1]	auto[0]	auto[1]	63	1			T21	2		T180	3		T181	3
all_values[1]	auto[1]	auto[1]	auto[1]	62	1			T21	2		T180	2		T181	1
all_values[2]	auto[0]	auto[0]	auto[0]	45	1			T21	3		T234	4		T275	4
all_values[2]	auto[0]	auto[0]	auto[1]	57	1			T21	1		T180	1		T181	2
all_values[2]	auto[0]	auto[1]	auto[0]	17	1			T21	1		T279	1		T280	2
all_values[2]	auto[0]	auto[1]	auto[1]	69	1			T180	3		T236	4		T234	2
all_values[2]	auto[1]	auto[0]	auto[1]	88	1			T21	2		T180	1		T181	5
all_values[2]	auto[1]	auto[1]	auto[1]	57	1			T180	2		T236	2		T275	1
all_values[3]	auto[0]	auto[0]	auto[0]	45	1			T181	1		T236	1		T234	2
all_values[3]	auto[0]	auto[0]	auto[1]	79	1			T21	3		T180	2		T181	1
all_values[3]	auto[0]	auto[1]	auto[0]	14	1			T274	2		T279	2		T281	1
all_values[3]	auto[0]	auto[1]	auto[1]	57	1			T180	2		T181	2		T236	4
all_values[3]	auto[1]	auto[0]	auto[1]	72	1			T21	3		T236	3		T234	4
all_values[3]	auto[1]	auto[1]	auto[1]	66	1			T21	1		T180	3		T181	3
all_values[4]	auto[0]	auto[0]	auto[0]	41	1			T181	2		T234	2		T275	1
all_values[4]	auto[0]	auto[0]	auto[1]	72	1			T21	2		T180	4		T236	4
all_values[4]	auto[0]	auto[1]	auto[0]	28	1			T181	1		T277	1		T135	1
all_values[4]	auto[0]	auto[1]	auto[1]	61	1			T21	4		T181	2		T236	3
all_values[4]	auto[1]	auto[0]	auto[1]	76	1			T180	1		T181	1		T236	1
all_values[4]	auto[1]	auto[1]	auto[1]	55	1			T21	1		T180	2		T181	1
all_values[5]	auto[0]	auto[0]	auto[0]	55	1			T180	1		T236	1		T234	4
all_values[5]	auto[0]	auto[0]	auto[1]	59	1			T21	2		T180	1		T181	1
all_values[5]	auto[0]	auto[1]	auto[0]	23	1			T180	4		T276	4		T282	2
all_values[5]	auto[0]	auto[1]	auto[1]	75	1			T21	1		T181	3		T236	1
all_values[5]	auto[1]	auto[0]	auto[1]	71	1			T21	3		T180	1		T181	2
all_values[5]	auto[1]	auto[1]	auto[1]	50	1			T21	1		T181	1		T236	3
all_values[6]	auto[0]	auto[0]	auto[0]	35	1			T181	1		T276	1		T135	1
all_values[6]	auto[0]	auto[0]	auto[1]	72	1			T21	1		T180	2		T181	4
all_values[6]	auto[0]	auto[1]	auto[0]	22	1			T234	1		T283	3		T281	1
all_values[6]	auto[0]	auto[1]	auto[1]	57	1			T21	2		T236	3		T234	1
all_values[6]	auto[1]	auto[0]	auto[1]	78	1			T21	1		T180	3		T181	1
all_values[6]	auto[1]	auto[1]	auto[1]	69	1			T21	3		T180	2		T181	1
all_values[7]	auto[0]	auto[0]	auto[0]	35	1			T180	2		T236	3		T274	1
all_values[7]	auto[0]	auto[0]	auto[1]	68	1			T21	5		T236	2		T234	3
all_values[7]	auto[0]	auto[1]	auto[0]	23	1			T180	1		T276	1		T284	1
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T180	2		T181	2		T236	2
all_values[7]	auto[1]	auto[0]	auto[1]	69	1			T21	1		T180	1		T181	3
all_values[7]	auto[1]	auto[1]	auto[1]	65	1			T21	1		T180	1		T181	2
all_values[8]	auto[0]	auto[0]	auto[0]	59	1			T234	1		T275	1		T274	1
all_values[8]	auto[0]	auto[0]	auto[1]	60	1			T21	2		T180	2		T181	4
all_values[8]	auto[0]	auto[1]	auto[0]	32	1			T21	1		T180	1		T234	1
all_values[8]	auto[0]	auto[1]	auto[1]	66	1			T180	2		T236	4		T234	2
all_values[8]	auto[1]	auto[0]	auto[1]	65	1			T21	4		T180	1		T181	3
all_values[8]	auto[1]	auto[1]	auto[1]	51	1			T180	1		T234	3		T275	1
all_values[9]	auto[0]	auto[0]	auto[0]	35	1			T180	3		T236	1		T234	1
all_values[9]	auto[0]	auto[0]	auto[1]	67	1			T181	2		T236	2		T234	5
all_values[9]	auto[0]	auto[1]	auto[0]	23	1			T21	1		T180	4		T275	1
all_values[9]	auto[0]	auto[1]	auto[1]	76	1			T21	2		T181	1		T236	2
all_values[9]	auto[1]	auto[0]	auto[1]	67	1			T181	2		T236	4		T234	2
all_values[9]	auto[1]	auto[1]	auto[1]	65	1			T21	4		T181	2		T236	2
all_values[10]	auto[0]	auto[0]	auto[0]	32	1			T236	1		T234	1		T275	1
all_values[10]	auto[0]	auto[0]	auto[1]	80	1			T180	3		T181	2		T236	4
all_values[10]	auto[0]	auto[1]	auto[0]	15	1			T21	1		T285	3		T286	1
all_values[10]	auto[0]	auto[1]	auto[1]	64	1			T21	4		T180	1		T234	5
all_values[10]	auto[1]	auto[0]	auto[1]	80	1			T181	3		T236	5		T234	2
all_values[10]	auto[1]	auto[1]	auto[1]	62	1			T21	2		T180	3		T181	2
all_values[11]	auto[0]	auto[0]	auto[0]	40	1			T181	2		T236	2		T234	1
all_values[11]	auto[0]	auto[0]	auto[1]	63	1			T180	1		T181	1		T236	3
all_values[11]	auto[0]	auto[1]	auto[0]	20	1			T21	1		T181	2		T275	1
all_values[11]	auto[0]	auto[1]	auto[1]	64	1			T21	2		T180	1		T236	1
all_values[11]	auto[1]	auto[0]	auto[1]	77	1			T180	2		T181	1		T236	3
all_values[11]	auto[1]	auto[1]	auto[1]	69	1			T21	4		T180	3		T181	1
all_values[12]	auto[0]	auto[0]	auto[0]	45	1			T21	2		T180	2		T181	2
all_values[12]	auto[0]	auto[0]	auto[1]	61	1			T180	1		T181	2		T236	4
all_values[12]	auto[0]	auto[1]	auto[0]	31	1			T21	1		T180	2		T236	2
all_values[12]	auto[0]	auto[1]	auto[1]	59	1			T21	1		T234	3		T275	2
all_values[12]	auto[1]	auto[0]	auto[1]	78	1			T21	2		T181	1		T236	2
all_values[12]	auto[1]	auto[1]	auto[1]	59	1			T21	1		T180	2		T181	2
all_values[13]	auto[0]	auto[0]	auto[0]	42	1			T21	3		T236	3		T275	1
all_values[13]	auto[0]	auto[0]	auto[1]	66	1			T21	2		T180	1		T181	3
all_values[13]	auto[0]	auto[1]	auto[0]	21	1			T21	1		T180	1		T234	1
all_values[13]	auto[0]	auto[1]	auto[1]	66	1			T180	1		T181	2		T236	1
all_values[13]	auto[1]	auto[0]	auto[1]	67	1			T21	1		T180	2		T181	2
all_values[13]	auto[1]	auto[1]	auto[1]	71	1			T180	2		T236	2		T234	1
all_values[14]	auto[0]	auto[0]	auto[0]	35	1			T21	1		T236	3		T275	1
all_values[14]	auto[0]	auto[0]	auto[1]	74	1			T21	1		T180	1		T181	2
all_values[14]	auto[0]	auto[1]	auto[0]	15	1			T21	1		T180	1		T236	2
all_values[14]	auto[0]	auto[1]	auto[1]	69	1			T21	1		T180	1		T181	3
all_values[14]	auto[1]	auto[0]	auto[1]	79	1			T21	3		T180	4		T181	2
all_values[14]	auto[1]	auto[1]	auto[1]	61	1			T236	1		T234	3		T274	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal