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67 always_ff @(posedge clk_i or negedge rst_ni) begin
68 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
69 1/1 err_q <= '0;
Tests: T1 T2 T3
70 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
71 1/1 err_q <= 1'b1;
Tests: T182 T186 T187
72 end
MISSING_ELSE
73 end
74
75 // integrity error output is permanent and should be used for alert generation
76 // register errors are transactional
77 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
78
79 // outgoing integrity generation
80 tlul_pkg::tl_d2h_t tl_o_pre;
81 tlul_rsp_intg_gen #(
82 .EnableRspIntgGen(1),
83 .EnableDataIntgGen(1)
84 ) u_rsp_intg_gen (
85 .tl_i(tl_o_pre),
86 .tl_o(tl_o)
87 );
88
89 1/1 assign tl_reg_h2d = tl_i;
Tests: T1 T2 T3
90 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T1 T2 T3
91
92 tlul_adapter_reg #(
93 .RegAw(AW),
94 .RegDw(DW),
95 .EnableDataIntgGen(0)
96 ) u_reg_if (
97 .clk_i (clk_i),
98 .rst_ni (rst_ni),
99
100 .tl_i (tl_reg_h2d),
101 .tl_o (tl_reg_d2h),
102
103 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
104 .intg_error_o(),
105
106 .we_o (reg_we),
107 .re_o (reg_re),
108 .addr_o (reg_addr),
109 .wdata_o (reg_wdata),
110 .be_o (reg_be),
111 .busy_i (reg_busy),
112 .rdata_i (reg_rdata),
113 .error_i (reg_error)
114 );
115
116 // cdc oversampling signals
117
118 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
119 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T183 T184 T185
120
121 // Define SW related signals
122 // Format: <reg>_<field>_{wd|we|qs}
123 // or <reg>_{wd|we|qs} if field == 1 or 0
124 logic intr_state_we;
125 logic intr_state_fmt_threshold_qs;
126 logic intr_state_rx_threshold_qs;
127 logic intr_state_acq_threshold_qs;
128 logic intr_state_rx_overflow_qs;
129 logic intr_state_rx_overflow_wd;
130 logic intr_state_controller_halt_qs;
131 logic intr_state_scl_interference_qs;
132 logic intr_state_scl_interference_wd;
133 logic intr_state_sda_interference_qs;
134 logic intr_state_sda_interference_wd;
135 logic intr_state_stretch_timeout_qs;
136 logic intr_state_stretch_timeout_wd;
137 logic intr_state_sda_unstable_qs;
138 logic intr_state_sda_unstable_wd;
139 logic intr_state_cmd_complete_qs;
140 logic intr_state_cmd_complete_wd;
141 logic intr_state_tx_stretch_qs;
142 logic intr_state_tx_threshold_qs;
143 logic intr_state_acq_stretch_qs;
144 logic intr_state_unexp_stop_qs;
145 logic intr_state_unexp_stop_wd;
146 logic intr_state_host_timeout_qs;
147 logic intr_state_host_timeout_wd;
148 logic intr_enable_we;
149 logic intr_enable_fmt_threshold_qs;
150 logic intr_enable_fmt_threshold_wd;
151 logic intr_enable_rx_threshold_qs;
152 logic intr_enable_rx_threshold_wd;
153 logic intr_enable_acq_threshold_qs;
154 logic intr_enable_acq_threshold_wd;
155 logic intr_enable_rx_overflow_qs;
156 logic intr_enable_rx_overflow_wd;
157 logic intr_enable_controller_halt_qs;
158 logic intr_enable_controller_halt_wd;
159 logic intr_enable_scl_interference_qs;
160 logic intr_enable_scl_interference_wd;
161 logic intr_enable_sda_interference_qs;
162 logic intr_enable_sda_interference_wd;
163 logic intr_enable_stretch_timeout_qs;
164 logic intr_enable_stretch_timeout_wd;
165 logic intr_enable_sda_unstable_qs;
166 logic intr_enable_sda_unstable_wd;
167 logic intr_enable_cmd_complete_qs;
168 logic intr_enable_cmd_complete_wd;
169 logic intr_enable_tx_stretch_qs;
170 logic intr_enable_tx_stretch_wd;
171 logic intr_enable_tx_threshold_qs;
172 logic intr_enable_tx_threshold_wd;
173 logic intr_enable_acq_stretch_qs;
174 logic intr_enable_acq_stretch_wd;
175 logic intr_enable_unexp_stop_qs;
176 logic intr_enable_unexp_stop_wd;
177 logic intr_enable_host_timeout_qs;
178 logic intr_enable_host_timeout_wd;
179 logic intr_test_we;
180 logic intr_test_fmt_threshold_wd;
181 logic intr_test_rx_threshold_wd;
182 logic intr_test_acq_threshold_wd;
183 logic intr_test_rx_overflow_wd;
184 logic intr_test_controller_halt_wd;
185 logic intr_test_scl_interference_wd;
186 logic intr_test_sda_interference_wd;
187 logic intr_test_stretch_timeout_wd;
188 logic intr_test_sda_unstable_wd;
189 logic intr_test_cmd_complete_wd;
190 logic intr_test_tx_stretch_wd;
191 logic intr_test_tx_threshold_wd;
192 logic intr_test_acq_stretch_wd;
193 logic intr_test_unexp_stop_wd;
194 logic intr_test_host_timeout_wd;
195 logic alert_test_we;
196 logic alert_test_wd;
197 logic ctrl_we;
198 logic ctrl_enablehost_qs;
199 logic ctrl_enablehost_wd;
200 logic ctrl_enabletarget_qs;
201 logic ctrl_enabletarget_wd;
202 logic ctrl_llpbk_qs;
203 logic ctrl_llpbk_wd;
204 logic ctrl_nack_addr_after_timeout_qs;
205 logic ctrl_nack_addr_after_timeout_wd;
206 logic ctrl_ack_ctrl_en_qs;
207 logic ctrl_ack_ctrl_en_wd;
208 logic ctrl_multi_controller_monitor_en_qs;
209 logic ctrl_multi_controller_monitor_en_wd;
210 logic ctrl_tx_stretch_ctrl_en_qs;
211 logic ctrl_tx_stretch_ctrl_en_wd;
212 logic status_re;
213 logic status_fmtfull_qs;
214 logic status_rxfull_qs;
215 logic status_fmtempty_qs;
216 logic status_hostidle_qs;
217 logic status_targetidle_qs;
218 logic status_rxempty_qs;
219 logic status_txfull_qs;
220 logic status_acqfull_qs;
221 logic status_txempty_qs;
222 logic status_acqempty_qs;
223 logic status_ack_ctrl_stretch_qs;
224 logic rdata_re;
225 logic [7:0] rdata_qs;
226 logic fdata_we;
227 logic [7:0] fdata_fbyte_wd;
228 logic fdata_start_wd;
229 logic fdata_stop_wd;
230 logic fdata_readb_wd;
231 logic fdata_rcont_wd;
232 logic fdata_nakok_wd;
233 logic fifo_ctrl_we;
234 logic fifo_ctrl_rxrst_wd;
235 logic fifo_ctrl_fmtrst_wd;
236 logic fifo_ctrl_acqrst_wd;
237 logic fifo_ctrl_txrst_wd;
238 logic host_fifo_config_we;
239 logic [11:0] host_fifo_config_rx_thresh_qs;
240 logic [11:0] host_fifo_config_rx_thresh_wd;
241 logic [11:0] host_fifo_config_fmt_thresh_qs;
242 logic [11:0] host_fifo_config_fmt_thresh_wd;
243 logic target_fifo_config_we;
244 logic [11:0] target_fifo_config_tx_thresh_qs;
245 logic [11:0] target_fifo_config_tx_thresh_wd;
246 logic [11:0] target_fifo_config_acq_thresh_qs;
247 logic [11:0] target_fifo_config_acq_thresh_wd;
248 logic host_fifo_status_re;
249 logic [11:0] host_fifo_status_fmtlvl_qs;
250 logic [11:0] host_fifo_status_rxlvl_qs;
251 logic target_fifo_status_re;
252 logic [11:0] target_fifo_status_txlvl_qs;
253 logic [11:0] target_fifo_status_acqlvl_qs;
254 logic ovrd_we;
255 logic ovrd_txovrden_qs;
256 logic ovrd_txovrden_wd;
257 logic ovrd_sclval_qs;
258 logic ovrd_sclval_wd;
259 logic ovrd_sdaval_qs;
260 logic ovrd_sdaval_wd;
261 logic val_re;
262 logic [15:0] val_scl_rx_qs;
263 logic [15:0] val_sda_rx_qs;
264 logic timing0_we;
265 logic [12:0] timing0_thigh_qs;
266 logic [12:0] timing0_thigh_wd;
267 logic [12:0] timing0_tlow_qs;
268 logic [12:0] timing0_tlow_wd;
269 logic timing1_we;
270 logic [9:0] timing1_t_r_qs;
271 logic [9:0] timing1_t_r_wd;
272 logic [8:0] timing1_t_f_qs;
273 logic [8:0] timing1_t_f_wd;
274 logic timing2_we;
275 logic [12:0] timing2_tsu_sta_qs;
276 logic [12:0] timing2_tsu_sta_wd;
277 logic [12:0] timing2_thd_sta_qs;
278 logic [12:0] timing2_thd_sta_wd;
279 logic timing3_we;
280 logic [8:0] timing3_tsu_dat_qs;
281 logic [8:0] timing3_tsu_dat_wd;
282 logic [12:0] timing3_thd_dat_qs;
283 logic [12:0] timing3_thd_dat_wd;
284 logic timing4_we;
285 logic [12:0] timing4_tsu_sto_qs;
286 logic [12:0] timing4_tsu_sto_wd;
287 logic [12:0] timing4_t_buf_qs;
288 logic [12:0] timing4_t_buf_wd;
289 logic timeout_ctrl_we;
290 logic [29:0] timeout_ctrl_val_qs;
291 logic [29:0] timeout_ctrl_val_wd;
292 logic timeout_ctrl_mode_qs;
293 logic timeout_ctrl_mode_wd;
294 logic timeout_ctrl_en_qs;
295 logic timeout_ctrl_en_wd;
296 logic target_id_we;
297 logic [6:0] target_id_address0_qs;
298 logic [6:0] target_id_address0_wd;
299 logic [6:0] target_id_mask0_qs;
300 logic [6:0] target_id_mask0_wd;
301 logic [6:0] target_id_address1_qs;
302 logic [6:0] target_id_address1_wd;
303 logic [6:0] target_id_mask1_qs;
304 logic [6:0] target_id_mask1_wd;
305 logic acqdata_re;
306 logic [7:0] acqdata_abyte_qs;
307 logic [2:0] acqdata_signal_qs;
308 logic txdata_we;
309 logic [7:0] txdata_wd;
310 logic host_timeout_ctrl_we;
311 logic [19:0] host_timeout_ctrl_qs;
312 logic [19:0] host_timeout_ctrl_wd;
313 logic target_timeout_ctrl_we;
314 logic [30:0] target_timeout_ctrl_val_qs;
315 logic [30:0] target_timeout_ctrl_val_wd;
316 logic target_timeout_ctrl_en_qs;
317 logic target_timeout_ctrl_en_wd;
318 logic target_nack_count_re;
319 logic [7:0] target_nack_count_qs;
320 logic [7:0] target_nack_count_wd;
321 logic target_ack_ctrl_re;
322 logic target_ack_ctrl_we;
323 logic [8:0] target_ack_ctrl_nbytes_qs;
324 logic [8:0] target_ack_ctrl_nbytes_wd;
325 logic target_ack_ctrl_nack_wd;
326 logic acq_fifo_next_data_re;
327 logic [7:0] acq_fifo_next_data_qs;
328 logic host_nack_handler_timeout_we;
329 logic [30:0] host_nack_handler_timeout_val_qs;
330 logic [30:0] host_nack_handler_timeout_val_wd;
331 logic host_nack_handler_timeout_en_qs;
332 logic host_nack_handler_timeout_en_wd;
333 logic controller_events_we;
334 logic controller_events_nack_qs;
335 logic controller_events_nack_wd;
336 logic controller_events_unhandled_nack_timeout_qs;
337 logic controller_events_unhandled_nack_timeout_wd;
338 logic controller_events_bus_timeout_qs;
339 logic controller_events_bus_timeout_wd;
340 logic controller_events_arbitration_lost_qs;
341 logic controller_events_arbitration_lost_wd;
342 logic target_events_we;
343 logic target_events_tx_pending_qs;
344 logic target_events_tx_pending_wd;
345 logic target_events_bus_timeout_qs;
346 logic target_events_bus_timeout_wd;
347 logic target_events_arbitration_lost_qs;
348 logic target_events_arbitration_lost_wd;
349
350 // Register instances
351 // R[intr_state]: V(False)
352 // F[fmt_threshold]: 0:0
353 prim_subreg #(
354 .DW (1),
355 .SwAccess(prim_subreg_pkg::SwAccessRO),
356 .RESVAL (1'h0),
357 .Mubi (1'b0)
358 ) u_intr_state_fmt_threshold (
359 .clk_i (clk_i),
360 .rst_ni (rst_ni),
361
362 // from register interface
363 .we (1'b0),
364 .wd ('0),
365
366 // from internal hardware
367 .de (hw2reg.intr_state.fmt_threshold.de),
368 .d (hw2reg.intr_state.fmt_threshold.d),
369
370 // to internal hardware
371 .qe (),
372 .q (reg2hw.intr_state.fmt_threshold.q),
373 .ds (),
374
375 // to register interface (read)
376 .qs (intr_state_fmt_threshold_qs)
377 );
378
379 // F[rx_threshold]: 1:1
380 prim_subreg #(
381 .DW (1),
382 .SwAccess(prim_subreg_pkg::SwAccessRO),
383 .RESVAL (1'h0),
384 .Mubi (1'b0)
385 ) u_intr_state_rx_threshold (
386 .clk_i (clk_i),
387 .rst_ni (rst_ni),
388
389 // from register interface
390 .we (1'b0),
391 .wd ('0),
392
393 // from internal hardware
394 .de (hw2reg.intr_state.rx_threshold.de),
395 .d (hw2reg.intr_state.rx_threshold.d),
396
397 // to internal hardware
398 .qe (),
399 .q (reg2hw.intr_state.rx_threshold.q),
400 .ds (),
401
402 // to register interface (read)
403 .qs (intr_state_rx_threshold_qs)
404 );
405
406 // F[acq_threshold]: 2:2
407 prim_subreg #(
408 .DW (1),
409 .SwAccess(prim_subreg_pkg::SwAccessRO),
410 .RESVAL (1'h0),
411 .Mubi (1'b0)
412 ) u_intr_state_acq_threshold (
413 .clk_i (clk_i),
414 .rst_ni (rst_ni),
415
416 // from register interface
417 .we (1'b0),
418 .wd ('0),
419
420 // from internal hardware
421 .de (hw2reg.intr_state.acq_threshold.de),
422 .d (hw2reg.intr_state.acq_threshold.d),
423
424 // to internal hardware
425 .qe (),
426 .q (reg2hw.intr_state.acq_threshold.q),
427 .ds (),
428
429 // to register interface (read)
430 .qs (intr_state_acq_threshold_qs)
431 );
432
433 // F[rx_overflow]: 3:3
434 prim_subreg #(
435 .DW (1),
436 .SwAccess(prim_subreg_pkg::SwAccessW1C),
437 .RESVAL (1'h0),
438 .Mubi (1'b0)
439 ) u_intr_state_rx_overflow (
440 .clk_i (clk_i),
441 .rst_ni (rst_ni),
442
443 // from register interface
444 .we (intr_state_we),
445 .wd (intr_state_rx_overflow_wd),
446
447 // from internal hardware
448 .de (hw2reg.intr_state.rx_overflow.de),
449 .d (hw2reg.intr_state.rx_overflow.d),
450
451 // to internal hardware
452 .qe (),
453 .q (reg2hw.intr_state.rx_overflow.q),
454 .ds (),
455
456 // to register interface (read)
457 .qs (intr_state_rx_overflow_qs)
458 );
459
460 // F[controller_halt]: 4:4
461 prim_subreg #(
462 .DW (1),
463 .SwAccess(prim_subreg_pkg::SwAccessRO),
464 .RESVAL (1'h0),
465 .Mubi (1'b0)
466 ) u_intr_state_controller_halt (
467 .clk_i (clk_i),
468 .rst_ni (rst_ni),
469
470 // from register interface
471 .we (1'b0),
472 .wd ('0),
473
474 // from internal hardware
475 .de (hw2reg.intr_state.controller_halt.de),
476 .d (hw2reg.intr_state.controller_halt.d),
477
478 // to internal hardware
479 .qe (),
480 .q (reg2hw.intr_state.controller_halt.q),
481 .ds (),
482
483 // to register interface (read)
484 .qs (intr_state_controller_halt_qs)
485 );
486
487 // F[scl_interference]: 5:5
488 prim_subreg #(
489 .DW (1),
490 .SwAccess(prim_subreg_pkg::SwAccessW1C),
491 .RESVAL (1'h0),
492 .Mubi (1'b0)
493 ) u_intr_state_scl_interference (
494 .clk_i (clk_i),
495 .rst_ni (rst_ni),
496
497 // from register interface
498 .we (intr_state_we),
499 .wd (intr_state_scl_interference_wd),
500
501 // from internal hardware
502 .de (hw2reg.intr_state.scl_interference.de),
503 .d (hw2reg.intr_state.scl_interference.d),
504
505 // to internal hardware
506 .qe (),
507 .q (reg2hw.intr_state.scl_interference.q),
508 .ds (),
509
510 // to register interface (read)
511 .qs (intr_state_scl_interference_qs)
512 );
513
514 // F[sda_interference]: 6:6
515 prim_subreg #(
516 .DW (1),
517 .SwAccess(prim_subreg_pkg::SwAccessW1C),
518 .RESVAL (1'h0),
519 .Mubi (1'b0)
520 ) u_intr_state_sda_interference (
521 .clk_i (clk_i),
522 .rst_ni (rst_ni),
523
524 // from register interface
525 .we (intr_state_we),
526 .wd (intr_state_sda_interference_wd),
527
528 // from internal hardware
529 .de (hw2reg.intr_state.sda_interference.de),
530 .d (hw2reg.intr_state.sda_interference.d),
531
532 // to internal hardware
533 .qe (),
534 .q (reg2hw.intr_state.sda_interference.q),
535 .ds (),
536
537 // to register interface (read)
538 .qs (intr_state_sda_interference_qs)
539 );
540
541 // F[stretch_timeout]: 7:7
542 prim_subreg #(
543 .DW (1),
544 .SwAccess(prim_subreg_pkg::SwAccessW1C),
545 .RESVAL (1'h0),
546 .Mubi (1'b0)
547 ) u_intr_state_stretch_timeout (
548 .clk_i (clk_i),
549 .rst_ni (rst_ni),
550
551 // from register interface
552 .we (intr_state_we),
553 .wd (intr_state_stretch_timeout_wd),
554
555 // from internal hardware
556 .de (hw2reg.intr_state.stretch_timeout.de),
557 .d (hw2reg.intr_state.stretch_timeout.d),
558
559 // to internal hardware
560 .qe (),
561 .q (reg2hw.intr_state.stretch_timeout.q),
562 .ds (),
563
564 // to register interface (read)
565 .qs (intr_state_stretch_timeout_qs)
566 );
567
568 // F[sda_unstable]: 8:8
569 prim_subreg #(
570 .DW (1),
571 .SwAccess(prim_subreg_pkg::SwAccessW1C),
572 .RESVAL (1'h0),
573 .Mubi (1'b0)
574 ) u_intr_state_sda_unstable (
575 .clk_i (clk_i),
576 .rst_ni (rst_ni),
577
578 // from register interface
579 .we (intr_state_we),
580 .wd (intr_state_sda_unstable_wd),
581
582 // from internal hardware
583 .de (hw2reg.intr_state.sda_unstable.de),
584 .d (hw2reg.intr_state.sda_unstable.d),
585
586 // to internal hardware
587 .qe (),
588 .q (reg2hw.intr_state.sda_unstable.q),
589 .ds (),
590
591 // to register interface (read)
592 .qs (intr_state_sda_unstable_qs)
593 );
594
595 // F[cmd_complete]: 9:9
596 prim_subreg #(
597 .DW (1),
598 .SwAccess(prim_subreg_pkg::SwAccessW1C),
599 .RESVAL (1'h0),
600 .Mubi (1'b0)
601 ) u_intr_state_cmd_complete (
602 .clk_i (clk_i),
603 .rst_ni (rst_ni),
604
605 // from register interface
606 .we (intr_state_we),
607 .wd (intr_state_cmd_complete_wd),
608
609 // from internal hardware
610 .de (hw2reg.intr_state.cmd_complete.de),
611 .d (hw2reg.intr_state.cmd_complete.d),
612
613 // to internal hardware
614 .qe (),
615 .q (reg2hw.intr_state.cmd_complete.q),
616 .ds (),
617
618 // to register interface (read)
619 .qs (intr_state_cmd_complete_qs)
620 );
621
622 // F[tx_stretch]: 10:10
623 prim_subreg #(
624 .DW (1),
625 .SwAccess(prim_subreg_pkg::SwAccessRO),
626 .RESVAL (1'h0),
627 .Mubi (1'b0)
628 ) u_intr_state_tx_stretch (
629 .clk_i (clk_i),
630 .rst_ni (rst_ni),
631
632 // from register interface
633 .we (1'b0),
634 .wd ('0),
635
636 // from internal hardware
637 .de (hw2reg.intr_state.tx_stretch.de),
638 .d (hw2reg.intr_state.tx_stretch.d),
639
640 // to internal hardware
641 .qe (),
642 .q (reg2hw.intr_state.tx_stretch.q),
643 .ds (),
644
645 // to register interface (read)
646 .qs (intr_state_tx_stretch_qs)
647 );
648
649 // F[tx_threshold]: 11:11
650 prim_subreg #(
651 .DW (1),
652 .SwAccess(prim_subreg_pkg::SwAccessRO),
653 .RESVAL (1'h0),
654 .Mubi (1'b0)
655 ) u_intr_state_tx_threshold (
656 .clk_i (clk_i),
657 .rst_ni (rst_ni),
658
659 // from register interface
660 .we (1'b0),
661 .wd ('0),
662
663 // from internal hardware
664 .de (hw2reg.intr_state.tx_threshold.de),
665 .d (hw2reg.intr_state.tx_threshold.d),
666
667 // to internal hardware
668 .qe (),
669 .q (reg2hw.intr_state.tx_threshold.q),
670 .ds (),
671
672 // to register interface (read)
673 .qs (intr_state_tx_threshold_qs)
674 );
675
676 // F[acq_stretch]: 12:12
677 prim_subreg #(
678 .DW (1),
679 .SwAccess(prim_subreg_pkg::SwAccessRO),
680 .RESVAL (1'h0),
681 .Mubi (1'b0)
682 ) u_intr_state_acq_stretch (
683 .clk_i (clk_i),
684 .rst_ni (rst_ni),
685
686 // from register interface
687 .we (1'b0),
688 .wd ('0),
689
690 // from internal hardware
691 .de (hw2reg.intr_state.acq_stretch.de),
692 .d (hw2reg.intr_state.acq_stretch.d),
693
694 // to internal hardware
695 .qe (),
696 .q (reg2hw.intr_state.acq_stretch.q),
697 .ds (),
698
699 // to register interface (read)
700 .qs (intr_state_acq_stretch_qs)
701 );
702
703 // F[unexp_stop]: 13:13
704 prim_subreg #(
705 .DW (1),
706 .SwAccess(prim_subreg_pkg::SwAccessW1C),
707 .RESVAL (1'h0),
708 .Mubi (1'b0)
709 ) u_intr_state_unexp_stop (
710 .clk_i (clk_i),
711 .rst_ni (rst_ni),
712
713 // from register interface
714 .we (intr_state_we),
715 .wd (intr_state_unexp_stop_wd),
716
717 // from internal hardware
718 .de (hw2reg.intr_state.unexp_stop.de),
719 .d (hw2reg.intr_state.unexp_stop.d),
720
721 // to internal hardware
722 .qe (),
723 .q (reg2hw.intr_state.unexp_stop.q),
724 .ds (),
725
726 // to register interface (read)
727 .qs (intr_state_unexp_stop_qs)
728 );
729
730 // F[host_timeout]: 14:14
731 prim_subreg #(
732 .DW (1),
733 .SwAccess(prim_subreg_pkg::SwAccessW1C),
734 .RESVAL (1'h0),
735 .Mubi (1'b0)
736 ) u_intr_state_host_timeout (
737 .clk_i (clk_i),
738 .rst_ni (rst_ni),
739
740 // from register interface
741 .we (intr_state_we),
742 .wd (intr_state_host_timeout_wd),
743
744 // from internal hardware
745 .de (hw2reg.intr_state.host_timeout.de),
746 .d (hw2reg.intr_state.host_timeout.d),
747
748 // to internal hardware
749 .qe (),
750 .q (reg2hw.intr_state.host_timeout.q),
751 .ds (),
752
753 // to register interface (read)
754 .qs (intr_state_host_timeout_qs)
755 );
756
757
758 // R[intr_enable]: V(False)
759 // F[fmt_threshold]: 0:0
760 prim_subreg #(
761 .DW (1),
762 .SwAccess(prim_subreg_pkg::SwAccessRW),
763 .RESVAL (1'h0),
764 .Mubi (1'b0)
765 ) u_intr_enable_fmt_threshold (
766 .clk_i (clk_i),
767 .rst_ni (rst_ni),
768
769 // from register interface
770 .we (intr_enable_we),
771 .wd (intr_enable_fmt_threshold_wd),
772
773 // from internal hardware
774 .de (1'b0),
775 .d ('0),
776
777 // to internal hardware
778 .qe (),
779 .q (reg2hw.intr_enable.fmt_threshold.q),
780 .ds (),
781
782 // to register interface (read)
783 .qs (intr_enable_fmt_threshold_qs)
784 );
785
786 // F[rx_threshold]: 1:1
787 prim_subreg #(
788 .DW (1),
789 .SwAccess(prim_subreg_pkg::SwAccessRW),
790 .RESVAL (1'h0),
791 .Mubi (1'b0)
792 ) u_intr_enable_rx_threshold (
793 .clk_i (clk_i),
794 .rst_ni (rst_ni),
795
796 // from register interface
797 .we (intr_enable_we),
798 .wd (intr_enable_rx_threshold_wd),
799
800 // from internal hardware
801 .de (1'b0),
802 .d ('0),
803
804 // to internal hardware
805 .qe (),
806 .q (reg2hw.intr_enable.rx_threshold.q),
807 .ds (),
808
809 // to register interface (read)
810 .qs (intr_enable_rx_threshold_qs)
811 );
812
813 // F[acq_threshold]: 2:2
814 prim_subreg #(
815 .DW (1),
816 .SwAccess(prim_subreg_pkg::SwAccessRW),
817 .RESVAL (1'h0),
818 .Mubi (1'b0)
819 ) u_intr_enable_acq_threshold (
820 .clk_i (clk_i),
821 .rst_ni (rst_ni),
822
823 // from register interface
824 .we (intr_enable_we),
825 .wd (intr_enable_acq_threshold_wd),
826
827 // from internal hardware
828 .de (1'b0),
829 .d ('0),
830
831 // to internal hardware
832 .qe (),
833 .q (reg2hw.intr_enable.acq_threshold.q),
834 .ds (),
835
836 // to register interface (read)
837 .qs (intr_enable_acq_threshold_qs)
838 );
839
840 // F[rx_overflow]: 3:3
841 prim_subreg #(
842 .DW (1),
843 .SwAccess(prim_subreg_pkg::SwAccessRW),
844 .RESVAL (1'h0),
845 .Mubi (1'b0)
846 ) u_intr_enable_rx_overflow (
847 .clk_i (clk_i),
848 .rst_ni (rst_ni),
849
850 // from register interface
851 .we (intr_enable_we),
852 .wd (intr_enable_rx_overflow_wd),
853
854 // from internal hardware
855 .de (1'b0),
856 .d ('0),
857
858 // to internal hardware
859 .qe (),
860 .q (reg2hw.intr_enable.rx_overflow.q),
861 .ds (),
862
863 // to register interface (read)
864 .qs (intr_enable_rx_overflow_qs)
865 );
866
867 // F[controller_halt]: 4:4
868 prim_subreg #(
869 .DW (1),
870 .SwAccess(prim_subreg_pkg::SwAccessRW),
871 .RESVAL (1'h0),
872 .Mubi (1'b0)
873 ) u_intr_enable_controller_halt (
874 .clk_i (clk_i),
875 .rst_ni (rst_ni),
876
877 // from register interface
878 .we (intr_enable_we),
879 .wd (intr_enable_controller_halt_wd),
880
881 // from internal hardware
882 .de (1'b0),
883 .d ('0),
884
885 // to internal hardware
886 .qe (),
887 .q (reg2hw.intr_enable.controller_halt.q),
888 .ds (),
889
890 // to register interface (read)
891 .qs (intr_enable_controller_halt_qs)
892 );
893
894 // F[scl_interference]: 5:5
895 prim_subreg #(
896 .DW (1),
897 .SwAccess(prim_subreg_pkg::SwAccessRW),
898 .RESVAL (1'h0),
899 .Mubi (1'b0)
900 ) u_intr_enable_scl_interference (
901 .clk_i (clk_i),
902 .rst_ni (rst_ni),
903
904 // from register interface
905 .we (intr_enable_we),
906 .wd (intr_enable_scl_interference_wd),
907
908 // from internal hardware
909 .de (1'b0),
910 .d ('0),
911
912 // to internal hardware
913 .qe (),
914 .q (reg2hw.intr_enable.scl_interference.q),
915 .ds (),
916
917 // to register interface (read)
918 .qs (intr_enable_scl_interference_qs)
919 );
920
921 // F[sda_interference]: 6:6
922 prim_subreg #(
923 .DW (1),
924 .SwAccess(prim_subreg_pkg::SwAccessRW),
925 .RESVAL (1'h0),
926 .Mubi (1'b0)
927 ) u_intr_enable_sda_interference (
928 .clk_i (clk_i),
929 .rst_ni (rst_ni),
930
931 // from register interface
932 .we (intr_enable_we),
933 .wd (intr_enable_sda_interference_wd),
934
935 // from internal hardware
936 .de (1'b0),
937 .d ('0),
938
939 // to internal hardware
940 .qe (),
941 .q (reg2hw.intr_enable.sda_interference.q),
942 .ds (),
943
944 // to register interface (read)
945 .qs (intr_enable_sda_interference_qs)
946 );
947
948 // F[stretch_timeout]: 7:7
949 prim_subreg #(
950 .DW (1),
951 .SwAccess(prim_subreg_pkg::SwAccessRW),
952 .RESVAL (1'h0),
953 .Mubi (1'b0)
954 ) u_intr_enable_stretch_timeout (
955 .clk_i (clk_i),
956 .rst_ni (rst_ni),
957
958 // from register interface
959 .we (intr_enable_we),
960 .wd (intr_enable_stretch_timeout_wd),
961
962 // from internal hardware
963 .de (1'b0),
964 .d ('0),
965
966 // to internal hardware
967 .qe (),
968 .q (reg2hw.intr_enable.stretch_timeout.q),
969 .ds (),
970
971 // to register interface (read)
972 .qs (intr_enable_stretch_timeout_qs)
973 );
974
975 // F[sda_unstable]: 8:8
976 prim_subreg #(
977 .DW (1),
978 .SwAccess(prim_subreg_pkg::SwAccessRW),
979 .RESVAL (1'h0),
980 .Mubi (1'b0)
981 ) u_intr_enable_sda_unstable (
982 .clk_i (clk_i),
983 .rst_ni (rst_ni),
984
985 // from register interface
986 .we (intr_enable_we),
987 .wd (intr_enable_sda_unstable_wd),
988
989 // from internal hardware
990 .de (1'b0),
991 .d ('0),
992
993 // to internal hardware
994 .qe (),
995 .q (reg2hw.intr_enable.sda_unstable.q),
996 .ds (),
997
998 // to register interface (read)
999 .qs (intr_enable_sda_unstable_qs)
1000 );
1001
1002 // F[cmd_complete]: 9:9
1003 prim_subreg #(
1004 .DW (1),
1005 .SwAccess(prim_subreg_pkg::SwAccessRW),
1006 .RESVAL (1'h0),
1007 .Mubi (1'b0)
1008 ) u_intr_enable_cmd_complete (
1009 .clk_i (clk_i),
1010 .rst_ni (rst_ni),
1011
1012 // from register interface
1013 .we (intr_enable_we),
1014 .wd (intr_enable_cmd_complete_wd),
1015
1016 // from internal hardware
1017 .de (1'b0),
1018 .d ('0),
1019
1020 // to internal hardware
1021 .qe (),
1022 .q (reg2hw.intr_enable.cmd_complete.q),
1023 .ds (),
1024
1025 // to register interface (read)
1026 .qs (intr_enable_cmd_complete_qs)
1027 );
1028
1029 // F[tx_stretch]: 10:10
1030 prim_subreg #(
1031 .DW (1),
1032 .SwAccess(prim_subreg_pkg::SwAccessRW),
1033 .RESVAL (1'h0),
1034 .Mubi (1'b0)
1035 ) u_intr_enable_tx_stretch (
1036 .clk_i (clk_i),
1037 .rst_ni (rst_ni),
1038
1039 // from register interface
1040 .we (intr_enable_we),
1041 .wd (intr_enable_tx_stretch_wd),
1042
1043 // from internal hardware
1044 .de (1'b0),
1045 .d ('0),
1046
1047 // to internal hardware
1048 .qe (),
1049 .q (reg2hw.intr_enable.tx_stretch.q),
1050 .ds (),
1051
1052 // to register interface (read)
1053 .qs (intr_enable_tx_stretch_qs)
1054 );
1055
1056 // F[tx_threshold]: 11:11
1057 prim_subreg #(
1058 .DW (1),
1059 .SwAccess(prim_subreg_pkg::SwAccessRW),
1060 .RESVAL (1'h0),
1061 .Mubi (1'b0)
1062 ) u_intr_enable_tx_threshold (
1063 .clk_i (clk_i),
1064 .rst_ni (rst_ni),
1065
1066 // from register interface
1067 .we (intr_enable_we),
1068 .wd (intr_enable_tx_threshold_wd),
1069
1070 // from internal hardware
1071 .de (1'b0),
1072 .d ('0),
1073
1074 // to internal hardware
1075 .qe (),
1076 .q (reg2hw.intr_enable.tx_threshold.q),
1077 .ds (),
1078
1079 // to register interface (read)
1080 .qs (intr_enable_tx_threshold_qs)
1081 );
1082
1083 // F[acq_stretch]: 12:12
1084 prim_subreg #(
1085 .DW (1),
1086 .SwAccess(prim_subreg_pkg::SwAccessRW),
1087 .RESVAL (1'h0),
1088 .Mubi (1'b0)
1089 ) u_intr_enable_acq_stretch (
1090 .clk_i (clk_i),
1091 .rst_ni (rst_ni),
1092
1093 // from register interface
1094 .we (intr_enable_we),
1095 .wd (intr_enable_acq_stretch_wd),
1096
1097 // from internal hardware
1098 .de (1'b0),
1099 .d ('0),
1100
1101 // to internal hardware
1102 .qe (),
1103 .q (reg2hw.intr_enable.acq_stretch.q),
1104 .ds (),
1105
1106 // to register interface (read)
1107 .qs (intr_enable_acq_stretch_qs)
1108 );
1109
1110 // F[unexp_stop]: 13:13
1111 prim_subreg #(
1112 .DW (1),
1113 .SwAccess(prim_subreg_pkg::SwAccessRW),
1114 .RESVAL (1'h0),
1115 .Mubi (1'b0)
1116 ) u_intr_enable_unexp_stop (
1117 .clk_i (clk_i),
1118 .rst_ni (rst_ni),
1119
1120 // from register interface
1121 .we (intr_enable_we),
1122 .wd (intr_enable_unexp_stop_wd),
1123
1124 // from internal hardware
1125 .de (1'b0),
1126 .d ('0),
1127
1128 // to internal hardware
1129 .qe (),
1130 .q (reg2hw.intr_enable.unexp_stop.q),
1131 .ds (),
1132
1133 // to register interface (read)
1134 .qs (intr_enable_unexp_stop_qs)
1135 );
1136
1137 // F[host_timeout]: 14:14
1138 prim_subreg #(
1139 .DW (1),
1140 .SwAccess(prim_subreg_pkg::SwAccessRW),
1141 .RESVAL (1'h0),
1142 .Mubi (1'b0)
1143 ) u_intr_enable_host_timeout (
1144 .clk_i (clk_i),
1145 .rst_ni (rst_ni),
1146
1147 // from register interface
1148 .we (intr_enable_we),
1149 .wd (intr_enable_host_timeout_wd),
1150
1151 // from internal hardware
1152 .de (1'b0),
1153 .d ('0),
1154
1155 // to internal hardware
1156 .qe (),
1157 .q (reg2hw.intr_enable.host_timeout.q),
1158 .ds (),
1159
1160 // to register interface (read)
1161 .qs (intr_enable_host_timeout_qs)
1162 );
1163
1164
1165 // R[intr_test]: V(True)
1166 logic intr_test_qe;
1167 logic [14:0] intr_test_flds_we;
1168 1/1 assign intr_test_qe = &intr_test_flds_we;
Tests: T21 T180 T181
1169 // F[fmt_threshold]: 0:0
1170 prim_subreg_ext #(
1171 .DW (1)
1172 ) u_intr_test_fmt_threshold (
1173 .re (1'b0),
1174 .we (intr_test_we),
1175 .wd (intr_test_fmt_threshold_wd),
1176 .d ('0),
1177 .qre (),
1178 .qe (intr_test_flds_we[0]),
1179 .q (reg2hw.intr_test.fmt_threshold.q),
1180 .ds (),
1181 .qs ()
1182 );
1183 1/1 assign reg2hw.intr_test.fmt_threshold.qe = intr_test_qe;
Tests: T21 T180 T181
1184
1185 // F[rx_threshold]: 1:1
1186 prim_subreg_ext #(
1187 .DW (1)
1188 ) u_intr_test_rx_threshold (
1189 .re (1'b0),
1190 .we (intr_test_we),
1191 .wd (intr_test_rx_threshold_wd),
1192 .d ('0),
1193 .qre (),
1194 .qe (intr_test_flds_we[1]),
1195 .q (reg2hw.intr_test.rx_threshold.q),
1196 .ds (),
1197 .qs ()
1198 );
1199 1/1 assign reg2hw.intr_test.rx_threshold.qe = intr_test_qe;
Tests: T21 T180 T181
1200
1201 // F[acq_threshold]: 2:2
1202 prim_subreg_ext #(
1203 .DW (1)
1204 ) u_intr_test_acq_threshold (
1205 .re (1'b0),
1206 .we (intr_test_we),
1207 .wd (intr_test_acq_threshold_wd),
1208 .d ('0),
1209 .qre (),
1210 .qe (intr_test_flds_we[2]),
1211 .q (reg2hw.intr_test.acq_threshold.q),
1212 .ds (),
1213 .qs ()
1214 );
1215 1/1 assign reg2hw.intr_test.acq_threshold.qe = intr_test_qe;
Tests: T21 T180 T181
1216
1217 // F[rx_overflow]: 3:3
1218 prim_subreg_ext #(
1219 .DW (1)
1220 ) u_intr_test_rx_overflow (
1221 .re (1'b0),
1222 .we (intr_test_we),
1223 .wd (intr_test_rx_overflow_wd),
1224 .d ('0),
1225 .qre (),
1226 .qe (intr_test_flds_we[3]),
1227 .q (reg2hw.intr_test.rx_overflow.q),
1228 .ds (),
1229 .qs ()
1230 );
1231 1/1 assign reg2hw.intr_test.rx_overflow.qe = intr_test_qe;
Tests: T21 T180 T181
1232
1233 // F[controller_halt]: 4:4
1234 prim_subreg_ext #(
1235 .DW (1)
1236 ) u_intr_test_controller_halt (
1237 .re (1'b0),
1238 .we (intr_test_we),
1239 .wd (intr_test_controller_halt_wd),
1240 .d ('0),
1241 .qre (),
1242 .qe (intr_test_flds_we[4]),
1243 .q (reg2hw.intr_test.controller_halt.q),
1244 .ds (),
1245 .qs ()
1246 );
1247 1/1 assign reg2hw.intr_test.controller_halt.qe = intr_test_qe;
Tests: T21 T180 T181
1248
1249 // F[scl_interference]: 5:5
1250 prim_subreg_ext #(
1251 .DW (1)
1252 ) u_intr_test_scl_interference (
1253 .re (1'b0),
1254 .we (intr_test_we),
1255 .wd (intr_test_scl_interference_wd),
1256 .d ('0),
1257 .qre (),
1258 .qe (intr_test_flds_we[5]),
1259 .q (reg2hw.intr_test.scl_interference.q),
1260 .ds (),
1261 .qs ()
1262 );
1263 1/1 assign reg2hw.intr_test.scl_interference.qe = intr_test_qe;
Tests: T21 T180 T181
1264
1265 // F[sda_interference]: 6:6
1266 prim_subreg_ext #(
1267 .DW (1)
1268 ) u_intr_test_sda_interference (
1269 .re (1'b0),
1270 .we (intr_test_we),
1271 .wd (intr_test_sda_interference_wd),
1272 .d ('0),
1273 .qre (),
1274 .qe (intr_test_flds_we[6]),
1275 .q (reg2hw.intr_test.sda_interference.q),
1276 .ds (),
1277 .qs ()
1278 );
1279 1/1 assign reg2hw.intr_test.sda_interference.qe = intr_test_qe;
Tests: T21 T180 T181
1280
1281 // F[stretch_timeout]: 7:7
1282 prim_subreg_ext #(
1283 .DW (1)
1284 ) u_intr_test_stretch_timeout (
1285 .re (1'b0),
1286 .we (intr_test_we),
1287 .wd (intr_test_stretch_timeout_wd),
1288 .d ('0),
1289 .qre (),
1290 .qe (intr_test_flds_we[7]),
1291 .q (reg2hw.intr_test.stretch_timeout.q),
1292 .ds (),
1293 .qs ()
1294 );
1295 1/1 assign reg2hw.intr_test.stretch_timeout.qe = intr_test_qe;
Tests: T21 T180 T181
1296
1297 // F[sda_unstable]: 8:8
1298 prim_subreg_ext #(
1299 .DW (1)
1300 ) u_intr_test_sda_unstable (
1301 .re (1'b0),
1302 .we (intr_test_we),
1303 .wd (intr_test_sda_unstable_wd),
1304 .d ('0),
1305 .qre (),
1306 .qe (intr_test_flds_we[8]),
1307 .q (reg2hw.intr_test.sda_unstable.q),
1308 .ds (),
1309 .qs ()
1310 );
1311 1/1 assign reg2hw.intr_test.sda_unstable.qe = intr_test_qe;
Tests: T21 T180 T181
1312
1313 // F[cmd_complete]: 9:9
1314 prim_subreg_ext #(
1315 .DW (1)
1316 ) u_intr_test_cmd_complete (
1317 .re (1'b0),
1318 .we (intr_test_we),
1319 .wd (intr_test_cmd_complete_wd),
1320 .d ('0),
1321 .qre (),
1322 .qe (intr_test_flds_we[9]),
1323 .q (reg2hw.intr_test.cmd_complete.q),
1324 .ds (),
1325 .qs ()
1326 );
1327 1/1 assign reg2hw.intr_test.cmd_complete.qe = intr_test_qe;
Tests: T21 T180 T181
1328
1329 // F[tx_stretch]: 10:10
1330 prim_subreg_ext #(
1331 .DW (1)
1332 ) u_intr_test_tx_stretch (
1333 .re (1'b0),
1334 .we (intr_test_we),
1335 .wd (intr_test_tx_stretch_wd),
1336 .d ('0),
1337 .qre (),
1338 .qe (intr_test_flds_we[10]),
1339 .q (reg2hw.intr_test.tx_stretch.q),
1340 .ds (),
1341 .qs ()
1342 );
1343 1/1 assign reg2hw.intr_test.tx_stretch.qe = intr_test_qe;
Tests: T21 T180 T181
1344
1345 // F[tx_threshold]: 11:11
1346 prim_subreg_ext #(
1347 .DW (1)
1348 ) u_intr_test_tx_threshold (
1349 .re (1'b0),
1350 .we (intr_test_we),
1351 .wd (intr_test_tx_threshold_wd),
1352 .d ('0),
1353 .qre (),
1354 .qe (intr_test_flds_we[11]),
1355 .q (reg2hw.intr_test.tx_threshold.q),
1356 .ds (),
1357 .qs ()
1358 );
1359 1/1 assign reg2hw.intr_test.tx_threshold.qe = intr_test_qe;
Tests: T21 T180 T181
1360
1361 // F[acq_stretch]: 12:12
1362 prim_subreg_ext #(
1363 .DW (1)
1364 ) u_intr_test_acq_stretch (
1365 .re (1'b0),
1366 .we (intr_test_we),
1367 .wd (intr_test_acq_stretch_wd),
1368 .d ('0),
1369 .qre (),
1370 .qe (intr_test_flds_we[12]),
1371 .q (reg2hw.intr_test.acq_stretch.q),
1372 .ds (),
1373 .qs ()
1374 );
1375 1/1 assign reg2hw.intr_test.acq_stretch.qe = intr_test_qe;
Tests: T21 T180 T181
1376
1377 // F[unexp_stop]: 13:13
1378 prim_subreg_ext #(
1379 .DW (1)
1380 ) u_intr_test_unexp_stop (
1381 .re (1'b0),
1382 .we (intr_test_we),
1383 .wd (intr_test_unexp_stop_wd),
1384 .d ('0),
1385 .qre (),
1386 .qe (intr_test_flds_we[13]),
1387 .q (reg2hw.intr_test.unexp_stop.q),
1388 .ds (),
1389 .qs ()
1390 );
1391 1/1 assign reg2hw.intr_test.unexp_stop.qe = intr_test_qe;
Tests: T21 T180 T181
1392
1393 // F[host_timeout]: 14:14
1394 prim_subreg_ext #(
1395 .DW (1)
1396 ) u_intr_test_host_timeout (
1397 .re (1'b0),
1398 .we (intr_test_we),
1399 .wd (intr_test_host_timeout_wd),
1400 .d ('0),
1401 .qre (),
1402 .qe (intr_test_flds_we[14]),
1403 .q (reg2hw.intr_test.host_timeout.q),
1404 .ds (),
1405 .qs ()
1406 );
1407 1/1 assign reg2hw.intr_test.host_timeout.qe = intr_test_qe;
Tests: T21 T180 T181
1408
1409
1410 // R[alert_test]: V(True)
1411 logic alert_test_qe;
1412 logic [0:0] alert_test_flds_we;
1413 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T99 T100 T101
1414 prim_subreg_ext #(
1415 .DW (1)
1416 ) u_alert_test (
1417 .re (1'b0),
1418 .we (alert_test_we),
1419 .wd (alert_test_wd),
1420 .d ('0),
1421 .qre (),
1422 .qe (alert_test_flds_we[0]),
1423 .q (reg2hw.alert_test.q),
1424 .ds (),
1425 .qs ()
1426 );
1427 1/1 assign reg2hw.alert_test.qe = alert_test_qe;
Tests: T99 T100 T101
1428
1429
1430 // R[ctrl]: V(False)
1431 // F[enablehost]: 0:0
1432 prim_subreg #(
1433 .DW (1),
1434 .SwAccess(prim_subreg_pkg::SwAccessRW),
1435 .RESVAL (1'h0),
1436 .Mubi (1'b0)
1437 ) u_ctrl_enablehost (
1438 .clk_i (clk_i),
1439 .rst_ni (rst_ni),
1440
1441 // from register interface
1442 .we (ctrl_we),
1443 .wd (ctrl_enablehost_wd),
1444
1445 // from internal hardware
1446 .de (1'b0),
1447 .d ('0),
1448
1449 // to internal hardware
1450 .qe (),
1451 .q (reg2hw.ctrl.enablehost.q),
1452 .ds (),
1453
1454 // to register interface (read)
1455 .qs (ctrl_enablehost_qs)
1456 );
1457
1458 // F[enabletarget]: 1:1
1459 prim_subreg #(
1460 .DW (1),
1461 .SwAccess(prim_subreg_pkg::SwAccessRW),
1462 .RESVAL (1'h0),
1463 .Mubi (1'b0)
1464 ) u_ctrl_enabletarget (
1465 .clk_i (clk_i),
1466 .rst_ni (rst_ni),
1467
1468 // from register interface
1469 .we (ctrl_we),
1470 .wd (ctrl_enabletarget_wd),
1471
1472 // from internal hardware
1473 .de (1'b0),
1474 .d ('0),
1475
1476 // to internal hardware
1477 .qe (),
1478 .q (reg2hw.ctrl.enabletarget.q),
1479 .ds (),
1480
1481 // to register interface (read)
1482 .qs (ctrl_enabletarget_qs)
1483 );
1484
1485 // F[llpbk]: 2:2
1486 prim_subreg #(
1487 .DW (1),
1488 .SwAccess(prim_subreg_pkg::SwAccessRW),
1489 .RESVAL (1'h0),
1490 .Mubi (1'b0)
1491 ) u_ctrl_llpbk (
1492 .clk_i (clk_i),
1493 .rst_ni (rst_ni),
1494
1495 // from register interface
1496 .we (ctrl_we),
1497 .wd (ctrl_llpbk_wd),
1498
1499 // from internal hardware
1500 .de (1'b0),
1501 .d ('0),
1502
1503 // to internal hardware
1504 .qe (),
1505 .q (reg2hw.ctrl.llpbk.q),
1506 .ds (),
1507
1508 // to register interface (read)
1509 .qs (ctrl_llpbk_qs)
1510 );
1511
1512 // F[nack_addr_after_timeout]: 3:3
1513 prim_subreg #(
1514 .DW (1),
1515 .SwAccess(prim_subreg_pkg::SwAccessRW),
1516 .RESVAL (1'h0),
1517 .Mubi (1'b0)
1518 ) u_ctrl_nack_addr_after_timeout (
1519 .clk_i (clk_i),
1520 .rst_ni (rst_ni),
1521
1522 // from register interface
1523 .we (ctrl_we),
1524 .wd (ctrl_nack_addr_after_timeout_wd),
1525
1526 // from internal hardware
1527 .de (1'b0),
1528 .d ('0),
1529
1530 // to internal hardware
1531 .qe (),
1532 .q (reg2hw.ctrl.nack_addr_after_timeout.q),
1533 .ds (),
1534
1535 // to register interface (read)
1536 .qs (ctrl_nack_addr_after_timeout_qs)
1537 );
1538
1539 // F[ack_ctrl_en]: 4:4
1540 prim_subreg #(
1541 .DW (1),
1542 .SwAccess(prim_subreg_pkg::SwAccessRW),
1543 .RESVAL (1'h0),
1544 .Mubi (1'b0)
1545 ) u_ctrl_ack_ctrl_en (
1546 .clk_i (clk_i),
1547 .rst_ni (rst_ni),
1548
1549 // from register interface
1550 .we (ctrl_we),
1551 .wd (ctrl_ack_ctrl_en_wd),
1552
1553 // from internal hardware
1554 .de (1'b0),
1555 .d ('0),
1556
1557 // to internal hardware
1558 .qe (),
1559 .q (reg2hw.ctrl.ack_ctrl_en.q),
1560 .ds (),
1561
1562 // to register interface (read)
1563 .qs (ctrl_ack_ctrl_en_qs)
1564 );
1565
1566 // F[multi_controller_monitor_en]: 5:5
1567 prim_subreg #(
1568 .DW (1),
1569 .SwAccess(prim_subreg_pkg::SwAccessRW),
1570 .RESVAL (1'h0),
1571 .Mubi (1'b0)
1572 ) u_ctrl_multi_controller_monitor_en (
1573 .clk_i (clk_i),
1574 .rst_ni (rst_ni),
1575
1576 // from register interface
1577 .we (ctrl_we),
1578 .wd (ctrl_multi_controller_monitor_en_wd),
1579
1580 // from internal hardware
1581 .de (1'b0),
1582 .d ('0),
1583
1584 // to internal hardware
1585 .qe (),
1586 .q (reg2hw.ctrl.multi_controller_monitor_en.q),
1587 .ds (),
1588
1589 // to register interface (read)
1590 .qs (ctrl_multi_controller_monitor_en_qs)
1591 );
1592
1593 // F[tx_stretch_ctrl_en]: 6:6
1594 prim_subreg #(
1595 .DW (1),
1596 .SwAccess(prim_subreg_pkg::SwAccessRW),
1597 .RESVAL (1'h0),
1598 .Mubi (1'b0)
1599 ) u_ctrl_tx_stretch_ctrl_en (
1600 .clk_i (clk_i),
1601 .rst_ni (rst_ni),
1602
1603 // from register interface
1604 .we (ctrl_we),
1605 .wd (ctrl_tx_stretch_ctrl_en_wd),
1606
1607 // from internal hardware
1608 .de (1'b0),
1609 .d ('0),
1610
1611 // to internal hardware
1612 .qe (),
1613 .q (reg2hw.ctrl.tx_stretch_ctrl_en.q),
1614 .ds (),
1615
1616 // to register interface (read)
1617 .qs (ctrl_tx_stretch_ctrl_en_qs)
1618 );
1619
1620
1621 // R[status]: V(True)
1622 // F[fmtfull]: 0:0
1623 prim_subreg_ext #(
1624 .DW (1)
1625 ) u_status_fmtfull (
1626 .re (status_re),
1627 .we (1'b0),
1628 .wd ('0),
1629 .d (hw2reg.status.fmtfull.d),
1630 .qre (),
1631 .qe (),
1632 .q (),
1633 .ds (),
1634 .qs (status_fmtfull_qs)
1635 );
1636
1637 // F[rxfull]: 1:1
1638 prim_subreg_ext #(
1639 .DW (1)
1640 ) u_status_rxfull (
1641 .re (status_re),
1642 .we (1'b0),
1643 .wd ('0),
1644 .d (hw2reg.status.rxfull.d),
1645 .qre (),
1646 .qe (),
1647 .q (),
1648 .ds (),
1649 .qs (status_rxfull_qs)
1650 );
1651
1652 // F[fmtempty]: 2:2
1653 prim_subreg_ext #(
1654 .DW (1)
1655 ) u_status_fmtempty (
1656 .re (status_re),
1657 .we (1'b0),
1658 .wd ('0),
1659 .d (hw2reg.status.fmtempty.d),
1660 .qre (),
1661 .qe (),
1662 .q (),
1663 .ds (),
1664 .qs (status_fmtempty_qs)
1665 );
1666
1667 // F[hostidle]: 3:3
1668 prim_subreg_ext #(
1669 .DW (1)
1670 ) u_status_hostidle (
1671 .re (status_re),
1672 .we (1'b0),
1673 .wd ('0),
1674 .d (hw2reg.status.hostidle.d),
1675 .qre (),
1676 .qe (),
1677 .q (),
1678 .ds (),
1679 .qs (status_hostidle_qs)
1680 );
1681
1682 // F[targetidle]: 4:4
1683 prim_subreg_ext #(
1684 .DW (1)
1685 ) u_status_targetidle (
1686 .re (status_re),
1687 .we (1'b0),
1688 .wd ('0),
1689 .d (hw2reg.status.targetidle.d),
1690 .qre (),
1691 .qe (),
1692 .q (),
1693 .ds (),
1694 .qs (status_targetidle_qs)
1695 );
1696
1697 // F[rxempty]: 5:5
1698 prim_subreg_ext #(
1699 .DW (1)
1700 ) u_status_rxempty (
1701 .re (status_re),
1702 .we (1'b0),
1703 .wd ('0),
1704 .d (hw2reg.status.rxempty.d),
1705 .qre (),
1706 .qe (),
1707 .q (),
1708 .ds (),
1709 .qs (status_rxempty_qs)
1710 );
1711
1712 // F[txfull]: 6:6
1713 prim_subreg_ext #(
1714 .DW (1)
1715 ) u_status_txfull (
1716 .re (status_re),
1717 .we (1'b0),
1718 .wd ('0),
1719 .d (hw2reg.status.txfull.d),
1720 .qre (),
1721 .qe (),
1722 .q (),
1723 .ds (),
1724 .qs (status_txfull_qs)
1725 );
1726
1727 // F[acqfull]: 7:7
1728 prim_subreg_ext #(
1729 .DW (1)
1730 ) u_status_acqfull (
1731 .re (status_re),
1732 .we (1'b0),
1733 .wd ('0),
1734 .d (hw2reg.status.acqfull.d),
1735 .qre (),
1736 .qe (),
1737 .q (),
1738 .ds (),
1739 .qs (status_acqfull_qs)
1740 );
1741
1742 // F[txempty]: 8:8
1743 prim_subreg_ext #(
1744 .DW (1)
1745 ) u_status_txempty (
1746 .re (status_re),
1747 .we (1'b0),
1748 .wd ('0),
1749 .d (hw2reg.status.txempty.d),
1750 .qre (),
1751 .qe (),
1752 .q (),
1753 .ds (),
1754 .qs (status_txempty_qs)
1755 );
1756
1757 // F[acqempty]: 9:9
1758 prim_subreg_ext #(
1759 .DW (1)
1760 ) u_status_acqempty (
1761 .re (status_re),
1762 .we (1'b0),
1763 .wd ('0),
1764 .d (hw2reg.status.acqempty.d),
1765 .qre (),
1766 .qe (),
1767 .q (),
1768 .ds (),
1769 .qs (status_acqempty_qs)
1770 );
1771
1772 // F[ack_ctrl_stretch]: 10:10
1773 prim_subreg_ext #(
1774 .DW (1)
1775 ) u_status_ack_ctrl_stretch (
1776 .re (status_re),
1777 .we (1'b0),
1778 .wd ('0),
1779 .d (hw2reg.status.ack_ctrl_stretch.d),
1780 .qre (),
1781 .qe (),
1782 .q (),
1783 .ds (),
1784 .qs (status_ack_ctrl_stretch_qs)
1785 );
1786
1787
1788 // R[rdata]: V(True)
1789 prim_subreg_ext #(
1790 .DW (8)
1791 ) u_rdata (
1792 .re (rdata_re),
1793 .we (1'b0),
1794 .wd ('0),
1795 .d (hw2reg.rdata.d),
1796 .qre (reg2hw.rdata.re),
1797 .qe (),
1798 .q (reg2hw.rdata.q),
1799 .ds (),
1800 .qs (rdata_qs)
1801 );
1802
1803
1804 // R[fdata]: V(False)
1805 logic fdata_qe;
1806 logic [5:0] fdata_flds_we;
1807 prim_flop #(
1808 .Width(1),
1809 .ResetValue(0)
1810 ) u_fdata0_qe (
1811 .clk_i(clk_i),
1812 .rst_ni(rst_ni),
1813 .d_i(&fdata_flds_we),
1814 .q_o(fdata_qe)
1815 );
1816 // F[fbyte]: 7:0
1817 prim_subreg #(
1818 .DW (8),
1819 .SwAccess(prim_subreg_pkg::SwAccessWO),
1820 .RESVAL (8'h0),
1821 .Mubi (1'b0)
1822 ) u_fdata_fbyte (
1823 .clk_i (clk_i),
1824 .rst_ni (rst_ni),
1825
1826 // from register interface
1827 .we (fdata_we),
1828 .wd (fdata_fbyte_wd),
1829
1830 // from internal hardware
1831 .de (1'b0),
1832 .d ('0),
1833
1834 // to internal hardware
1835 .qe (fdata_flds_we[0]),
1836 .q (reg2hw.fdata.fbyte.q),
1837 .ds (),
1838
1839 // to register interface (read)
1840 .qs ()
1841 );
1842 1/1 assign reg2hw.fdata.fbyte.qe = fdata_qe;
Tests: T1 T2 T3
1843
1844 // F[start]: 8:8
1845 prim_subreg #(
1846 .DW (1),
1847 .SwAccess(prim_subreg_pkg::SwAccessWO),
1848 .RESVAL (1'h0),
1849 .Mubi (1'b0)
1850 ) u_fdata_start (
1851 .clk_i (clk_i),
1852 .rst_ni (rst_ni),
1853
1854 // from register interface
1855 .we (fdata_we),
1856 .wd (fdata_start_wd),
1857
1858 // from internal hardware
1859 .de (1'b0),
1860 .d ('0),
1861
1862 // to internal hardware
1863 .qe (fdata_flds_we[1]),
1864 .q (reg2hw.fdata.start.q),
1865 .ds (),
1866
1867 // to register interface (read)
1868 .qs ()
1869 );
1870 1/1 assign reg2hw.fdata.start.qe = fdata_qe;
Tests: T1 T2 T3
1871
1872 // F[stop]: 9:9
1873 prim_subreg #(
1874 .DW (1),
1875 .SwAccess(prim_subreg_pkg::SwAccessWO),
1876 .RESVAL (1'h0),
1877 .Mubi (1'b0)
1878 ) u_fdata_stop (
1879 .clk_i (clk_i),
1880 .rst_ni (rst_ni),
1881
1882 // from register interface
1883 .we (fdata_we),
1884 .wd (fdata_stop_wd),
1885
1886 // from internal hardware
1887 .de (1'b0),
1888 .d ('0),
1889
1890 // to internal hardware
1891 .qe (fdata_flds_we[2]),
1892 .q (reg2hw.fdata.stop.q),
1893 .ds (),
1894
1895 // to register interface (read)
1896 .qs ()
1897 );
1898 1/1 assign reg2hw.fdata.stop.qe = fdata_qe;
Tests: T1 T2 T3
1899
1900 // F[readb]: 10:10
1901 prim_subreg #(
1902 .DW (1),
1903 .SwAccess(prim_subreg_pkg::SwAccessWO),
1904 .RESVAL (1'h0),
1905 .Mubi (1'b0)
1906 ) u_fdata_readb (
1907 .clk_i (clk_i),
1908 .rst_ni (rst_ni),
1909
1910 // from register interface
1911 .we (fdata_we),
1912 .wd (fdata_readb_wd),
1913
1914 // from internal hardware
1915 .de (1'b0),
1916 .d ('0),
1917
1918 // to internal hardware
1919 .qe (fdata_flds_we[3]),
1920 .q (reg2hw.fdata.readb.q),
1921 .ds (),
1922
1923 // to register interface (read)
1924 .qs ()
1925 );
1926 1/1 assign reg2hw.fdata.readb.qe = fdata_qe;
Tests: T1 T2 T3
1927
1928 // F[rcont]: 11:11
1929 prim_subreg #(
1930 .DW (1),
1931 .SwAccess(prim_subreg_pkg::SwAccessWO),
1932 .RESVAL (1'h0),
1933 .Mubi (1'b0)
1934 ) u_fdata_rcont (
1935 .clk_i (clk_i),
1936 .rst_ni (rst_ni),
1937
1938 // from register interface
1939 .we (fdata_we),
1940 .wd (fdata_rcont_wd),
1941
1942 // from internal hardware
1943 .de (1'b0),
1944 .d ('0),
1945
1946 // to internal hardware
1947 .qe (fdata_flds_we[4]),
1948 .q (reg2hw.fdata.rcont.q),
1949 .ds (),
1950
1951 // to register interface (read)
1952 .qs ()
1953 );
1954 1/1 assign reg2hw.fdata.rcont.qe = fdata_qe;
Tests: T1 T2 T3
1955
1956 // F[nakok]: 12:12
1957 prim_subreg #(
1958 .DW (1),
1959 .SwAccess(prim_subreg_pkg::SwAccessWO),
1960 .RESVAL (1'h0),
1961 .Mubi (1'b0)
1962 ) u_fdata_nakok (
1963 .clk_i (clk_i),
1964 .rst_ni (rst_ni),
1965
1966 // from register interface
1967 .we (fdata_we),
1968 .wd (fdata_nakok_wd),
1969
1970 // from internal hardware
1971 .de (1'b0),
1972 .d ('0),
1973
1974 // to internal hardware
1975 .qe (fdata_flds_we[5]),
1976 .q (reg2hw.fdata.nakok.q),
1977 .ds (),
1978
1979 // to register interface (read)
1980 .qs ()
1981 );
1982 1/1 assign reg2hw.fdata.nakok.qe = fdata_qe;
Tests: T1 T2 T3
1983
1984
1985 // R[fifo_ctrl]: V(False)
1986 logic fifo_ctrl_qe;
1987 logic [3:0] fifo_ctrl_flds_we;
1988 prim_flop #(
1989 .Width(1),
1990 .ResetValue(0)
1991 ) u_fifo_ctrl0_qe (
1992 .clk_i(clk_i),
1993 .rst_ni(rst_ni),
1994 .d_i(&fifo_ctrl_flds_we),
1995 .q_o(fifo_ctrl_qe)
1996 );
1997 // F[rxrst]: 0:0
1998 prim_subreg #(
1999 .DW (1),
2000 .SwAccess(prim_subreg_pkg::SwAccessWO),
2001 .RESVAL (1'h0),
2002 .Mubi (1'b0)
2003 ) u_fifo_ctrl_rxrst (
2004 .clk_i (clk_i),
2005 .rst_ni (rst_ni),
2006
2007 // from register interface
2008 .we (fifo_ctrl_we),
2009 .wd (fifo_ctrl_rxrst_wd),
2010
2011 // from internal hardware
2012 .de (1'b0),
2013 .d ('0),
2014
2015 // to internal hardware
2016 .qe (fifo_ctrl_flds_we[0]),
2017 .q (reg2hw.fifo_ctrl.rxrst.q),
2018 .ds (),
2019
2020 // to register interface (read)
2021 .qs ()
2022 );
2023 1/1 assign reg2hw.fifo_ctrl.rxrst.qe = fifo_ctrl_qe;
Tests: T1 T2 T3
2024
2025 // F[fmtrst]: 1:1
2026 prim_subreg #(
2027 .DW (1),
2028 .SwAccess(prim_subreg_pkg::SwAccessWO),
2029 .RESVAL (1'h0),
2030 .Mubi (1'b0)
2031 ) u_fifo_ctrl_fmtrst (
2032 .clk_i (clk_i),
2033 .rst_ni (rst_ni),
2034
2035 // from register interface
2036 .we (fifo_ctrl_we),
2037 .wd (fifo_ctrl_fmtrst_wd),
2038
2039 // from internal hardware
2040 .de (1'b0),
2041 .d ('0),
2042
2043 // to internal hardware
2044 .qe (fifo_ctrl_flds_we[1]),
2045 .q (reg2hw.fifo_ctrl.fmtrst.q),
2046 .ds (),
2047
2048 // to register interface (read)
2049 .qs ()
2050 );
2051 1/1 assign reg2hw.fifo_ctrl.fmtrst.qe = fifo_ctrl_qe;
Tests: T1 T2 T3
2052
2053 // F[acqrst]: 7:7
2054 prim_subreg #(
2055 .DW (1),
2056 .SwAccess(prim_subreg_pkg::SwAccessWO),
2057 .RESVAL (1'h0),
2058 .Mubi (1'b0)
2059 ) u_fifo_ctrl_acqrst (
2060 .clk_i (clk_i),
2061 .rst_ni (rst_ni),
2062
2063 // from register interface
2064 .we (fifo_ctrl_we),
2065 .wd (fifo_ctrl_acqrst_wd),
2066
2067 // from internal hardware
2068 .de (1'b0),
2069 .d ('0),
2070
2071 // to internal hardware
2072 .qe (fifo_ctrl_flds_we[2]),
2073 .q (reg2hw.fifo_ctrl.acqrst.q),
2074 .ds (),
2075
2076 // to register interface (read)
2077 .qs ()
2078 );
2079 1/1 assign reg2hw.fifo_ctrl.acqrst.qe = fifo_ctrl_qe;
Tests: T1 T2 T3
2080
2081 // F[txrst]: 8:8
2082 prim_subreg #(
2083 .DW (1),
2084 .SwAccess(prim_subreg_pkg::SwAccessWO),
2085 .RESVAL (1'h0),
2086 .Mubi (1'b0)
2087 ) u_fifo_ctrl_txrst (
2088 .clk_i (clk_i),
2089 .rst_ni (rst_ni),
2090
2091 // from register interface
2092 .we (fifo_ctrl_we),
2093 .wd (fifo_ctrl_txrst_wd),
2094
2095 // from internal hardware
2096 .de (1'b0),
2097 .d ('0),
2098
2099 // to internal hardware
2100 .qe (fifo_ctrl_flds_we[3]),
2101 .q (reg2hw.fifo_ctrl.txrst.q),
2102 .ds (),
2103
2104 // to register interface (read)
2105 .qs ()
2106 );
2107 1/1 assign reg2hw.fifo_ctrl.txrst.qe = fifo_ctrl_qe;
Tests: T1 T2 T3
2108
2109
2110 // R[host_fifo_config]: V(False)
2111 logic host_fifo_config_qe;
2112 logic [1:0] host_fifo_config_flds_we;
2113 prim_flop #(
2114 .Width(1),
2115 .ResetValue(0)
2116 ) u_host_fifo_config0_qe (
2117 .clk_i(clk_i),
2118 .rst_ni(rst_ni),
2119 .d_i(&host_fifo_config_flds_we),
2120 .q_o(host_fifo_config_qe)
2121 );
2122 // F[rx_thresh]: 11:0
2123 prim_subreg #(
2124 .DW (12),
2125 .SwAccess(prim_subreg_pkg::SwAccessRW),
2126 .RESVAL (12'h0),
2127 .Mubi (1'b0)
2128 ) u_host_fifo_config_rx_thresh (
2129 .clk_i (clk_i),
2130 .rst_ni (rst_ni),
2131
2132 // from register interface
2133 .we (host_fifo_config_we),
2134 .wd (host_fifo_config_rx_thresh_wd),
2135
2136 // from internal hardware
2137 .de (1'b0),
2138 .d ('0),
2139
2140 // to internal hardware
2141 .qe (host_fifo_config_flds_we[0]),
2142 .q (reg2hw.host_fifo_config.rx_thresh.q),
2143 .ds (),
2144
2145 // to register interface (read)
2146 .qs (host_fifo_config_rx_thresh_qs)
2147 );
2148 1/1 assign reg2hw.host_fifo_config.rx_thresh.qe = host_fifo_config_qe;
Tests: T1 T2 T3
2149
2150 // F[fmt_thresh]: 27:16
2151 prim_subreg #(
2152 .DW (12),
2153 .SwAccess(prim_subreg_pkg::SwAccessRW),
2154 .RESVAL (12'h0),
2155 .Mubi (1'b0)
2156 ) u_host_fifo_config_fmt_thresh (
2157 .clk_i (clk_i),
2158 .rst_ni (rst_ni),
2159
2160 // from register interface
2161 .we (host_fifo_config_we),
2162 .wd (host_fifo_config_fmt_thresh_wd),
2163
2164 // from internal hardware
2165 .de (1'b0),
2166 .d ('0),
2167
2168 // to internal hardware
2169 .qe (host_fifo_config_flds_we[1]),
2170 .q (reg2hw.host_fifo_config.fmt_thresh.q),
2171 .ds (),
2172
2173 // to register interface (read)
2174 .qs (host_fifo_config_fmt_thresh_qs)
2175 );
2176 1/1 assign reg2hw.host_fifo_config.fmt_thresh.qe = host_fifo_config_qe;
Tests: T1 T2 T3
2177
2178
2179 // R[target_fifo_config]: V(False)
2180 logic target_fifo_config_qe;
2181 logic [1:0] target_fifo_config_flds_we;
2182 prim_flop #(
2183 .Width(1),
2184 .ResetValue(0)
2185 ) u_target_fifo_config0_qe (
2186 .clk_i(clk_i),
2187 .rst_ni(rst_ni),
2188 .d_i(&target_fifo_config_flds_we),
2189 .q_o(target_fifo_config_qe)
2190 );
2191 // F[tx_thresh]: 11:0
2192 prim_subreg #(
2193 .DW (12),
2194 .SwAccess(prim_subreg_pkg::SwAccessRW),
2195 .RESVAL (12'h0),
2196 .Mubi (1'b0)
2197 ) u_target_fifo_config_tx_thresh (
2198 .clk_i (clk_i),
2199 .rst_ni (rst_ni),
2200
2201 // from register interface
2202 .we (target_fifo_config_we),
2203 .wd (target_fifo_config_tx_thresh_wd),
2204
2205 // from internal hardware
2206 .de (1'b0),
2207 .d ('0),
2208
2209 // to internal hardware
2210 .qe (target_fifo_config_flds_we[0]),
2211 .q (reg2hw.target_fifo_config.tx_thresh.q),
2212 .ds (),
2213
2214 // to register interface (read)
2215 .qs (target_fifo_config_tx_thresh_qs)
2216 );
2217 1/1 assign reg2hw.target_fifo_config.tx_thresh.qe = target_fifo_config_qe;
Tests: T1 T2 T3
2218
2219 // F[acq_thresh]: 27:16
2220 prim_subreg #(
2221 .DW (12),
2222 .SwAccess(prim_subreg_pkg::SwAccessRW),
2223 .RESVAL (12'h0),
2224 .Mubi (1'b0)
2225 ) u_target_fifo_config_acq_thresh (
2226 .clk_i (clk_i),
2227 .rst_ni (rst_ni),
2228
2229 // from register interface
2230 .we (target_fifo_config_we),
2231 .wd (target_fifo_config_acq_thresh_wd),
2232
2233 // from internal hardware
2234 .de (1'b0),
2235 .d ('0),
2236
2237 // to internal hardware
2238 .qe (target_fifo_config_flds_we[1]),
2239 .q (reg2hw.target_fifo_config.acq_thresh.q),
2240 .ds (),
2241
2242 // to register interface (read)
2243 .qs (target_fifo_config_acq_thresh_qs)
2244 );
2245 1/1 assign reg2hw.target_fifo_config.acq_thresh.qe = target_fifo_config_qe;
Tests: T1 T2 T3
2246
2247
2248 // R[host_fifo_status]: V(True)
2249 // F[fmtlvl]: 11:0
2250 prim_subreg_ext #(
2251 .DW (12)
2252 ) u_host_fifo_status_fmtlvl (
2253 .re (host_fifo_status_re),
2254 .we (1'b0),
2255 .wd ('0),
2256 .d (hw2reg.host_fifo_status.fmtlvl.d),
2257 .qre (),
2258 .qe (),
2259 .q (),
2260 .ds (),
2261 .qs (host_fifo_status_fmtlvl_qs)
2262 );
2263
2264 // F[rxlvl]: 27:16
2265 prim_subreg_ext #(
2266 .DW (12)
2267 ) u_host_fifo_status_rxlvl (
2268 .re (host_fifo_status_re),
2269 .we (1'b0),
2270 .wd ('0),
2271 .d (hw2reg.host_fifo_status.rxlvl.d),
2272 .qre (),
2273 .qe (),
2274 .q (),
2275 .ds (),
2276 .qs (host_fifo_status_rxlvl_qs)
2277 );
2278
2279
2280 // R[target_fifo_status]: V(True)
2281 // F[txlvl]: 11:0
2282 prim_subreg_ext #(
2283 .DW (12)
2284 ) u_target_fifo_status_txlvl (
2285 .re (target_fifo_status_re),
2286 .we (1'b0),
2287 .wd ('0),
2288 .d (hw2reg.target_fifo_status.txlvl.d),
2289 .qre (),
2290 .qe (),
2291 .q (),
2292 .ds (),
2293 .qs (target_fifo_status_txlvl_qs)
2294 );
2295
2296 // F[acqlvl]: 27:16
2297 prim_subreg_ext #(
2298 .DW (12)
2299 ) u_target_fifo_status_acqlvl (
2300 .re (target_fifo_status_re),
2301 .we (1'b0),
2302 .wd ('0),
2303 .d (hw2reg.target_fifo_status.acqlvl.d),
2304 .qre (),
2305 .qe (),
2306 .q (),
2307 .ds (),
2308 .qs (target_fifo_status_acqlvl_qs)
2309 );
2310
2311
2312 // R[ovrd]: V(False)
2313 // F[txovrden]: 0:0
2314 prim_subreg #(
2315 .DW (1),
2316 .SwAccess(prim_subreg_pkg::SwAccessRW),
2317 .RESVAL (1'h0),
2318 .Mubi (1'b0)
2319 ) u_ovrd_txovrden (
2320 .clk_i (clk_i),
2321 .rst_ni (rst_ni),
2322
2323 // from register interface
2324 .we (ovrd_we),
2325 .wd (ovrd_txovrden_wd),
2326
2327 // from internal hardware
2328 .de (1'b0),
2329 .d ('0),
2330
2331 // to internal hardware
2332 .qe (),
2333 .q (reg2hw.ovrd.txovrden.q),
2334 .ds (),
2335
2336 // to register interface (read)
2337 .qs (ovrd_txovrden_qs)
2338 );
2339
2340 // F[sclval]: 1:1
2341 prim_subreg #(
2342 .DW (1),
2343 .SwAccess(prim_subreg_pkg::SwAccessRW),
2344 .RESVAL (1'h0),
2345 .Mubi (1'b0)
2346 ) u_ovrd_sclval (
2347 .clk_i (clk_i),
2348 .rst_ni (rst_ni),
2349
2350 // from register interface
2351 .we (ovrd_we),
2352 .wd (ovrd_sclval_wd),
2353
2354 // from internal hardware
2355 .de (1'b0),
2356 .d ('0),
2357
2358 // to internal hardware
2359 .qe (),
2360 .q (reg2hw.ovrd.sclval.q),
2361 .ds (),
2362
2363 // to register interface (read)
2364 .qs (ovrd_sclval_qs)
2365 );
2366
2367 // F[sdaval]: 2:2
2368 prim_subreg #(
2369 .DW (1),
2370 .SwAccess(prim_subreg_pkg::SwAccessRW),
2371 .RESVAL (1'h0),
2372 .Mubi (1'b0)
2373 ) u_ovrd_sdaval (
2374 .clk_i (clk_i),
2375 .rst_ni (rst_ni),
2376
2377 // from register interface
2378 .we (ovrd_we),
2379 .wd (ovrd_sdaval_wd),
2380
2381 // from internal hardware
2382 .de (1'b0),
2383 .d ('0),
2384
2385 // to internal hardware
2386 .qe (),
2387 .q (reg2hw.ovrd.sdaval.q),
2388 .ds (),
2389
2390 // to register interface (read)
2391 .qs (ovrd_sdaval_qs)
2392 );
2393
2394
2395 // R[val]: V(True)
2396 // F[scl_rx]: 15:0
2397 prim_subreg_ext #(
2398 .DW (16)
2399 ) u_val_scl_rx (
2400 .re (val_re),
2401 .we (1'b0),
2402 .wd ('0),
2403 .d (hw2reg.val.scl_rx.d),
2404 .qre (),
2405 .qe (),
2406 .q (),
2407 .ds (),
2408 .qs (val_scl_rx_qs)
2409 );
2410
2411 // F[sda_rx]: 31:16
2412 prim_subreg_ext #(
2413 .DW (16)
2414 ) u_val_sda_rx (
2415 .re (val_re),
2416 .we (1'b0),
2417 .wd ('0),
2418 .d (hw2reg.val.sda_rx.d),
2419 .qre (),
2420 .qe (),
2421 .q (),
2422 .ds (),
2423 .qs (val_sda_rx_qs)
2424 );
2425
2426
2427 // R[timing0]: V(False)
2428 // F[thigh]: 12:0
2429 prim_subreg #(
2430 .DW (13),
2431 .SwAccess(prim_subreg_pkg::SwAccessRW),
2432 .RESVAL (13'h0),
2433 .Mubi (1'b0)
2434 ) u_timing0_thigh (
2435 .clk_i (clk_i),
2436 .rst_ni (rst_ni),
2437
2438 // from register interface
2439 .we (timing0_we),
2440 .wd (timing0_thigh_wd),
2441
2442 // from internal hardware
2443 .de (1'b0),
2444 .d ('0),
2445
2446 // to internal hardware
2447 .qe (),
2448 .q (reg2hw.timing0.thigh.q),
2449 .ds (),
2450
2451 // to register interface (read)
2452 .qs (timing0_thigh_qs)
2453 );
2454
2455 // F[tlow]: 28:16
2456 prim_subreg #(
2457 .DW (13),
2458 .SwAccess(prim_subreg_pkg::SwAccessRW),
2459 .RESVAL (13'h0),
2460 .Mubi (1'b0)
2461 ) u_timing0_tlow (
2462 .clk_i (clk_i),
2463 .rst_ni (rst_ni),
2464
2465 // from register interface
2466 .we (timing0_we),
2467 .wd (timing0_tlow_wd),
2468
2469 // from internal hardware
2470 .de (1'b0),
2471 .d ('0),
2472
2473 // to internal hardware
2474 .qe (),
2475 .q (reg2hw.timing0.tlow.q),
2476 .ds (),
2477
2478 // to register interface (read)
2479 .qs (timing0_tlow_qs)
2480 );
2481
2482
2483 // R[timing1]: V(False)
2484 // F[t_r]: 9:0
2485 prim_subreg #(
2486 .DW (10),
2487 .SwAccess(prim_subreg_pkg::SwAccessRW),
2488 .RESVAL (10'h0),
2489 .Mubi (1'b0)
2490 ) u_timing1_t_r (
2491 .clk_i (clk_i),
2492 .rst_ni (rst_ni),
2493
2494 // from register interface
2495 .we (timing1_we),
2496 .wd (timing1_t_r_wd),
2497
2498 // from internal hardware
2499 .de (1'b0),
2500 .d ('0),
2501
2502 // to internal hardware
2503 .qe (),
2504 .q (reg2hw.timing1.t_r.q),
2505 .ds (),
2506
2507 // to register interface (read)
2508 .qs (timing1_t_r_qs)
2509 );
2510
2511 // F[t_f]: 24:16
2512 prim_subreg #(
2513 .DW (9),
2514 .SwAccess(prim_subreg_pkg::SwAccessRW),
2515 .RESVAL (9'h0),
2516 .Mubi (1'b0)
2517 ) u_timing1_t_f (
2518 .clk_i (clk_i),
2519 .rst_ni (rst_ni),
2520
2521 // from register interface
2522 .we (timing1_we),
2523 .wd (timing1_t_f_wd),
2524
2525 // from internal hardware
2526 .de (1'b0),
2527 .d ('0),
2528
2529 // to internal hardware
2530 .qe (),
2531 .q (reg2hw.timing1.t_f.q),
2532 .ds (),
2533
2534 // to register interface (read)
2535 .qs (timing1_t_f_qs)
2536 );
2537
2538
2539 // R[timing2]: V(False)
2540 // F[tsu_sta]: 12:0
2541 prim_subreg #(
2542 .DW (13),
2543 .SwAccess(prim_subreg_pkg::SwAccessRW),
2544 .RESVAL (13'h0),
2545 .Mubi (1'b0)
2546 ) u_timing2_tsu_sta (
2547 .clk_i (clk_i),
2548 .rst_ni (rst_ni),
2549
2550 // from register interface
2551 .we (timing2_we),
2552 .wd (timing2_tsu_sta_wd),
2553
2554 // from internal hardware
2555 .de (1'b0),
2556 .d ('0),
2557
2558 // to internal hardware
2559 .qe (),
2560 .q (reg2hw.timing2.tsu_sta.q),
2561 .ds (),
2562
2563 // to register interface (read)
2564 .qs (timing2_tsu_sta_qs)
2565 );
2566
2567 // F[thd_sta]: 28:16
2568 prim_subreg #(
2569 .DW (13),
2570 .SwAccess(prim_subreg_pkg::SwAccessRW),
2571 .RESVAL (13'h0),
2572 .Mubi (1'b0)
2573 ) u_timing2_thd_sta (
2574 .clk_i (clk_i),
2575 .rst_ni (rst_ni),
2576
2577 // from register interface
2578 .we (timing2_we),
2579 .wd (timing2_thd_sta_wd),
2580
2581 // from internal hardware
2582 .de (1'b0),
2583 .d ('0),
2584
2585 // to internal hardware
2586 .qe (),
2587 .q (reg2hw.timing2.thd_sta.q),
2588 .ds (),
2589
2590 // to register interface (read)
2591 .qs (timing2_thd_sta_qs)
2592 );
2593
2594
2595 // R[timing3]: V(False)
2596 // F[tsu_dat]: 8:0
2597 prim_subreg #(
2598 .DW (9),
2599 .SwAccess(prim_subreg_pkg::SwAccessRW),
2600 .RESVAL (9'h0),
2601 .Mubi (1'b0)
2602 ) u_timing3_tsu_dat (
2603 .clk_i (clk_i),
2604 .rst_ni (rst_ni),
2605
2606 // from register interface
2607 .we (timing3_we),
2608 .wd (timing3_tsu_dat_wd),
2609
2610 // from internal hardware
2611 .de (1'b0),
2612 .d ('0),
2613
2614 // to internal hardware
2615 .qe (),
2616 .q (reg2hw.timing3.tsu_dat.q),
2617 .ds (),
2618
2619 // to register interface (read)
2620 .qs (timing3_tsu_dat_qs)
2621 );
2622
2623 // F[thd_dat]: 28:16
2624 prim_subreg #(
2625 .DW (13),
2626 .SwAccess(prim_subreg_pkg::SwAccessRW),
2627 .RESVAL (13'h0),
2628 .Mubi (1'b0)
2629 ) u_timing3_thd_dat (
2630 .clk_i (clk_i),
2631 .rst_ni (rst_ni),
2632
2633 // from register interface
2634 .we (timing3_we),
2635 .wd (timing3_thd_dat_wd),
2636
2637 // from internal hardware
2638 .de (1'b0),
2639 .d ('0),
2640
2641 // to internal hardware
2642 .qe (),
2643 .q (reg2hw.timing3.thd_dat.q),
2644 .ds (),
2645
2646 // to register interface (read)
2647 .qs (timing3_thd_dat_qs)
2648 );
2649
2650
2651 // R[timing4]: V(False)
2652 // F[tsu_sto]: 12:0
2653 prim_subreg #(
2654 .DW (13),
2655 .SwAccess(prim_subreg_pkg::SwAccessRW),
2656 .RESVAL (13'h0),
2657 .Mubi (1'b0)
2658 ) u_timing4_tsu_sto (
2659 .clk_i (clk_i),
2660 .rst_ni (rst_ni),
2661
2662 // from register interface
2663 .we (timing4_we),
2664 .wd (timing4_tsu_sto_wd),
2665
2666 // from internal hardware
2667 .de (1'b0),
2668 .d ('0),
2669
2670 // to internal hardware
2671 .qe (),
2672 .q (reg2hw.timing4.tsu_sto.q),
2673 .ds (),
2674
2675 // to register interface (read)
2676 .qs (timing4_tsu_sto_qs)
2677 );
2678
2679 // F[t_buf]: 28:16
2680 prim_subreg #(
2681 .DW (13),
2682 .SwAccess(prim_subreg_pkg::SwAccessRW),
2683 .RESVAL (13'h0),
2684 .Mubi (1'b0)
2685 ) u_timing4_t_buf (
2686 .clk_i (clk_i),
2687 .rst_ni (rst_ni),
2688
2689 // from register interface
2690 .we (timing4_we),
2691 .wd (timing4_t_buf_wd),
2692
2693 // from internal hardware
2694 .de (1'b0),
2695 .d ('0),
2696
2697 // to internal hardware
2698 .qe (),
2699 .q (reg2hw.timing4.t_buf.q),
2700 .ds (),
2701
2702 // to register interface (read)
2703 .qs (timing4_t_buf_qs)
2704 );
2705
2706
2707 // R[timeout_ctrl]: V(False)
2708 // F[val]: 29:0
2709 prim_subreg #(
2710 .DW (30),
2711 .SwAccess(prim_subreg_pkg::SwAccessRW),
2712 .RESVAL (30'h0),
2713 .Mubi (1'b0)
2714 ) u_timeout_ctrl_val (
2715 .clk_i (clk_i),
2716 .rst_ni (rst_ni),
2717
2718 // from register interface
2719 .we (timeout_ctrl_we),
2720 .wd (timeout_ctrl_val_wd),
2721
2722 // from internal hardware
2723 .de (1'b0),
2724 .d ('0),
2725
2726 // to internal hardware
2727 .qe (),
2728 .q (reg2hw.timeout_ctrl.val.q),
2729 .ds (),
2730
2731 // to register interface (read)
2732 .qs (timeout_ctrl_val_qs)
2733 );
2734
2735 // F[mode]: 30:30
2736 prim_subreg #(
2737 .DW (1),
2738 .SwAccess(prim_subreg_pkg::SwAccessRW),
2739 .RESVAL (1'h0),
2740 .Mubi (1'b0)
2741 ) u_timeout_ctrl_mode (
2742 .clk_i (clk_i),
2743 .rst_ni (rst_ni),
2744
2745 // from register interface
2746 .we (timeout_ctrl_we),
2747 .wd (timeout_ctrl_mode_wd),
2748
2749 // from internal hardware
2750 .de (1'b0),
2751 .d ('0),
2752
2753 // to internal hardware
2754 .qe (),
2755 .q (reg2hw.timeout_ctrl.mode.q),
2756 .ds (),
2757
2758 // to register interface (read)
2759 .qs (timeout_ctrl_mode_qs)
2760 );
2761
2762 // F[en]: 31:31
2763 prim_subreg #(
2764 .DW (1),
2765 .SwAccess(prim_subreg_pkg::SwAccessRW),
2766 .RESVAL (1'h0),
2767 .Mubi (1'b0)
2768 ) u_timeout_ctrl_en (
2769 .clk_i (clk_i),
2770 .rst_ni (rst_ni),
2771
2772 // from register interface
2773 .we (timeout_ctrl_we),
2774 .wd (timeout_ctrl_en_wd),
2775
2776 // from internal hardware
2777 .de (1'b0),
2778 .d ('0),
2779
2780 // to internal hardware
2781 .qe (),
2782 .q (reg2hw.timeout_ctrl.en.q),
2783 .ds (),
2784
2785 // to register interface (read)
2786 .qs (timeout_ctrl_en_qs)
2787 );
2788
2789
2790 // R[target_id]: V(False)
2791 // F[address0]: 6:0
2792 prim_subreg #(
2793 .DW (7),
2794 .SwAccess(prim_subreg_pkg::SwAccessRW),
2795 .RESVAL (7'h0),
2796 .Mubi (1'b0)
2797 ) u_target_id_address0 (
2798 .clk_i (clk_i),
2799 .rst_ni (rst_ni),
2800
2801 // from register interface
2802 .we (target_id_we),
2803 .wd (target_id_address0_wd),
2804
2805 // from internal hardware
2806 .de (1'b0),
2807 .d ('0),
2808
2809 // to internal hardware
2810 .qe (),
2811 .q (reg2hw.target_id.address0.q),
2812 .ds (),
2813
2814 // to register interface (read)
2815 .qs (target_id_address0_qs)
2816 );
2817
2818 // F[mask0]: 13:7
2819 prim_subreg #(
2820 .DW (7),
2821 .SwAccess(prim_subreg_pkg::SwAccessRW),
2822 .RESVAL (7'h0),
2823 .Mubi (1'b0)
2824 ) u_target_id_mask0 (
2825 .clk_i (clk_i),
2826 .rst_ni (rst_ni),
2827
2828 // from register interface
2829 .we (target_id_we),
2830 .wd (target_id_mask0_wd),
2831
2832 // from internal hardware
2833 .de (1'b0),
2834 .d ('0),
2835
2836 // to internal hardware
2837 .qe (),
2838 .q (reg2hw.target_id.mask0.q),
2839 .ds (),
2840
2841 // to register interface (read)
2842 .qs (target_id_mask0_qs)
2843 );
2844
2845 // F[address1]: 20:14
2846 prim_subreg #(
2847 .DW (7),
2848 .SwAccess(prim_subreg_pkg::SwAccessRW),
2849 .RESVAL (7'h0),
2850 .Mubi (1'b0)
2851 ) u_target_id_address1 (
2852 .clk_i (clk_i),
2853 .rst_ni (rst_ni),
2854
2855 // from register interface
2856 .we (target_id_we),
2857 .wd (target_id_address1_wd),
2858
2859 // from internal hardware
2860 .de (1'b0),
2861 .d ('0),
2862
2863 // to internal hardware
2864 .qe (),
2865 .q (reg2hw.target_id.address1.q),
2866 .ds (),
2867
2868 // to register interface (read)
2869 .qs (target_id_address1_qs)
2870 );
2871
2872 // F[mask1]: 27:21
2873 prim_subreg #(
2874 .DW (7),
2875 .SwAccess(prim_subreg_pkg::SwAccessRW),
2876 .RESVAL (7'h0),
2877 .Mubi (1'b0)
2878 ) u_target_id_mask1 (
2879 .clk_i (clk_i),
2880 .rst_ni (rst_ni),
2881
2882 // from register interface
2883 .we (target_id_we),
2884 .wd (target_id_mask1_wd),
2885
2886 // from internal hardware
2887 .de (1'b0),
2888 .d ('0),
2889
2890 // to internal hardware
2891 .qe (),
2892 .q (reg2hw.target_id.mask1.q),
2893 .ds (),
2894
2895 // to register interface (read)
2896 .qs (target_id_mask1_qs)
2897 );
2898
2899
2900 // R[acqdata]: V(True)
2901 // F[abyte]: 7:0
2902 prim_subreg_ext #(
2903 .DW (8)
2904 ) u_acqdata_abyte (
2905 .re (acqdata_re),
2906 .we (1'b0),
2907 .wd ('0),
2908 .d (hw2reg.acqdata.abyte.d),
2909 .qre (reg2hw.acqdata.abyte.re),
2910 .qe (),
2911 .q (reg2hw.acqdata.abyte.q),
2912 .ds (),
2913 .qs (acqdata_abyte_qs)
2914 );
2915
2916 // F[signal]: 10:8
2917 prim_subreg_ext #(
2918 .DW (3)
2919 ) u_acqdata_signal (
2920 .re (acqdata_re),
2921 .we (1'b0),
2922 .wd ('0),
2923 .d (hw2reg.acqdata.signal.d),
2924 .qre (reg2hw.acqdata.signal.re),
2925 .qe (),
2926 .q (reg2hw.acqdata.signal.q),
2927 .ds (),
2928 .qs (acqdata_signal_qs)
2929 );
2930
2931
2932 // R[txdata]: V(False)
2933 logic txdata_qe;
2934 logic [0:0] txdata_flds_we;
2935 prim_flop #(
2936 .Width(1),
2937 .ResetValue(0)
2938 ) u_txdata0_qe (
2939 .clk_i(clk_i),
2940 .rst_ni(rst_ni),
2941 .d_i(&txdata_flds_we),
2942 .q_o(txdata_qe)
2943 );
2944 prim_subreg #(
2945 .DW (8),
2946 .SwAccess(prim_subreg_pkg::SwAccessWO),
2947 .RESVAL (8'h0),
2948 .Mubi (1'b0)
2949 ) u_txdata (
2950 .clk_i (clk_i),
2951 .rst_ni (rst_ni),
2952
2953 // from register interface
2954 .we (txdata_we),
2955 .wd (txdata_wd),
2956
2957 // from internal hardware
2958 .de (1'b0),
2959 .d ('0),
2960
2961 // to internal hardware
2962 .qe (txdata_flds_we[0]),
2963 .q (reg2hw.txdata.q),
2964 .ds (),
2965
2966 // to register interface (read)
2967 .qs ()
2968 );
2969 1/1 assign reg2hw.txdata.qe = txdata_qe;
Tests: T1 T2 T3
2970
2971
2972 // R[host_timeout_ctrl]: V(False)
2973 prim_subreg #(
2974 .DW (20),
2975 .SwAccess(prim_subreg_pkg::SwAccessRW),
2976 .RESVAL (20'h0),
2977 .Mubi (1'b0)
2978 ) u_host_timeout_ctrl (
2979 .clk_i (clk_i),
2980 .rst_ni (rst_ni),
2981
2982 // from register interface
2983 .we (host_timeout_ctrl_we),
2984 .wd (host_timeout_ctrl_wd),
2985
2986 // from internal hardware
2987 .de (1'b0),
2988 .d ('0),
2989
2990 // to internal hardware
2991 .qe (),
2992 .q (reg2hw.host_timeout_ctrl.q),
2993 .ds (),
2994
2995 // to register interface (read)
2996 .qs (host_timeout_ctrl_qs)
2997 );
2998
2999
3000 // R[target_timeout_ctrl]: V(False)
3001 // F[val]: 30:0
3002 prim_subreg #(
3003 .DW (31),
3004 .SwAccess(prim_subreg_pkg::SwAccessRW),
3005 .RESVAL (31'h0),
3006 .Mubi (1'b0)
3007 ) u_target_timeout_ctrl_val (
3008 .clk_i (clk_i),
3009 .rst_ni (rst_ni),
3010
3011 // from register interface
3012 .we (target_timeout_ctrl_we),
3013 .wd (target_timeout_ctrl_val_wd),
3014
3015 // from internal hardware
3016 .de (1'b0),
3017 .d ('0),
3018
3019 // to internal hardware
3020 .qe (),
3021 .q (reg2hw.target_timeout_ctrl.val.q),
3022 .ds (),
3023
3024 // to register interface (read)
3025 .qs (target_timeout_ctrl_val_qs)
3026 );
3027
3028 // F[en]: 31:31
3029 prim_subreg #(
3030 .DW (1),
3031 .SwAccess(prim_subreg_pkg::SwAccessRW),
3032 .RESVAL (1'h0),
3033 .Mubi (1'b0)
3034 ) u_target_timeout_ctrl_en (
3035 .clk_i (clk_i),
3036 .rst_ni (rst_ni),
3037
3038 // from register interface
3039 .we (target_timeout_ctrl_we),
3040 .wd (target_timeout_ctrl_en_wd),
3041
3042 // from internal hardware
3043 .de (1'b0),
3044 .d ('0),
3045
3046 // to internal hardware
3047 .qe (),
3048 .q (reg2hw.target_timeout_ctrl.en.q),
3049 .ds (),
3050
3051 // to register interface (read)
3052 .qs (target_timeout_ctrl_en_qs)
3053 );
3054
3055
3056 // R[target_nack_count]: V(False)
3057 prim_subreg #(
3058 .DW (8),
3059 .SwAccess(prim_subreg_pkg::SwAccessRC),
3060 .RESVAL (8'h0),
3061 .Mubi (1'b0)
3062 ) u_target_nack_count (
3063 .clk_i (clk_i),
3064 .rst_ni (rst_ni),
3065
3066 // from register interface
3067 .we (target_nack_count_re),
3068 .wd (target_nack_count_wd),
3069
3070 // from internal hardware
3071 .de (hw2reg.target_nack_count.de),
3072 .d (hw2reg.target_nack_count.d),
3073
3074 // to internal hardware
3075 .qe (),
3076 .q (reg2hw.target_nack_count.q),
3077 .ds (),
3078
3079 // to register interface (read)
3080 .qs (target_nack_count_qs)
3081 );
3082
3083
3084 // R[target_ack_ctrl]: V(True)
3085 logic target_ack_ctrl_qe;
3086 logic [1:0] target_ack_ctrl_flds_we;
3087 1/1 assign target_ack_ctrl_qe = &target_ack_ctrl_flds_we;
Tests: T46 T47 T48
3088 // F[nbytes]: 8:0
3089 prim_subreg_ext #(
3090 .DW (9)
3091 ) u_target_ack_ctrl_nbytes (
3092 .re (target_ack_ctrl_re),
3093 .we (target_ack_ctrl_we),
3094 .wd (target_ack_ctrl_nbytes_wd),
3095 .d (hw2reg.target_ack_ctrl.nbytes.d),
3096 .qre (),
3097 .qe (target_ack_ctrl_flds_we[0]),
3098 .q (reg2hw.target_ack_ctrl.nbytes.q),
3099 .ds (),
3100 .qs (target_ack_ctrl_nbytes_qs)
3101 );
3102 1/1 assign reg2hw.target_ack_ctrl.nbytes.qe = target_ack_ctrl_qe;
Tests: T46 T47 T48
3103
3104 // F[nack]: 31:31
3105 prim_subreg_ext #(
3106 .DW (1)
3107 ) u_target_ack_ctrl_nack (
3108 .re (1'b0),
3109 .we (target_ack_ctrl_we),
3110 .wd (target_ack_ctrl_nack_wd),
3111 .d ('0),
3112 .qre (),
3113 .qe (target_ack_ctrl_flds_we[1]),
3114 .q (reg2hw.target_ack_ctrl.nack.q),
3115 .ds (),
3116 .qs ()
3117 );
3118 1/1 assign reg2hw.target_ack_ctrl.nack.qe = target_ack_ctrl_qe;
Tests: T46 T47 T48
3119
3120
3121 // R[acq_fifo_next_data]: V(True)
3122 prim_subreg_ext #(
3123 .DW (8)
3124 ) u_acq_fifo_next_data (
3125 .re (acq_fifo_next_data_re),
3126 .we (1'b0),
3127 .wd ('0),
3128 .d (hw2reg.acq_fifo_next_data.d),
3129 .qre (),
3130 .qe (),
3131 .q (),
3132 .ds (),
3133 .qs (acq_fifo_next_data_qs)
3134 );
3135
3136
3137 // R[host_nack_handler_timeout]: V(False)
3138 // F[val]: 30:0
3139 prim_subreg #(
3140 .DW (31),
3141 .SwAccess(prim_subreg_pkg::SwAccessRW),
3142 .RESVAL (31'h0),
3143 .Mubi (1'b0)
3144 ) u_host_nack_handler_timeout_val (
3145 .clk_i (clk_i),
3146 .rst_ni (rst_ni),
3147
3148 // from register interface
3149 .we (host_nack_handler_timeout_we),
3150 .wd (host_nack_handler_timeout_val_wd),
3151
3152 // from internal hardware
3153 .de (1'b0),
3154 .d ('0),
3155
3156 // to internal hardware
3157 .qe (),
3158 .q (reg2hw.host_nack_handler_timeout.val.q),
3159 .ds (),
3160
3161 // to register interface (read)
3162 .qs (host_nack_handler_timeout_val_qs)
3163 );
3164
3165 // F[en]: 31:31
3166 prim_subreg #(
3167 .DW (1),
3168 .SwAccess(prim_subreg_pkg::SwAccessRW),
3169 .RESVAL (1'h0),
3170 .Mubi (1'b0)
3171 ) u_host_nack_handler_timeout_en (
3172 .clk_i (clk_i),
3173 .rst_ni (rst_ni),
3174
3175 // from register interface
3176 .we (host_nack_handler_timeout_we),
3177 .wd (host_nack_handler_timeout_en_wd),
3178
3179 // from internal hardware
3180 .de (1'b0),
3181 .d ('0),
3182
3183 // to internal hardware
3184 .qe (),
3185 .q (reg2hw.host_nack_handler_timeout.en.q),
3186 .ds (),
3187
3188 // to register interface (read)
3189 .qs (host_nack_handler_timeout_en_qs)
3190 );
3191
3192
3193 // R[controller_events]: V(False)
3194 // F[nack]: 0:0
3195 prim_subreg #(
3196 .DW (1),
3197 .SwAccess(prim_subreg_pkg::SwAccessW1C),
3198 .RESVAL (1'h0),
3199 .Mubi (1'b0)
3200 ) u_controller_events_nack (
3201 .clk_i (clk_i),
3202 .rst_ni (rst_ni),
3203
3204 // from register interface
3205 .we (controller_events_we),
3206 .wd (controller_events_nack_wd),
3207
3208 // from internal hardware
3209 .de (hw2reg.controller_events.nack.de),
3210 .d (hw2reg.controller_events.nack.d),
3211
3212 // to internal hardware
3213 .qe (),
3214 .q (reg2hw.controller_events.nack.q),
3215 .ds (),
3216
3217 // to register interface (read)
3218 .qs (controller_events_nack_qs)
3219 );
3220
3221 // F[unhandled_nack_timeout]: 1:1
3222 prim_subreg #(
3223 .DW (1),
3224 .SwAccess(prim_subreg_pkg::SwAccessW1C),
3225 .RESVAL (1'h0),
3226 .Mubi (1'b0)
3227 ) u_controller_events_unhandled_nack_timeout (
3228 .clk_i (clk_i),
3229 .rst_ni (rst_ni),
3230
3231 // from register interface
3232 .we (controller_events_we),
3233 .wd (controller_events_unhandled_nack_timeout_wd),
3234
3235 // from internal hardware
3236 .de (hw2reg.controller_events.unhandled_nack_timeout.de),
3237 .d (hw2reg.controller_events.unhandled_nack_timeout.d),
3238
3239 // to internal hardware
3240 .qe (),
3241 .q (reg2hw.controller_events.unhandled_nack_timeout.q),
3242 .ds (),
3243
3244 // to register interface (read)
3245 .qs (controller_events_unhandled_nack_timeout_qs)
3246 );
3247
3248 // F[bus_timeout]: 2:2
3249 prim_subreg #(
3250 .DW (1),
3251 .SwAccess(prim_subreg_pkg::SwAccessW1C),
3252 .RESVAL (1'h0),
3253 .Mubi (1'b0)
3254 ) u_controller_events_bus_timeout (
3255 .clk_i (clk_i),
3256 .rst_ni (rst_ni),
3257
3258 // from register interface
3259 .we (controller_events_we),
3260 .wd (controller_events_bus_timeout_wd),
3261
3262 // from internal hardware
3263 .de (hw2reg.controller_events.bus_timeout.de),
3264 .d (hw2reg.controller_events.bus_timeout.d),
3265
3266 // to internal hardware
3267 .qe (),
3268 .q (reg2hw.controller_events.bus_timeout.q),
3269 .ds (),
3270
3271 // to register interface (read)
3272 .qs (controller_events_bus_timeout_qs)
3273 );
3274
3275 // F[arbitration_lost]: 3:3
3276 prim_subreg #(
3277 .DW (1),
3278 .SwAccess(prim_subreg_pkg::SwAccessW1C),
3279 .RESVAL (1'h0),
3280 .Mubi (1'b0)
3281 ) u_controller_events_arbitration_lost (
3282 .clk_i (clk_i),
3283 .rst_ni (rst_ni),
3284
3285 // from register interface
3286 .we (controller_events_we),
3287 .wd (controller_events_arbitration_lost_wd),
3288
3289 // from internal hardware
3290 .de (hw2reg.controller_events.arbitration_lost.de),
3291 .d (hw2reg.controller_events.arbitration_lost.d),
3292
3293 // to internal hardware
3294 .qe (),
3295 .q (reg2hw.controller_events.arbitration_lost.q),
3296 .ds (),
3297
3298 // to register interface (read)
3299 .qs (controller_events_arbitration_lost_qs)
3300 );
3301
3302
3303 // R[target_events]: V(False)
3304 // F[tx_pending]: 0:0
3305 prim_subreg #(
3306 .DW (1),
3307 .SwAccess(prim_subreg_pkg::SwAccessW1C),
3308 .RESVAL (1'h0),
3309 .Mubi (1'b0)
3310 ) u_target_events_tx_pending (
3311 .clk_i (clk_i),
3312 .rst_ni (rst_ni),
3313
3314 // from register interface
3315 .we (target_events_we),
3316 .wd (target_events_tx_pending_wd),
3317
3318 // from internal hardware
3319 .de (hw2reg.target_events.tx_pending.de),
3320 .d (hw2reg.target_events.tx_pending.d),
3321
3322 // to internal hardware
3323 .qe (),
3324 .q (reg2hw.target_events.tx_pending.q),
3325 .ds (),
3326
3327 // to register interface (read)
3328 .qs (target_events_tx_pending_qs)
3329 );
3330
3331 // F[bus_timeout]: 1:1
3332 prim_subreg #(
3333 .DW (1),
3334 .SwAccess(prim_subreg_pkg::SwAccessW1C),
3335 .RESVAL (1'h0),
3336 .Mubi (1'b0)
3337 ) u_target_events_bus_timeout (
3338 .clk_i (clk_i),
3339 .rst_ni (rst_ni),
3340
3341 // from register interface
3342 .we (target_events_we),
3343 .wd (target_events_bus_timeout_wd),
3344
3345 // from internal hardware
3346 .de (hw2reg.target_events.bus_timeout.de),
3347 .d (hw2reg.target_events.bus_timeout.d),
3348
3349 // to internal hardware
3350 .qe (),
3351 .q (reg2hw.target_events.bus_timeout.q),
3352 .ds (),
3353
3354 // to register interface (read)
3355 .qs (target_events_bus_timeout_qs)
3356 );
3357
3358 // F[arbitration_lost]: 2:2
3359 prim_subreg #(
3360 .DW (1),
3361 .SwAccess(prim_subreg_pkg::SwAccessW1C),
3362 .RESVAL (1'h0),
3363 .Mubi (1'b0)
3364 ) u_target_events_arbitration_lost (
3365 .clk_i (clk_i),
3366 .rst_ni (rst_ni),
3367
3368 // from register interface
3369 .we (target_events_we),
3370 .wd (target_events_arbitration_lost_wd),
3371
3372 // from internal hardware
3373 .de (hw2reg.target_events.arbitration_lost.de),
3374 .d (hw2reg.target_events.arbitration_lost.d),
3375
3376 // to internal hardware
3377 .qe (),
3378 .q (reg2hw.target_events.arbitration_lost.q),
3379 .ds (),
3380
3381 // to register interface (read)
3382 .qs (target_events_arbitration_lost_qs)
3383 );
3384
3385
3386
3387 logic [31:0] addr_hit;
3388 always_comb begin
3389 1/1 addr_hit = '0;
Tests: T1 T2 T3
3390 1/1 addr_hit[ 0] = (reg_addr == I2C_INTR_STATE_OFFSET);
Tests: T1 T2 T3
3391 1/1 addr_hit[ 1] = (reg_addr == I2C_INTR_ENABLE_OFFSET);
Tests: T1 T2 T3
3392 1/1 addr_hit[ 2] = (reg_addr == I2C_INTR_TEST_OFFSET);
Tests: T1 T2 T3
3393 1/1 addr_hit[ 3] = (reg_addr == I2C_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
3394 1/1 addr_hit[ 4] = (reg_addr == I2C_CTRL_OFFSET);
Tests: T1 T2 T3
3395 1/1 addr_hit[ 5] = (reg_addr == I2C_STATUS_OFFSET);
Tests: T1 T2 T3
3396 1/1 addr_hit[ 6] = (reg_addr == I2C_RDATA_OFFSET);
Tests: T1 T2 T3
3397 1/1 addr_hit[ 7] = (reg_addr == I2C_FDATA_OFFSET);
Tests: T1 T2 T3
3398 1/1 addr_hit[ 8] = (reg_addr == I2C_FIFO_CTRL_OFFSET);
Tests: T1 T2 T3
3399 1/1 addr_hit[ 9] = (reg_addr == I2C_HOST_FIFO_CONFIG_OFFSET);
Tests: T1 T2 T3
3400 1/1 addr_hit[10] = (reg_addr == I2C_TARGET_FIFO_CONFIG_OFFSET);
Tests: T1 T2 T3
3401 1/1 addr_hit[11] = (reg_addr == I2C_HOST_FIFO_STATUS_OFFSET);
Tests: T1 T2 T3
3402 1/1 addr_hit[12] = (reg_addr == I2C_TARGET_FIFO_STATUS_OFFSET);
Tests: T1 T2 T3
3403 1/1 addr_hit[13] = (reg_addr == I2C_OVRD_OFFSET);
Tests: T1 T2 T3
3404 1/1 addr_hit[14] = (reg_addr == I2C_VAL_OFFSET);
Tests: T1 T2 T3
3405 1/1 addr_hit[15] = (reg_addr == I2C_TIMING0_OFFSET);
Tests: T1 T2 T3
3406 1/1 addr_hit[16] = (reg_addr == I2C_TIMING1_OFFSET);
Tests: T1 T2 T3
3407 1/1 addr_hit[17] = (reg_addr == I2C_TIMING2_OFFSET);
Tests: T1 T2 T3
3408 1/1 addr_hit[18] = (reg_addr == I2C_TIMING3_OFFSET);
Tests: T1 T2 T3
3409 1/1 addr_hit[19] = (reg_addr == I2C_TIMING4_OFFSET);
Tests: T1 T2 T3
3410 1/1 addr_hit[20] = (reg_addr == I2C_TIMEOUT_CTRL_OFFSET);
Tests: T1 T2 T3
3411 1/1 addr_hit[21] = (reg_addr == I2C_TARGET_ID_OFFSET);
Tests: T1 T2 T3
3412 1/1 addr_hit[22] = (reg_addr == I2C_ACQDATA_OFFSET);
Tests: T1 T2 T3
3413 1/1 addr_hit[23] = (reg_addr == I2C_TXDATA_OFFSET);
Tests: T1 T2 T3
3414 1/1 addr_hit[24] = (reg_addr == I2C_HOST_TIMEOUT_CTRL_OFFSET);
Tests: T1 T2 T3
3415 1/1 addr_hit[25] = (reg_addr == I2C_TARGET_TIMEOUT_CTRL_OFFSET);
Tests: T1 T2 T3
3416 1/1 addr_hit[26] = (reg_addr == I2C_TARGET_NACK_COUNT_OFFSET);
Tests: T1 T2 T3
3417 1/1 addr_hit[27] = (reg_addr == I2C_TARGET_ACK_CTRL_OFFSET);
Tests: T1 T2 T3
3418 1/1 addr_hit[28] = (reg_addr == I2C_ACQ_FIFO_NEXT_DATA_OFFSET);
Tests: T1 T2 T3
3419 1/1 addr_hit[29] = (reg_addr == I2C_HOST_NACK_HANDLER_TIMEOUT_OFFSET);
Tests: T1 T2 T3
3420 1/1 addr_hit[30] = (reg_addr == I2C_CONTROLLER_EVENTS_OFFSET);
Tests: T1 T2 T3
3421 1/1 addr_hit[31] = (reg_addr == I2C_TARGET_EVENTS_OFFSET);
Tests: T1 T2 T3
3422 end
3423
3424 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
3425
3426 // Check sub-word write is permitted
3427 always_comb begin
3428 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
3429 ((addr_hit[ 0] & (|(I2C_PERMIT[ 0] & ~reg_be))) |
3430 (addr_hit[ 1] & (|(I2C_PERMIT[ 1] & ~reg_be))) |
3431 (addr_hit[ 2] & (|(I2C_PERMIT[ 2] & ~reg_be))) |
3432 (addr_hit[ 3] & (|(I2C_PERMIT[ 3] & ~reg_be))) |
3433 (addr_hit[ 4] & (|(I2C_PERMIT[ 4] & ~reg_be))) |
3434 (addr_hit[ 5] & (|(I2C_PERMIT[ 5] & ~reg_be))) |
3435 (addr_hit[ 6] & (|(I2C_PERMIT[ 6] & ~reg_be))) |
3436 (addr_hit[ 7] & (|(I2C_PERMIT[ 7] & ~reg_be))) |
3437 (addr_hit[ 8] & (|(I2C_PERMIT[ 8] & ~reg_be))) |
3438 (addr_hit[ 9] & (|(I2C_PERMIT[ 9] & ~reg_be))) |
3439 (addr_hit[10] & (|(I2C_PERMIT[10] & ~reg_be))) |
3440 (addr_hit[11] & (|(I2C_PERMIT[11] & ~reg_be))) |
3441 (addr_hit[12] & (|(I2C_PERMIT[12] & ~reg_be))) |
3442 (addr_hit[13] & (|(I2C_PERMIT[13] & ~reg_be))) |
3443 (addr_hit[14] & (|(I2C_PERMIT[14] & ~reg_be))) |
3444 (addr_hit[15] & (|(I2C_PERMIT[15] & ~reg_be))) |
3445 (addr_hit[16] & (|(I2C_PERMIT[16] & ~reg_be))) |
3446 (addr_hit[17] & (|(I2C_PERMIT[17] & ~reg_be))) |
3447 (addr_hit[18] & (|(I2C_PERMIT[18] & ~reg_be))) |
3448 (addr_hit[19] & (|(I2C_PERMIT[19] & ~reg_be))) |
3449 (addr_hit[20] & (|(I2C_PERMIT[20] & ~reg_be))) |
3450 (addr_hit[21] & (|(I2C_PERMIT[21] & ~reg_be))) |
3451 (addr_hit[22] & (|(I2C_PERMIT[22] & ~reg_be))) |
3452 (addr_hit[23] & (|(I2C_PERMIT[23] & ~reg_be))) |
3453 (addr_hit[24] & (|(I2C_PERMIT[24] & ~reg_be))) |
3454 (addr_hit[25] & (|(I2C_PERMIT[25] & ~reg_be))) |
3455 (addr_hit[26] & (|(I2C_PERMIT[26] & ~reg_be))) |
3456 (addr_hit[27] & (|(I2C_PERMIT[27] & ~reg_be))) |
3457 (addr_hit[28] & (|(I2C_PERMIT[28] & ~reg_be))) |
3458 (addr_hit[29] & (|(I2C_PERMIT[29] & ~reg_be))) |
3459 (addr_hit[30] & (|(I2C_PERMIT[30] & ~reg_be))) |
3460 (addr_hit[31] & (|(I2C_PERMIT[31] & ~reg_be)))));
3461 end
3462
3463 // Generate write-enables
3464 1/1 assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
3465
3466 1/1 assign intr_state_rx_overflow_wd = reg_wdata[3];
Tests: T1 T2 T3
3467
3468 1/1 assign intr_state_scl_interference_wd = reg_wdata[5];
Tests: T1 T2 T3
3469
3470 1/1 assign intr_state_sda_interference_wd = reg_wdata[6];
Tests: T1 T2 T3
3471
3472 1/1 assign intr_state_stretch_timeout_wd = reg_wdata[7];
Tests: T1 T2 T3
3473
3474 1/1 assign intr_state_sda_unstable_wd = reg_wdata[8];
Tests: T1 T2 T3
3475
3476 1/1 assign intr_state_cmd_complete_wd = reg_wdata[9];
Tests: T1 T2 T3
3477
3478 1/1 assign intr_state_unexp_stop_wd = reg_wdata[13];
Tests: T1 T2 T3
3479
3480 1/1 assign intr_state_host_timeout_wd = reg_wdata[14];
Tests: T1 T2 T3
3481 1/1 assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T3
3482
3483 1/1 assign intr_enable_fmt_threshold_wd = reg_wdata[0];
Tests: T1 T2 T3
3484
3485 1/1 assign intr_enable_rx_threshold_wd = reg_wdata[1];
Tests: T1 T2 T3
3486
3487 1/1 assign intr_enable_acq_threshold_wd = reg_wdata[2];
Tests: T1 T2 T3
3488
3489 1/1 assign intr_enable_rx_overflow_wd = reg_wdata[3];
Tests: T1 T2 T3
3490
3491 1/1 assign intr_enable_controller_halt_wd = reg_wdata[4];
Tests: T1 T2 T3
3492
3493 1/1 assign intr_enable_scl_interference_wd = reg_wdata[5];
Tests: T1 T2 T3
3494
3495 1/1 assign intr_enable_sda_interference_wd = reg_wdata[6];
Tests: T1 T2 T3
3496
3497 1/1 assign intr_enable_stretch_timeout_wd = reg_wdata[7];
Tests: T1 T2 T3
3498
3499 1/1 assign intr_enable_sda_unstable_wd = reg_wdata[8];
Tests: T1 T2 T3
3500
3501 1/1 assign intr_enable_cmd_complete_wd = reg_wdata[9];
Tests: T1 T2 T3
3502
3503 1/1 assign intr_enable_tx_stretch_wd = reg_wdata[10];
Tests: T1 T2 T3
3504
3505 1/1 assign intr_enable_tx_threshold_wd = reg_wdata[11];
Tests: T1 T2 T3
3506
3507 1/1 assign intr_enable_acq_stretch_wd = reg_wdata[12];
Tests: T1 T2 T3
3508
3509 1/1 assign intr_enable_unexp_stop_wd = reg_wdata[13];
Tests: T1 T2 T3
3510
3511 1/1 assign intr_enable_host_timeout_wd = reg_wdata[14];
Tests: T1 T2 T3
3512 1/1 assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
3513
3514 1/1 assign intr_test_fmt_threshold_wd = reg_wdata[0];
Tests: T1 T2 T3
3515
3516 1/1 assign intr_test_rx_threshold_wd = reg_wdata[1];
Tests: T1 T2 T3
3517
3518 1/1 assign intr_test_acq_threshold_wd = reg_wdata[2];
Tests: T1 T2 T3
3519
3520 1/1 assign intr_test_rx_overflow_wd = reg_wdata[3];
Tests: T1 T2 T3
3521
3522 1/1 assign intr_test_controller_halt_wd = reg_wdata[4];
Tests: T1 T2 T3
3523
3524 1/1 assign intr_test_scl_interference_wd = reg_wdata[5];
Tests: T1 T2 T3
3525
3526 1/1 assign intr_test_sda_interference_wd = reg_wdata[6];
Tests: T1 T2 T3
3527
3528 1/1 assign intr_test_stretch_timeout_wd = reg_wdata[7];
Tests: T1 T2 T3
3529
3530 1/1 assign intr_test_sda_unstable_wd = reg_wdata[8];
Tests: T1 T2 T3
3531
3532 1/1 assign intr_test_cmd_complete_wd = reg_wdata[9];
Tests: T1 T2 T3
3533
3534 1/1 assign intr_test_tx_stretch_wd = reg_wdata[10];
Tests: T1 T2 T3
3535
3536 1/1 assign intr_test_tx_threshold_wd = reg_wdata[11];
Tests: T1 T2 T3
3537
3538 1/1 assign intr_test_acq_stretch_wd = reg_wdata[12];
Tests: T1 T2 T3
3539
3540 1/1 assign intr_test_unexp_stop_wd = reg_wdata[13];
Tests: T1 T2 T3
3541
3542 1/1 assign intr_test_host_timeout_wd = reg_wdata[14];
Tests: T1 T2 T3
3543 1/1 assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
3544
3545 1/1 assign alert_test_wd = reg_wdata[0];
Tests: T1 T2 T3
3546 1/1 assign ctrl_we = addr_hit[4] & reg_we & !reg_error;
Tests: T1 T2 T3
3547
3548 1/1 assign ctrl_enablehost_wd = reg_wdata[0];
Tests: T1 T2 T3
3549
3550 1/1 assign ctrl_enabletarget_wd = reg_wdata[1];
Tests: T1 T2 T3
3551
3552 1/1 assign ctrl_llpbk_wd = reg_wdata[2];
Tests: T1 T2 T3
3553
3554 1/1 assign ctrl_nack_addr_after_timeout_wd = reg_wdata[3];
Tests: T1 T2 T3
3555
3556 1/1 assign ctrl_ack_ctrl_en_wd = reg_wdata[4];
Tests: T1 T2 T3
3557
3558 1/1 assign ctrl_multi_controller_monitor_en_wd = reg_wdata[5];
Tests: T1 T2 T3
3559
3560 1/1 assign ctrl_tx_stretch_ctrl_en_wd = reg_wdata[6];
Tests: T1 T2 T3
3561 1/1 assign status_re = addr_hit[5] & reg_re & !reg_error;
Tests: T1 T2 T3
3562 1/1 assign rdata_re = addr_hit[6] & reg_re & !reg_error;
Tests: T1 T2 T3
3563 1/1 assign fdata_we = addr_hit[7] & reg_we & !reg_error;
Tests: T1 T2 T3
3564
3565 1/1 assign fdata_fbyte_wd = reg_wdata[7:0];
Tests: T1 T2 T3
3566
3567 1/1 assign fdata_start_wd = reg_wdata[8];
Tests: T1 T2 T3
3568
3569 1/1 assign fdata_stop_wd = reg_wdata[9];
Tests: T1 T2 T3
3570
3571 1/1 assign fdata_readb_wd = reg_wdata[10];
Tests: T1 T2 T3
3572
3573 1/1 assign fdata_rcont_wd = reg_wdata[11];
Tests: T1 T2 T3
3574
3575 1/1 assign fdata_nakok_wd = reg_wdata[12];
Tests: T1 T2 T3
3576 1/1 assign fifo_ctrl_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T3
3577
3578 1/1 assign fifo_ctrl_rxrst_wd = reg_wdata[0];
Tests: T1 T2 T3
3579
3580 1/1 assign fifo_ctrl_fmtrst_wd = reg_wdata[1];
Tests: T1 T2 T3
3581
3582 1/1 assign fifo_ctrl_acqrst_wd = reg_wdata[7];
Tests: T1 T2 T3
3583
3584 1/1 assign fifo_ctrl_txrst_wd = reg_wdata[8];
Tests: T1 T2 T3
3585 1/1 assign host_fifo_config_we = addr_hit[9] & reg_we & !reg_error;
Tests: T1 T2 T3
3586
3587 1/1 assign host_fifo_config_rx_thresh_wd = reg_wdata[11:0];
Tests: T1 T2 T3
3588
3589 1/1 assign host_fifo_config_fmt_thresh_wd = reg_wdata[27:16];
Tests: T1 T2 T3
3590 1/1 assign target_fifo_config_we = addr_hit[10] & reg_we & !reg_error;
Tests: T1 T2 T3
3591
3592 1/1 assign target_fifo_config_tx_thresh_wd = reg_wdata[11:0];
Tests: T1 T2 T3
3593
3594 1/1 assign target_fifo_config_acq_thresh_wd = reg_wdata[27:16];
Tests: T1 T2 T3
3595 1/1 assign host_fifo_status_re = addr_hit[11] & reg_re & !reg_error;
Tests: T1 T2 T3
3596 1/1 assign target_fifo_status_re = addr_hit[12] & reg_re & !reg_error;
Tests: T1 T2 T3
3597 1/1 assign ovrd_we = addr_hit[13] & reg_we & !reg_error;
Tests: T1 T2 T3
3598
3599 1/1 assign ovrd_txovrden_wd = reg_wdata[0];
Tests: T1 T2 T3
3600
3601 1/1 assign ovrd_sclval_wd = reg_wdata[1];
Tests: T1 T2 T3
3602
3603 1/1 assign ovrd_sdaval_wd = reg_wdata[2];
Tests: T1 T2 T3
3604 1/1 assign val_re = addr_hit[14] & reg_re & !reg_error;
Tests: T1 T2 T3
3605 1/1 assign timing0_we = addr_hit[15] & reg_we & !reg_error;
Tests: T1 T2 T3
3606
3607 1/1 assign timing0_thigh_wd = reg_wdata[12:0];
Tests: T1 T2 T3
3608
3609 1/1 assign timing0_tlow_wd = reg_wdata[28:16];
Tests: T1 T2 T3
3610 1/1 assign timing1_we = addr_hit[16] & reg_we & !reg_error;
Tests: T1 T2 T3
3611
3612 1/1 assign timing1_t_r_wd = reg_wdata[9:0];
Tests: T1 T2 T3
3613
3614 1/1 assign timing1_t_f_wd = reg_wdata[24:16];
Tests: T1 T2 T3
3615 1/1 assign timing2_we = addr_hit[17] & reg_we & !reg_error;
Tests: T1 T2 T3
3616
3617 1/1 assign timing2_tsu_sta_wd = reg_wdata[12:0];
Tests: T1 T2 T3
3618
3619 1/1 assign timing2_thd_sta_wd = reg_wdata[28:16];
Tests: T1 T2 T3
3620 1/1 assign timing3_we = addr_hit[18] & reg_we & !reg_error;
Tests: T1 T2 T3
3621
3622 1/1 assign timing3_tsu_dat_wd = reg_wdata[8:0];
Tests: T1 T2 T3
3623
3624 1/1 assign timing3_thd_dat_wd = reg_wdata[28:16];
Tests: T1 T2 T3
3625 1/1 assign timing4_we = addr_hit[19] & reg_we & !reg_error;
Tests: T1 T2 T3
3626
3627 1/1 assign timing4_tsu_sto_wd = reg_wdata[12:0];
Tests: T1 T2 T3
3628
3629 1/1 assign timing4_t_buf_wd = reg_wdata[28:16];
Tests: T1 T2 T3
3630 1/1 assign timeout_ctrl_we = addr_hit[20] & reg_we & !reg_error;
Tests: T1 T2 T3
3631
3632 1/1 assign timeout_ctrl_val_wd = reg_wdata[29:0];
Tests: T1 T2 T3
3633
3634 1/1 assign timeout_ctrl_mode_wd = reg_wdata[30];
Tests: T1 T2 T3
3635
3636 1/1 assign timeout_ctrl_en_wd = reg_wdata[31];
Tests: T1 T2 T3
3637 1/1 assign target_id_we = addr_hit[21] & reg_we & !reg_error;
Tests: T1 T2 T3
3638
3639 1/1 assign target_id_address0_wd = reg_wdata[6:0];
Tests: T1 T2 T3
3640
3641 1/1 assign target_id_mask0_wd = reg_wdata[13:7];
Tests: T1 T2 T3
3642
3643 1/1 assign target_id_address1_wd = reg_wdata[20:14];
Tests: T1 T2 T3
3644
3645 1/1 assign target_id_mask1_wd = reg_wdata[27:21];
Tests: T1 T2 T3
3646 1/1 assign acqdata_re = addr_hit[22] & reg_re & !reg_error;
Tests: T1 T2 T3
3647 1/1 assign txdata_we = addr_hit[23] & reg_we & !reg_error;
Tests: T1 T2 T3
3648
3649 1/1 assign txdata_wd = reg_wdata[7:0];
Tests: T1 T2 T3
3650 1/1 assign host_timeout_ctrl_we = addr_hit[24] & reg_we & !reg_error;
Tests: T1 T2 T3
3651
3652 1/1 assign host_timeout_ctrl_wd = reg_wdata[19:0];
Tests: T1 T2 T3
3653 1/1 assign target_timeout_ctrl_we = addr_hit[25] & reg_we & !reg_error;
Tests: T1 T2 T3
3654
3655 1/1 assign target_timeout_ctrl_val_wd = reg_wdata[30:0];
Tests: T1 T2 T3
3656
3657 1/1 assign target_timeout_ctrl_en_wd = reg_wdata[31];
Tests: T1 T2 T3
3658 1/1 assign target_nack_count_re = addr_hit[26] & reg_re & !reg_error;
Tests: T1 T2 T3
3659
3660 assign target_nack_count_wd = '1;
3661 1/1 assign target_ack_ctrl_re = addr_hit[27] & reg_re & !reg_error;
Tests: T1 T2 T3
3662 1/1 assign target_ack_ctrl_we = addr_hit[27] & reg_we & !reg_error;
Tests: T1 T2 T3
3663
3664 1/1 assign target_ack_ctrl_nbytes_wd = reg_wdata[8:0];
Tests: T1 T2 T3
3665
3666 1/1 assign target_ack_ctrl_nack_wd = reg_wdata[31];
Tests: T1 T2 T3
3667 1/1 assign acq_fifo_next_data_re = addr_hit[28] & reg_re & !reg_error;
Tests: T1 T2 T3
3668 1/1 assign host_nack_handler_timeout_we = addr_hit[29] & reg_we & !reg_error;
Tests: T1 T2 T3
3669
3670 1/1 assign host_nack_handler_timeout_val_wd = reg_wdata[30:0];
Tests: T1 T2 T3
3671
3672 1/1 assign host_nack_handler_timeout_en_wd = reg_wdata[31];
Tests: T1 T2 T3
3673 1/1 assign controller_events_we = addr_hit[30] & reg_we & !reg_error;
Tests: T1 T2 T3
3674
3675 1/1 assign controller_events_nack_wd = reg_wdata[0];
Tests: T1 T2 T3
3676
3677 1/1 assign controller_events_unhandled_nack_timeout_wd = reg_wdata[1];
Tests: T1 T2 T3
3678
3679 1/1 assign controller_events_bus_timeout_wd = reg_wdata[2];
Tests: T1 T2 T3
3680
3681 1/1 assign controller_events_arbitration_lost_wd = reg_wdata[3];
Tests: T1 T2 T3
3682 1/1 assign target_events_we = addr_hit[31] & reg_we & !reg_error;
Tests: T1 T2 T3
3683
3684 1/1 assign target_events_tx_pending_wd = reg_wdata[0];
Tests: T1 T2 T3
3685
3686 1/1 assign target_events_bus_timeout_wd = reg_wdata[1];
Tests: T1 T2 T3
3687
3688 1/1 assign target_events_arbitration_lost_wd = reg_wdata[2];
Tests: T1 T2 T3
3689
3690 // Assign write-enables to checker logic vector.
3691 always_comb begin
3692 1/1 reg_we_check = '0;
Tests: T1 T2 T3
3693 1/1 reg_we_check[0] = intr_state_we;
Tests: T1 T2 T3
3694 1/1 reg_we_check[1] = intr_enable_we;
Tests: T1 T2 T3
3695 1/1 reg_we_check[2] = intr_test_we;
Tests: T1 T2 T3
3696 1/1 reg_we_check[3] = alert_test_we;
Tests: T1 T2 T3
3697 1/1 reg_we_check[4] = ctrl_we;
Tests: T1 T2 T3
3698 1/1 reg_we_check[5] = 1'b0;
Tests: T1 T2 T3
3699 1/1 reg_we_check[6] = 1'b0;
Tests: T1 T2 T3
3700 1/1 reg_we_check[7] = fdata_we;
Tests: T1 T2 T3
3701 1/1 reg_we_check[8] = fifo_ctrl_we;
Tests: T1 T2 T3
3702 1/1 reg_we_check[9] = host_fifo_config_we;
Tests: T1 T2 T3
3703 1/1 reg_we_check[10] = target_fifo_config_we;
Tests: T1 T2 T3
3704 1/1 reg_we_check[11] = 1'b0;
Tests: T1 T2 T3
3705 1/1 reg_we_check[12] = 1'b0;
Tests: T1 T2 T3
3706 1/1 reg_we_check[13] = ovrd_we;
Tests: T1 T2 T3
3707 1/1 reg_we_check[14] = 1'b0;
Tests: T1 T2 T3
3708 1/1 reg_we_check[15] = timing0_we;
Tests: T1 T2 T3
3709 1/1 reg_we_check[16] = timing1_we;
Tests: T1 T2 T3
3710 1/1 reg_we_check[17] = timing2_we;
Tests: T1 T2 T3
3711 1/1 reg_we_check[18] = timing3_we;
Tests: T1 T2 T3
3712 1/1 reg_we_check[19] = timing4_we;
Tests: T1 T2 T3
3713 1/1 reg_we_check[20] = timeout_ctrl_we;
Tests: T1 T2 T3
3714 1/1 reg_we_check[21] = target_id_we;
Tests: T1 T2 T3
3715 1/1 reg_we_check[22] = 1'b0;
Tests: T1 T2 T3
3716 1/1 reg_we_check[23] = txdata_we;
Tests: T1 T2 T3
3717 1/1 reg_we_check[24] = host_timeout_ctrl_we;
Tests: T1 T2 T3
3718 1/1 reg_we_check[25] = target_timeout_ctrl_we;
Tests: T1 T2 T3
3719 1/1 reg_we_check[26] = 1'b0;
Tests: T1 T2 T3
3720 1/1 reg_we_check[27] = target_ack_ctrl_we;
Tests: T1 T2 T3
3721 1/1 reg_we_check[28] = 1'b0;
Tests: T1 T2 T3
3722 1/1 reg_we_check[29] = host_nack_handler_timeout_we;
Tests: T1 T2 T3
3723 1/1 reg_we_check[30] = controller_events_we;
Tests: T1 T2 T3
3724 1/1 reg_we_check[31] = target_events_we;
Tests: T1 T2 T3
3725 end
3726
3727 // Read data return
3728 always_comb begin
3729 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
3730 1/1 unique case (1'b1)
Tests: T1 T2 T3
3731 addr_hit[0]: begin
3732 1/1 reg_rdata_next[0] = intr_state_fmt_threshold_qs;
Tests: T1 T2 T3
3733 1/1 reg_rdata_next[1] = intr_state_rx_threshold_qs;
Tests: T1 T2 T3
3734 1/1 reg_rdata_next[2] = intr_state_acq_threshold_qs;
Tests: T1 T2 T3
3735 1/1 reg_rdata_next[3] = intr_state_rx_overflow_qs;
Tests: T1 T2 T3
3736 1/1 reg_rdata_next[4] = intr_state_controller_halt_qs;
Tests: T1 T2 T3
3737 1/1 reg_rdata_next[5] = intr_state_scl_interference_qs;
Tests: T1 T2 T3
3738 1/1 reg_rdata_next[6] = intr_state_sda_interference_qs;
Tests: T1 T2 T3
3739 1/1 reg_rdata_next[7] = intr_state_stretch_timeout_qs;
Tests: T1 T2 T3
3740 1/1 reg_rdata_next[8] = intr_state_sda_unstable_qs;
Tests: T1 T2 T3
3741 1/1 reg_rdata_next[9] = intr_state_cmd_complete_qs;
Tests: T1 T2 T3
3742 1/1 reg_rdata_next[10] = intr_state_tx_stretch_qs;
Tests: T1 T2 T3
3743 1/1 reg_rdata_next[11] = intr_state_tx_threshold_qs;
Tests: T1 T2 T3
3744 1/1 reg_rdata_next[12] = intr_state_acq_stretch_qs;
Tests: T1 T2 T3
3745 1/1 reg_rdata_next[13] = intr_state_unexp_stop_qs;
Tests: T1 T2 T3
3746 1/1 reg_rdata_next[14] = intr_state_host_timeout_qs;
Tests: T1 T2 T3
3747 end
3748
3749 addr_hit[1]: begin
3750 1/1 reg_rdata_next[0] = intr_enable_fmt_threshold_qs;
Tests: T1 T2 T3
3751 1/1 reg_rdata_next[1] = intr_enable_rx_threshold_qs;
Tests: T1 T2 T3
3752 1/1 reg_rdata_next[2] = intr_enable_acq_threshold_qs;
Tests: T1 T2 T3
3753 1/1 reg_rdata_next[3] = intr_enable_rx_overflow_qs;
Tests: T1 T2 T3
3754 1/1 reg_rdata_next[4] = intr_enable_controller_halt_qs;
Tests: T1 T2 T3
3755 1/1 reg_rdata_next[5] = intr_enable_scl_interference_qs;
Tests: T1 T2 T3
3756 1/1 reg_rdata_next[6] = intr_enable_sda_interference_qs;
Tests: T1 T2 T3
3757 1/1 reg_rdata_next[7] = intr_enable_stretch_timeout_qs;
Tests: T1 T2 T3
3758 1/1 reg_rdata_next[8] = intr_enable_sda_unstable_qs;
Tests: T1 T2 T3
3759 1/1 reg_rdata_next[9] = intr_enable_cmd_complete_qs;
Tests: T1 T2 T3
3760 1/1 reg_rdata_next[10] = intr_enable_tx_stretch_qs;
Tests: T1 T2 T3
3761 1/1 reg_rdata_next[11] = intr_enable_tx_threshold_qs;
Tests: T1 T2 T3
3762 1/1 reg_rdata_next[12] = intr_enable_acq_stretch_qs;
Tests: T1 T2 T3
3763 1/1 reg_rdata_next[13] = intr_enable_unexp_stop_qs;
Tests: T1 T2 T3
3764 1/1 reg_rdata_next[14] = intr_enable_host_timeout_qs;
Tests: T1 T2 T3
3765 end
3766
3767 addr_hit[2]: begin
3768 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
3769 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
3770 1/1 reg_rdata_next[2] = '0;
Tests: T1 T2 T3
3771 1/1 reg_rdata_next[3] = '0;
Tests: T1 T2 T3
3772 1/1 reg_rdata_next[4] = '0;
Tests: T1 T2 T3
3773 1/1 reg_rdata_next[5] = '0;
Tests: T1 T2 T3
3774 1/1 reg_rdata_next[6] = '0;
Tests: T1 T2 T3
3775 1/1 reg_rdata_next[7] = '0;
Tests: T1 T2 T3
3776 1/1 reg_rdata_next[8] = '0;
Tests: T1 T2 T3
3777 1/1 reg_rdata_next[9] = '0;
Tests: T1 T2 T3
3778 1/1 reg_rdata_next[10] = '0;
Tests: T1 T2 T3
3779 1/1 reg_rdata_next[11] = '0;
Tests: T1 T2 T3
3780 1/1 reg_rdata_next[12] = '0;
Tests: T1 T2 T3
3781 1/1 reg_rdata_next[13] = '0;
Tests: T1 T2 T3
3782 1/1 reg_rdata_next[14] = '0;
Tests: T1 T2 T3
3783 end
3784
3785 addr_hit[3]: begin
3786 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
3787 end
3788
3789 addr_hit[4]: begin
3790 1/1 reg_rdata_next[0] = ctrl_enablehost_qs;
Tests: T1 T2 T3
3791 1/1 reg_rdata_next[1] = ctrl_enabletarget_qs;
Tests: T1 T2 T3
3792 1/1 reg_rdata_next[2] = ctrl_llpbk_qs;
Tests: T1 T2 T3
3793 1/1 reg_rdata_next[3] = ctrl_nack_addr_after_timeout_qs;
Tests: T1 T2 T3
3794 1/1 reg_rdata_next[4] = ctrl_ack_ctrl_en_qs;
Tests: T1 T2 T3
3795 1/1 reg_rdata_next[5] = ctrl_multi_controller_monitor_en_qs;
Tests: T1 T2 T3
3796 1/1 reg_rdata_next[6] = ctrl_tx_stretch_ctrl_en_qs;
Tests: T1 T2 T3
3797 end
3798
3799 addr_hit[5]: begin
3800 1/1 reg_rdata_next[0] = status_fmtfull_qs;
Tests: T2 T3 T4
3801 1/1 reg_rdata_next[1] = status_rxfull_qs;
Tests: T2 T3 T4
3802 1/1 reg_rdata_next[2] = status_fmtempty_qs;
Tests: T2 T3 T4
3803 1/1 reg_rdata_next[3] = status_hostidle_qs;
Tests: T2 T3 T4
3804 1/1 reg_rdata_next[4] = status_targetidle_qs;
Tests: T2 T3 T4
3805 1/1 reg_rdata_next[5] = status_rxempty_qs;
Tests: T2 T3 T4
3806 1/1 reg_rdata_next[6] = status_txfull_qs;
Tests: T2 T3 T4
3807 1/1 reg_rdata_next[7] = status_acqfull_qs;
Tests: T2 T3 T4
3808 1/1 reg_rdata_next[8] = status_txempty_qs;
Tests: T2 T3 T4
3809 1/1 reg_rdata_next[9] = status_acqempty_qs;
Tests: T2 T3 T4
3810 1/1 reg_rdata_next[10] = status_ack_ctrl_stretch_qs;
Tests: T2 T3 T4
3811 end
3812
3813 addr_hit[6]: begin
3814 1/1 reg_rdata_next[7:0] = rdata_qs;
Tests: T2 T3 T4
3815 end
3816
3817 addr_hit[7]: begin
3818 1/1 reg_rdata_next[7:0] = '0;
Tests: T1 T2 T3
3819 1/1 reg_rdata_next[8] = '0;
Tests: T1 T2 T3
3820 1/1 reg_rdata_next[9] = '0;
Tests: T1 T2 T3
3821 1/1 reg_rdata_next[10] = '0;
Tests: T1 T2 T3
3822 1/1 reg_rdata_next[11] = '0;
Tests: T1 T2 T3
3823 1/1 reg_rdata_next[12] = '0;
Tests: T1 T2 T3
3824 end
3825
3826 addr_hit[8]: begin
3827 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
3828 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
3829 1/1 reg_rdata_next[7] = '0;
Tests: T1 T2 T3
3830 1/1 reg_rdata_next[8] = '0;
Tests: T1 T2 T3
3831 end
3832
3833 addr_hit[9]: begin
3834 1/1 reg_rdata_next[11:0] = host_fifo_config_rx_thresh_qs;
Tests: T2 T3 T4
3835 1/1 reg_rdata_next[27:16] = host_fifo_config_fmt_thresh_qs;
Tests: T2 T3 T4
3836 end
3837
3838 addr_hit[10]: begin
3839 1/1 reg_rdata_next[11:0] = target_fifo_config_tx_thresh_qs;
Tests: T1 T2 T3
3840 1/1 reg_rdata_next[27:16] = target_fifo_config_acq_thresh_qs;
Tests: T1 T2 T3
3841 end
3842
3843 addr_hit[11]: begin
3844 1/1 reg_rdata_next[11:0] = host_fifo_status_fmtlvl_qs;
Tests: T2 T3 T4
3845 1/1 reg_rdata_next[27:16] = host_fifo_status_rxlvl_qs;
Tests: T2 T3 T4
3846 end
3847
3848 addr_hit[12]: begin
3849 1/1 reg_rdata_next[11:0] = target_fifo_status_txlvl_qs;
Tests: T2 T3 T4
3850 1/1 reg_rdata_next[27:16] = target_fifo_status_acqlvl_qs;
Tests: T2 T3 T4
3851 end
3852
3853 addr_hit[13]: begin
3854 1/1 reg_rdata_next[0] = ovrd_txovrden_qs;
Tests: T1 T2 T3
3855 1/1 reg_rdata_next[1] = ovrd_sclval_qs;
Tests: T1 T2 T3
3856 1/1 reg_rdata_next[2] = ovrd_sdaval_qs;
Tests: T1 T2 T3
3857 end
3858
3859 addr_hit[14]: begin
3860 1/1 reg_rdata_next[15:0] = val_scl_rx_qs;
Tests: T2 T3 T4
3861 1/1 reg_rdata_next[31:16] = val_sda_rx_qs;
Tests: T2 T3 T4
3862 end
3863
3864 addr_hit[15]: begin
3865 1/1 reg_rdata_next[12:0] = timing0_thigh_qs;
Tests: T2 T3 T4
3866 1/1 reg_rdata_next[28:16] = timing0_tlow_qs;
Tests: T2 T3 T4
3867 end
3868
3869 addr_hit[16]: begin
3870 1/1 reg_rdata_next[9:0] = timing1_t_r_qs;
Tests: T1 T2 T3
3871 1/1 reg_rdata_next[24:16] = timing1_t_f_qs;
Tests: T1 T2 T3
3872 end
3873
3874 addr_hit[17]: begin
3875 1/1 reg_rdata_next[12:0] = timing2_tsu_sta_qs;
Tests: T2 T3 T4
3876 1/1 reg_rdata_next[28:16] = timing2_thd_sta_qs;
Tests: T2 T3 T4
3877 end
3878
3879 addr_hit[18]: begin
3880 1/1 reg_rdata_next[8:0] = timing3_tsu_dat_qs;
Tests: T1 T2 T3
3881 1/1 reg_rdata_next[28:16] = timing3_thd_dat_qs;
Tests: T1 T2 T3
3882 end
3883
3884 addr_hit[19]: begin
3885 1/1 reg_rdata_next[12:0] = timing4_tsu_sto_qs;
Tests: T2 T3 T4
3886 1/1 reg_rdata_next[28:16] = timing4_t_buf_qs;
Tests: T2 T3 T4
3887 end
3888
3889 addr_hit[20]: begin
3890 1/1 reg_rdata_next[29:0] = timeout_ctrl_val_qs;
Tests: T1 T2 T3
3891 1/1 reg_rdata_next[30] = timeout_ctrl_mode_qs;
Tests: T1 T2 T3
3892 1/1 reg_rdata_next[31] = timeout_ctrl_en_qs;
Tests: T1 T2 T3
3893 end
3894
3895 addr_hit[21]: begin
3896 1/1 reg_rdata_next[6:0] = target_id_address0_qs;
Tests: T2 T3 T4
3897 1/1 reg_rdata_next[13:7] = target_id_mask0_qs;
Tests: T2 T3 T4
3898 1/1 reg_rdata_next[20:14] = target_id_address1_qs;
Tests: T2 T3 T4
3899 1/1 reg_rdata_next[27:21] = target_id_mask1_qs;
Tests: T2 T3 T4
3900 end
3901
3902 addr_hit[22]: begin
3903 1/1 reg_rdata_next[7:0] = acqdata_abyte_qs;
Tests: T2 T3 T4
3904 1/1 reg_rdata_next[10:8] = acqdata_signal_qs;
Tests: T2 T3 T4
3905 end
3906
3907 addr_hit[23]: begin
3908 1/1 reg_rdata_next[7:0] = '0;
Tests: T2 T3 T4
3909 end
3910
3911 addr_hit[24]: begin
3912 1/1 reg_rdata_next[19:0] = host_timeout_ctrl_qs;
Tests: T1 T2 T3
3913 end
3914
3915 addr_hit[25]: begin
3916 1/1 reg_rdata_next[30:0] = target_timeout_ctrl_val_qs;
Tests: T2 T3 T4
3917 1/1 reg_rdata_next[31] = target_timeout_ctrl_en_qs;
Tests: T2 T3 T4
3918 end
3919
3920 addr_hit[26]: begin
3921 1/1 reg_rdata_next[7:0] = target_nack_count_qs;
Tests: T2 T3 T4
3922 end
3923
3924 addr_hit[27]: begin
3925 1/1 reg_rdata_next[8:0] = target_ack_ctrl_nbytes_qs;
Tests: T2 T3 T4
3926 1/1 reg_rdata_next[31] = '0;
Tests: T2 T3 T4
3927 end
3928
3929 addr_hit[28]: begin
3930 1/1 reg_rdata_next[7:0] = acq_fifo_next_data_qs;
Tests: T1 T2 T3
3931 end
3932
3933 addr_hit[29]: begin
3934 1/1 reg_rdata_next[30:0] = host_nack_handler_timeout_val_qs;
Tests: T1 T2 T3
3935 1/1 reg_rdata_next[31] = host_nack_handler_timeout_en_qs;
Tests: T1 T2 T3
3936 end
3937
3938 addr_hit[30]: begin
3939 1/1 reg_rdata_next[0] = controller_events_nack_qs;
Tests: T1 T2 T3
3940 1/1 reg_rdata_next[1] = controller_events_unhandled_nack_timeout_qs;
Tests: T1 T2 T3
3941 1/1 reg_rdata_next[2] = controller_events_bus_timeout_qs;
Tests: T1 T2 T3
3942 1/1 reg_rdata_next[3] = controller_events_arbitration_lost_qs;
Tests: T1 T2 T3
3943 end
3944
3945 addr_hit[31]: begin
3946 1/1 reg_rdata_next[0] = target_events_tx_pending_qs;
Tests: T1 T2 T3
3947 1/1 reg_rdata_next[1] = target_events_bus_timeout_qs;
Tests: T1 T2 T3
3948 1/1 reg_rdata_next[2] = target_events_arbitration_lost_qs;
Tests: T1 T2 T3
3949 end
3950
3951 default: begin
3952 reg_rdata_next = '1;
3953 end
3954 endcase
3955 end
3956
3957 // shadow busy
3958 logic shadow_busy;
3959 assign shadow_busy = 1'b0;
3960
3961 // register busy
3962 unreachable assign reg_busy = shadow_busy;
3963
3964 // Unused signal tieoff
3965
3966 // wdata / byte enable are not always fully used
3967 // add a blanket unused statement to handle lint waivers
3968 logic unused_wdata;
3969 logic unused_be;
3970 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
3971 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3