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129 always_comb begin : counter_functions
130 1/1 tcount_d = tcount_q;
Tests: T1 T2 T3
131 1/1 if (load_tcount) begin
Tests: T1 T2 T3
132 1/1 unique case (tcount_sel)
Tests: T10 T44 T45
133 1/1 tSetupData : tcount_d = 13'(t_r_i) + 13'(tsu_dat_i);
Tests: T10 T45 T46
134 1/1 tHoldData : tcount_d = 16'(thd_dat_i);
Tests: T10 T44 T45
135 0/1 ==> tNoDelay : tcount_d = 16'h0001;
136 default : tcount_d = 16'h0001;
137 endcase
138 1/1 end else if (target_enable_i) begin
Tests: T1 T2 T3
139 1/1 tcount_d = tcount_q - 1'b1;
Tests: T10 T44 T45
140 end
MISSING_ELSE
141 end
142
143 always_ff @ (posedge clk_i or negedge rst_ni) begin : clk_counter
144 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
145 1/1 tcount_q <= '1;
Tests: T1 T2 T3
146 end else begin
147 1/1 tcount_q <= tcount_d;
Tests: T1 T2 T3
148 end
149 end
150
151 // Keep track of how long the target has been stretching. This is used to
152 // timeout and send a NACK instead.
153 always_ff @ (posedge clk_i or negedge rst_ni) begin : clk_nack_after_stretch
154 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
155 1/1 stretch_active_cnt <= '0;
Tests: T1 T2 T3
156 1/1 end else if (actively_stretching) begin
Tests: T1 T2 T3
157 1/1 stretch_active_cnt <= stretch_active_cnt + 1'b1;
Tests: T10 T45 T46
158 1/1 end else if (start_detect_i && target_idle_o) begin
Tests: T1 T2 T3
159 1/1 stretch_active_cnt <= '0;
Tests: T2 T4 T5
160 end
MISSING_ELSE
161 end
162
163 // Track remaining number of bytes that may be automatically ACK'd
164 always_ff @(posedge clk_i or negedge rst_ni) begin
165 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
166 1/1 auto_ack_cnt_q <= '0;
Tests: T1 T2 T3
167 1/1 end else if (auto_ack_load_i && ack_ctrl_stretching) begin
Tests: T1 T2 T3
168 // Loads are only accepted while stretching to avoid races.
169 1/1 auto_ack_cnt_q <= auto_ack_load_value_i;
Tests: T46 T47 T48
170 end else begin
171 1/1 auto_ack_cnt_q <= auto_ack_cnt_d;
Tests: T1 T2 T3
172 end
173 end
174
175 1/1 assign can_auto_ack = !ack_ctrl_mode_i || (auto_ack_cnt_q > '0);
Tests: T1 T2 T3
176 1/1 assign auto_ack_cnt_o = auto_ack_cnt_q;
Tests: T1 T2 T3
177 1/1 assign ack_ctrl_stretching_o = ack_ctrl_stretching;
Tests: T1 T2 T3
178 1/1 assign acq_fifo_next_data_o = input_byte;
Tests: T1 T2 T3
179
180 // Latch whether this transaction is to be NACK'd.
181 always_ff @ (posedge clk_i or negedge rst_ni) begin : clk_nack_transaction
182 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
183 1/1 nack_transaction_q <= 1'b0;
Tests: T1 T2 T3
184 end else begin
185 1/1 nack_transaction_q <= nack_transaction_d;
Tests: T1 T2 T3
186 end
187 end
188
189 // SDA and SCL at the previous clock edge
190 always_ff @ (posedge clk_i or negedge rst_ni) begin : bus_prev
191 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
192 1/1 scl_i_q <= 1'b1;
Tests: T1 T2 T3
193 end else begin
194 1/1 scl_i_q <= scl_i;
Tests: T1 T2 T3
195 end
196 end
197
198 // Track the transaction framing and this target's participation in it.
199 always_ff @ (posedge clk_i or negedge rst_ni) begin
200 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
201 1/1 restart_det_q <= 1'b0;
Tests: T1 T2 T3
202 1/1 xact_for_us_q <= 1'b0;
Tests: T1 T2 T3
203 1/1 xfer_for_us_q <= 1'b0;
Tests: T1 T2 T3
204 end else begin
205 1/1 restart_det_q <= restart_det_d;
Tests: T1 T2 T3
206 1/1 xact_for_us_q <= xact_for_us_d;
Tests: T1 T2 T3
207 1/1 xfer_for_us_q <= xfer_for_us_d;
Tests: T1 T2 T3
208 end
209 end
210
211 // Bit counter on the target side
212 1/1 assign bit_ack = (bit_idx == 4'd8); // ack
Tests: T1 T2 T3
213
214 // Increment counter on negative SCL edge
215 always_ff @ (posedge clk_i or negedge rst_ni) begin : tgt_bit_counter
216 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
217 1/1 bit_idx <= 4'd0;
Tests: T1 T2 T3
218 1/1 end else if (start_detect_i) begin
Tests: T1 T2 T3
219 1/1 bit_idx <= 4'd0;
Tests: T2 T4 T5
220 1/1 end else if (scl_i_q && !scl_i) begin
Tests: T1 T2 T3
221 // input byte clear is always asserted on a "start"
222 // condition.
223 2/2 if (input_byte_clr || bit_ack) bit_idx <= 4'd0;
Tests: T1 T2 T3 | T2 T4 T5
224 1/1 else bit_idx <= bit_idx + 1'b1;
Tests: T1 T2 T3
225 end else begin
226 1/1 bit_idx <= bit_idx;
Tests: T1 T2 T3
227 end
228 end
229
230 // Deserializer for a byte read from the bus on the target side
231 1/1 assign address0_match = ((input_byte[7:1] & target_mask0_i) == target_address0_i) &&
Tests: T1 T2 T3
232 (target_mask0_i != '0);
233 1/1 assign address1_match = ((input_byte[7:1] & target_mask1_i) == target_address1_i) &&
Tests: T1 T2 T3
234 (target_mask1_i != '0);
235 1/1 assign address_match = (address0_match || address1_match);
Tests: T1 T2 T3
236
237 // Shift data in on positive SCL edge
238 always_ff @ (posedge clk_i or negedge rst_ni) begin : tgt_input_register
239 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
240 1/1 input_byte <= 8'h00;
Tests: T1 T2 T3
241 1/1 end else if (input_byte_clr) begin
Tests: T1 T2 T3
242 1/1 input_byte <= 8'h00;
Tests: T10 T44 T45
243 1/1 end else if (!scl_i_q && scl_i) begin
Tests: T1 T2 T3
244 2/2 if (!bit_ack) input_byte[7:0] <= {input_byte[6:0], sda_i}; // MSB goes in first
Tests: T2 T4 T5 | T2 T4 T5
MISSING_ELSE
245 end
MISSING_ELSE
246 end
247
248 // Detection by the target of ACK bit sent by the host
249 always_ff @ (posedge clk_i or negedge rst_ni) begin : host_ack_register
250 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
251 1/1 host_ack <= 1'b0;
Tests: T1 T2 T3
252 1/1 end else if (!scl_i_q && scl_i) begin
Tests: T1 T2 T3
253 2/2 if (bit_ack) host_ack <= ~sda_i;
Tests: T2 T4 T5 | T2 T4 T5
MISSING_ELSE
254 end
MISSING_ELSE
255 end
256
257 // An artificial acq_fifo_wready is used here to ensure we always have
258 // space to asborb a stop / repeat start format byte. Without guaranteeing
259 // space for this entry, the target module would need to stretch the
260 // repeat start / stop indication. If a system does not support stretching,
261 // there's no good way for a stop to be NACK'd.
262 // Besides the space necessary for the stop format byte, we also need one
263 // space to send a NACK. This means that we can notify software that a NACK
264 // has happened while still keeping space for a subsequent stop or repeated
265 // start.
266 logic [AcqFifoDepthWidth-1:0] acq_fifo_remainder;
267 1/1 assign acq_fifo_remainder = AcqFifoDepth - acq_fifo_depth_i;
Tests: T1 T2 T3
268 // This is used for acq_fifo_full_o to send the ACQ FIFO full alert to
269 // software.
270 1/1 assign acq_fifo_plenty_space = acq_fifo_remainder > AcqFifoDepthWidth'(2);
Tests: T1 T2 T3
271 1/1 assign acq_fifo_full_or_last_space = acq_fifo_remainder <= AcqFifoDepthWidth'(1);
Tests: T1 T2 T3
272
273 // State definitions
274 typedef enum logic [4:0] {
275 Idle,
276 /////////////////////////
277 // Target function states
278 /////////////////////////
279
280 // Target function receives start and address from external host
281 AcquireStart, AddrRead,
282 // Target function acknowledges the address and returns an ack to external host
283 AddrAckWait, AddrAckSetup, AddrAckPulse, AddrAckHold,
284 // Target function sends read data to external host-receiver
285 TransmitWait, TransmitSetup, TransmitPulse, TransmitHold,
286 // Target function receives ack from external host
287 TransmitAck, TransmitAckPulse, WaitForStop,
288 // Target function receives write data from the external host
289 AcquireByte,
290 // Target function sends ack to external host
291 AcquireAckWait, AcquireAckSetup, AcquireAckPulse, AcquireAckHold,
292 // Target function clock stretch handling.
293 StretchAddrAck, StretchAddrAckSetup, StretchAddr,
294 StretchTx, StretchTxSetup,
295 StretchAcqFull, StretchAcqSetup
296 } state_e;
297
298 state_e state_q, state_d;
299
300 logic rw_bit_q;
301 always_ff @(posedge clk_i or negedge rst_ni) begin
302 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
303 1/1 rw_bit_q <= '0;
Tests: T1 T2 T3
304 1/1 end else if (bit_ack && address_match) begin
Tests: T1 T2 T3
305 1/1 rw_bit_q <= rw_bit;
Tests: T10 T44 T45
306 end
MISSING_ELSE
307 end
308
309 // Reverse the bit order since data should be sent out MSB first
310 logic [TX_FIFO_WIDTH-1:0] tx_fifo_rdata;
311 assign tx_fifo_rdata = {<<1{tx_fifo_rdata_i}};
312
313 // The usage of target_idle_o directly confuses xcelium and leads the
314 // the simulator to a combinational loop. While it may be a tool recognized
315 // loop, it is not an actual physical loop, since target_idle affects only
316 // state_d, which is not used directly by any logic in this module.
317 // This is a work around for a known tool limitation.
318 logic target_idle;
319 1/1 assign target_idle = target_idle_o;
Tests: T1 T2 T3
320
321 // During a host issued read, a stop was received without first seeing a nack.
322 // This may be harmless but is technically illegal behavior, notify software.
323 1/1 assign event_unexp_stop_o = target_enable_i & xfer_for_us_q & rw_bit_q &
Tests: T1 T2 T3
324 stop_detect_i & !expect_stop;
325
326 // Record each transaction that gets NACK'd.
327 1/1 assign event_target_nack_o = !nack_transaction_q && nack_transaction_d;
Tests: T1 T2 T3
328
329 // Outputs for each state
330 always_comb begin : state_outputs
331 1/1 target_idle_o = 1'b1;
Tests: T1 T2 T3
332 1/1 sda_d = 1'b1;
Tests: T1 T2 T3
333 1/1 scl_d = 1'b1;
Tests: T1 T2 T3
334 1/1 transmitting_o = 1'b0;
Tests: T1 T2 T3
335 1/1 tx_fifo_rready_o = 1'b0;
Tests: T1 T2 T3
336 1/1 acq_fifo_wvalid_o = 1'b0;
Tests: T1 T2 T3
337 1/1 acq_fifo_wdata_o = ACQ_FIFO_WIDTH'(0);
Tests: T1 T2 T3
338 1/1 event_cmd_complete_o = 1'b0;
Tests: T1 T2 T3
339 1/1 rw_bit = rw_bit_q;
Tests: T1 T2 T3
340 1/1 expect_stop = 1'b0;
Tests: T1 T2 T3
341 1/1 restart_det_d = restart_det_q;
Tests: T1 T2 T3
342 1/1 xact_for_us_d = xact_for_us_q;
Tests: T1 T2 T3
343 1/1 xfer_for_us_d = xfer_for_us_q;
Tests: T1 T2 T3
344 1/1 auto_ack_cnt_d = auto_ack_cnt_q;
Tests: T1 T2 T3
345 1/1 ack_ctrl_stretching = 1'b0;
Tests: T1 T2 T3
346 1/1 nack_transaction_d = nack_transaction_q;
Tests: T1 T2 T3
347 1/1 actively_stretching = 1'b0;
Tests: T1 T2 T3
348 1/1 event_tx_arbitration_lost_o = 1'b0;
Tests: T1 T2 T3
349 1/1 event_tx_bus_timeout_o = 1'b0;
Tests: T1 T2 T3
350 1/1 event_read_cmd_received_o = 1'b0;
Tests: T1 T2 T3
351
352 1/1 unique case (state_q)
Tests: T1 T2 T3
353 // Idle: initial state, SDA is released (high), SCL is released if the
354 // bus is idle. Otherwise, if no STOP condition has been sent yet,
355 // continue pulling SCL low in host mode.
356 Idle : begin
357 1/1 sda_d = 1'b1;
Tests: T1 T2 T3
358 1/1 scl_d = 1'b1;
Tests: T1 T2 T3
359 1/1 restart_det_d = 1'b0;
Tests: T1 T2 T3
360 1/1 xact_for_us_d = 1'b0;
Tests: T1 T2 T3
361 1/1 xfer_for_us_d = 1'b0;
Tests: T1 T2 T3
362 1/1 nack_transaction_d = 1'b0;
Tests: T1 T2 T3
363 end
364
365 /////////////////
366 // TARGET MODE //
367 /////////////////
368
369 // AcquireStart: hold for the end of the start condition
370 AcquireStart : begin
371 1/1 target_idle_o = 1'b0;
Tests: T10 T44 T45
372 1/1 xfer_for_us_d = 1'b0;
Tests: T10 T44 T45
373 1/1 auto_ack_cnt_d = '0;
Tests: T10 T44 T45
374 end
375 // AddrRead: read and compare target address
376 AddrRead : begin
377 1/1 target_idle_o = 1'b0;
Tests: T10 T44 T45
378 1/1 rw_bit = input_byte[0];
Tests: T10 T44 T45
379
380 1/1 if (bit_ack) begin
Tests: T10 T44 T45
381 1/1 if (address_match) begin
Tests: T10 T44 T45
382 1/1 xact_for_us_d = 1'b1;
Tests: T10 T44 T45
383 1/1 xfer_for_us_d = 1'b1;
Tests: T10 T44 T45
384 end
MISSING_ELSE
385 end
MISSING_ELSE
386 end
387 // AddrAckWait: pause for hold time before acknowledging
388 AddrAckWait : begin
389 1/1 target_idle_o = 1'b0;
Tests: T10 T44 T45
390
391 1/1 if (scl_i) begin
Tests: T10 T44 T45
392 // The controller is going too fast. Abandon the transaction.
393 // Nothing gets recorded for this case.
394 0/1 ==> nack_transaction_d = 1'b1;
395 end
MISSING_ELSE
396 end
397 // AddrAckSetup: target pulls SDA low while SCL is low
398 AddrAckSetup : begin
399 1/1 target_idle_o = 1'b0;
Tests: T10 T44 T45
400 1/1 sda_d = 1'b0;
Tests: T10 T44 T45
401 1/1 transmitting_o = 1'b1;
Tests: T10 T44 T45
402 end
403 // AddrAckPulse: target pulls SDA low while SCL is released
404 AddrAckPulse : begin
405 1/1 target_idle_o = 1'b0;
Tests: T10 T44 T45
406 1/1 sda_d = 1'b0;
Tests: T10 T44 T45
407 1/1 transmitting_o = 1'b1;
Tests: T10 T44 T45
408 end
409 // AddrAckHold: target pulls SDA low while SCL is pulled low
410 AddrAckHold : begin
411 1/1 target_idle_o = 1'b0;
Tests: T10 T44 T45
412 1/1 sda_d = 1'b0;
Tests: T10 T44 T45
413 1/1 transmitting_o = 1'b1;
Tests: T10 T44 T45
414
415 // Upon transition to next state, populate the acquisition fifo
416 1/1 if (tcount_q == 20'd1) begin
Tests: T10 T44 T45
417 1/1 if (nack_transaction_q) begin
Tests: T10 T44 T45
418 // No need to record anything here. We already recorded the first
419 // NACK'd byte in a stretch state or abandoned the transaction in
420 // AddrAckWait.
421 1/1 end else if (!stretch_addr) begin
Tests: T10 T44 T45
422 // Only write to fifo if stretching conditions are not met
423 1/1 acq_fifo_wvalid_o = 1'b1;
Tests: T10 T44 T45
424 1/1 event_read_cmd_received_o = rw_bit_q;
Tests: T10 T44 T45
425 end
MISSING_ELSE
426
427 1/1 if (restart_det_q) begin
Tests: T10 T44 T45
428 1/1 acq_fifo_wdata_o = {AcqRestart, input_byte};
Tests: T10 T44 T45
429 end else begin
430 1/1 acq_fifo_wdata_o = {AcqStart, input_byte};
Tests: T10 T44 T45
431 end
432 end
==> MISSING_ELSE
433 end
434 // TransmitWait: Check if data is available prior to transmit
435 TransmitWait : begin
436 1/1 target_idle_o = 1'b0;
Tests: T10 T44 T45
437 end
438 // TransmitSetup: target shifts indexed bit onto SDA while SCL is low
439 TransmitSetup : begin
440 1/1 target_idle_o = 1'b0;
Tests: T10 T44 T45
441 1/1 sda_d = tx_fifo_rdata[3'(bit_idx)];
Tests: T10 T44 T45
442 1/1 transmitting_o = 1'b1;
Tests: T10 T44 T45
443 end
444 // TransmitPulse: target holds indexed bit onto SDA while SCL is released
445 TransmitPulse : begin
446 1/1 target_idle_o = 1'b0;
Tests: T10 T44 T45
447
448 // Hold value
449 1/1 sda_d = sda_q;
Tests: T10 T44 T45
450 1/1 transmitting_o = 1'b1;
Tests: T10 T44 T45
451 end
452 // TransmitHold: target holds indexed bit onto SDA while SCL is pulled low, for the hold time
453 TransmitHold : begin
454 1/1 target_idle_o = 1'b0;
Tests: T10 T44 T45
455
456 // Hold value
457 1/1 sda_d = sda_q;
Tests: T10 T44 T45
458 1/1 transmitting_o = 1'b1;
Tests: T10 T44 T45
459 end
460 // TransmitAck: target waits for host to ACK transmission
461 TransmitAck : begin
462 1/1 target_idle_o = 1'b0;
Tests: T10 T44 T45
463 end
464 TransmitAckPulse : begin
465 1/1 target_idle_o = 1'b0;
Tests: T10 T44 T45
466 1/1 if (!scl_i) begin
Tests: T10 T44 T45
467 // Pop Fifo regardless of ack/nack
468 1/1 tx_fifo_rready_o = 1'b1;
Tests: T10 T44 T45
469 end
MISSING_ELSE
470 end
471 // WaitForStop just waiting for host to trigger a stop after nack
472 WaitForStop : begin
473 1/1 target_idle_o = 1'b0;
Tests: T44 T45 T46
474 1/1 expect_stop = 1'b1;
Tests: T44 T45 T46
475 1/1 sda_d = 1'b1;
Tests: T44 T45 T46
476 end
477 // AcquireByte: target acquires a byte
478 AcquireByte : begin
479 1/1 target_idle_o = 1'b0;
Tests: T10 T44 T45
480 end
481 // AcquireAckWait: pause before acknowledging
482 AcquireAckWait : begin
483 1/1 target_idle_o = 1'b0;
Tests: T10 T44 T45
484 1/1 if (scl_i) begin
Tests: T10 T44 T45
485 // The controller is going too fast. Abandon the transaction.
486 // Nothing is recorded for this case.
487 0/1 ==> nack_transaction_d = 1'b1;
488 end
MISSING_ELSE
489 end
490 // AcquireAckSetup: target pulls SDA low while SCL is low
491 AcquireAckSetup : begin
492 1/1 target_idle_o = 1'b0;
Tests: T10 T44 T45
493 1/1 sda_d = 1'b0;
Tests: T10 T44 T45
494 1/1 transmitting_o = 1'b1;
Tests: T10 T44 T45
495 end
496 // AcquireAckPulse: target pulls SDA low while SCL is released
497 AcquireAckPulse : begin
498 1/1 target_idle_o = 1'b0;
Tests: T10 T44 T45
499 1/1 sda_d = 1'b0;
Tests: T10 T44 T45
500 1/1 transmitting_o = 1'b1;
Tests: T10 T44 T45
501 end
502 // AcquireAckHold: target pulls SDA low while SCL is pulled low
503 AcquireAckHold : begin
504 1/1 target_idle_o = 1'b0;
Tests: T10 T44 T45
505 1/1 sda_d = 1'b0;
Tests: T10 T44 T45
506 1/1 transmitting_o = 1'b1;
Tests: T10 T44 T45
507
508 1/1 if (tcount_q == 20'd1) begin
Tests: T10 T44 T45
509 1/1 auto_ack_cnt_d = auto_ack_cnt_q - 1'b1;
Tests: T10 T44 T45
510 1/1 acq_fifo_wvalid_o = ~stretch_rx; // assert that acq_fifo has space
Tests: T10 T44 T45
511 1/1 acq_fifo_wdata_o = {AcqData, input_byte}; // transfer data to acq_fifo
Tests: T10 T44 T45
512 end
==> MISSING_ELSE
513 end
514 // StretchAddrAck: target stretches the clock if matching address cannot be
515 // deposited yet. (During ACK phase)
516 StretchAddrAck : begin
517 1/1 target_idle_o = 1'b0;
Tests: T49 T50 T51
518 1/1 scl_d = 1'b0;
Tests: T49 T50 T51
519 1/1 actively_stretching = stretch_addr;
Tests: T49 T50 T51
520
521 1/1 if (nack_timeout) begin
Tests: T49 T50 T51
522 1/1 nack_transaction_d = 1'b1;
Tests: T49 T50 T51
523 // Record NACK'd Start bytes as long as there is space.
524 // The next state is always WaitForStop, so the ACQ FIFO needs to be
525 // written here.
526 1/1 acq_fifo_wvalid_o = !acq_fifo_full_or_last_space;
Tests: T49 T50 T51
527 1/1 acq_fifo_wdata_o = {AcqNackStart, input_byte};
Tests: T49 T50 T51
528 end
MISSING_ELSE
529 end
530 // StretchAddrAckSetup: target pulls SDA low while pulling SCL low for
531 // setup time. This is to prepare the setup time after a stretch.
532 StretchAddrAckSetup : begin
533 0/1 ==> target_idle_o = 1'b0;
534 0/1 ==> sda_d = 1'b0;
535 0/1 ==> scl_d = 1'b0;
536 0/1 ==> transmitting_o = 1'b1;
537 end
538 // StretchAddr: target stretches the clock if matching address cannot be
539 // deposited yet.
540 StretchAddr : begin
541 1/1 target_idle_o = 1'b0;
Tests: T10 T52 T53
542 1/1 scl_d = 1'b0;
Tests: T10 T52 T53
543 1/1 actively_stretching = stretch_addr;
Tests: T10 T52 T53
544
545 1/1 if (nack_timeout) begin
Tests: T10 T52 T53
546 1/1 nack_transaction_d = 1'b1;
Tests: T54 T55
547 // Record NACK'd Start bytes as long as there is space.
548 // The next state is always WaitForStop, so the ACQ FIFO needs to be
549 // written here.
550 1/1 acq_fifo_wvalid_o = !acq_fifo_full_or_last_space;
Tests: T54 T55
551 1/1 acq_fifo_wdata_o = {AcqNackStart, input_byte};
Tests: T54 T55
552 1/1 end else if (!stretch_addr) begin
Tests: T10 T52 T53
553 1/1 acq_fifo_wvalid_o = 1'b1;
Tests: T52 T56 T57
554 1/1 if (restart_det_q) begin
Tests: T52 T56 T57
555 1/1 acq_fifo_wdata_o = {AcqRestart, input_byte};
Tests: T52 T56 T57
556 end else begin
557 1/1 acq_fifo_wdata_o = {AcqStart, input_byte};
Tests: T57 T58 T59
558 end
559 end
MISSING_ELSE
560 end
561 // StretchTx: target stretches the clock when tx_fifo is empty
562 StretchTx : begin
563 1/1 target_idle_o = 1'b0;
Tests: T10 T45 T46
564 1/1 scl_d = 1'b0;
Tests: T10 T45 T46
565 1/1 actively_stretching = stretch_tx;
Tests: T10 T45 T46
566
567 1/1 if (nack_timeout) begin
Tests: T10 T45 T46
568 // Only the NackStop will get recorded (later) to provide ACQ FIFO
569 // history of the failed transaction. Meanwhile, the NACK timeout
570 // will still get reported.
571 1/1 nack_transaction_d = 1'b1;
Tests: T60 T61 T62
572 end
MISSING_ELSE
573 end
574 // StretchTxSetup: drive the return data
575 StretchTxSetup : begin
576 1/1 target_idle_o = 1'b0;
Tests: T10 T45 T46
577 1/1 scl_d = 1'b0;
Tests: T10 T45 T46
578 1/1 sda_d = tx_fifo_rdata[3'(bit_idx)];
Tests: T10 T45 T46
579 1/1 transmitting_o = 1'b1;
Tests: T10 T45 T46
580 end
581 // StretchAcqFull: target stretches the clock when acq_fifo is full
582 StretchAcqFull : begin
583 1/1 target_idle_o = 1'b0;
Tests: T10 T46 T47
584 1/1 scl_d = 1'b0;
Tests: T10 T46 T47
585 1/1 ack_ctrl_stretching = !can_auto_ack;
Tests: T10 T46 T47
586 1/1 actively_stretching = stretch_rx;
Tests: T10 T46 T47
587
588
589 1/1 if (nack_timeout || (sw_nack_i && !can_auto_ack)) begin
Tests: T10 T46 T47
590 1/1 nack_transaction_d = 1'b1;
Tests: T63 T64 T65
591 1/1 acq_fifo_wvalid_o = !acq_fifo_full_or_last_space;
Tests: T63 T64 T65
592 1/1 acq_fifo_wdata_o = {AcqNack, input_byte};
Tests: T63 T64 T65
593 end
MISSING_ELSE
594 end
595 // StretchAcqSetup: Drive the ACK and wait for tSetupData before
596 // releasing SCL
597 StretchAcqSetup : begin
598 1/1 target_idle_o = 1'b0;
Tests: T46 T47 T48
599 1/1 scl_d = 1'b0;
Tests: T46 T47 T48
600 1/1 sda_d = 1'b0;
Tests: T46 T47 T48
601 1/1 transmitting_o = 1'b1;
Tests: T46 T47 T48
602 end
603 // default
604 default : begin
605 target_idle_o = 1'b1;
606 sda_d = 1'b1;
607 scl_d = 1'b1;
608 transmitting_o = 1'b0;
609 tx_fifo_rready_o = 1'b0;
610 acq_fifo_wvalid_o = 1'b0;
611 acq_fifo_wdata_o = ACQ_FIFO_WIDTH'(0);
612 event_cmd_complete_o = 1'b0;
613 restart_det_d = 1'b0;
614 xact_for_us_d = 1'b0;
615 auto_ack_cnt_d = '0;
616 ack_ctrl_stretching = 1'b0;
617 nack_transaction_d = 1'b0;
618 actively_stretching = 1'b0;
619 end
620 endcase // unique case (state_q)
621
622 // start / stop override
623 1/1 if (target_enable_i && (stop_detect_i || bus_timeout_i)) begin
Tests: T1 T2 T3
624 1/1 event_cmd_complete_o = xfer_for_us_q;
Tests: T10 T44 T45
625 1/1 event_tx_bus_timeout_o = bus_timeout_i && rw_bit_q;
Tests: T10 T44 T45
626 // Note that we assume the ACQ FIFO can accept a new item and will
627 // receive the arbiter grant without delay. No other FIFOs should have
628 // activity during a Start or Stop symbol.
629 // TODO: Add an assertion.
630 1/1 acq_fifo_wvalid_o = xact_for_us_q;
Tests: T10 T44 T45
631 1/1 if (nack_transaction_q || bus_timeout_i) begin
Tests: T10 T44 T45
632 1/1 acq_fifo_wdata_o = {AcqNackStop, input_byte};
Tests: T63 T64 T60
633 end else begin
634 1/1 acq_fifo_wdata_o = {AcqStop, input_byte};
Tests: T10 T44 T45
635 end
636 1/1 end else if (target_enable_i && start_detect_i) begin
Tests: T1 T2 T3
637 1/1 restart_det_d = !target_idle_o;
Tests: T10 T44 T45
638 1/1 event_cmd_complete_o = xfer_for_us_q;
Tests: T10 T44 T45
639 1/1 end else if (arbitration_lost_i) begin
Tests: T1 T2 T3
640 0/1 ==> nack_transaction_d = 1'b1;
641 0/1 ==> event_cmd_complete_o = xfer_for_us_q;
642 0/1 ==> event_tx_arbitration_lost_o = rw_bit_q;
643 end
MISSING_ELSE
644 end
645
646 1/1 assign stretch_rx = !acq_fifo_plenty_space || !can_auto_ack;
Tests: T1 T2 T3
647 1/1 assign stretch_addr = !acq_fifo_plenty_space;
Tests: T1 T2 T3
648
649 // This condition determines whether this target has stretched beyond the
650 // timeout in which case it must now send a NACK to the host.
651 1/1 assign nack_timeout = nack_timeout_en_i && stretch_active_cnt >= nack_timeout_i;
Tests: T1 T2 T3
652
653 // Stretch Tx phase when:
654 // 1. When there is no data to return to host
655 // 2. When the acq_fifo contains any entry other than a singular start condition
656 // read command.
657 // 3. When there are unhandled events set in the TX_EVENTS CSR. This is
658 // a synchronization point with software, which needs to clear them
659 // first.
660 //
661 // Besides the unhandled events, only the fifo depth is checked here, because
662 // stretch_tx is only evaluated by the fsm on the read path. This means a read
663 // start byte has already been deposited, and there is no need for checking
664 // the value of the current state for this signal.
665 1/1 assign stretch_tx = !tx_fifo_rvalid_i || unhandled_tx_stretch_event_i ||
Tests: T1 T2 T3
666 (acq_fifo_depth_i > AcqFifoDepthWidth'(1'b1));
667
668 // Only used for assertion
669 logic unused_acq_rdata;
670 1/1 assign unused_acq_rdata = |acq_fifo_rdata_i;
Tests: T1 T2 T3
671
672 // Conditional state transition
673 always_comb begin : state_functions
674 1/1 state_d = state_q;
Tests: T1 T2 T3
675 1/1 load_tcount = 1'b0;
Tests: T1 T2 T3
676 1/1 tcount_sel = tNoDelay;
Tests: T1 T2 T3
677 1/1 input_byte_clr = 1'b0;
Tests: T1 T2 T3
678 1/1 event_tx_stretch_o = 1'b0;
Tests: T1 T2 T3
679
680 1/1 unique case (state_q)
Tests: T1 T2 T3
681 // Idle: initial state, SDA and SCL are released (high)
682 Idle : begin
683 // The bus is idle. Waiting for a Start.
684 end
685
686 /////////////////
687 // TARGET MODE //
688 /////////////////
689
690 // AcquireStart: hold for the end of the start condition
691 AcquireStart : begin
692 1/1 if (!scl_i) begin
Tests: T10 T44 T45
693 1/1 state_d = AddrRead;
Tests: T10 T44 T45
694 1/1 input_byte_clr = 1'b1;
Tests: T10 T44 T45
695 end
MISSING_ELSE
696 end
697 // AddrRead: read and compare target address
698 AddrRead : begin
699 // bit_ack goes high the cycle after scl_i goes low, after the 8th bit
700 // was captured.
701 1/1 if (bit_ack) begin
Tests: T10 T44 T45
702 1/1 if (address_match) begin
Tests: T10 T44 T45
703 1/1 state_d = AddrAckWait;
Tests: T10 T44 T45
704 // Wait for hold time to avoid interfering with the controller.
705 1/1 load_tcount = 1'b1;
Tests: T10 T44 T45
706 1/1 tcount_sel = tHoldData;
Tests: T10 T44 T45
707 end else begin // !address_match
708 // This means this transfer is not meant for us.
709 1/1 state_d = WaitForStop;
Tests: T48 T66 T67
710 end
711 end
MISSING_ELSE
712 end
713 // AddrAckWait: pause for hold time before acknowledging
714 AddrAckWait : begin
715 1/1 if (scl_i) begin
Tests: T10 T44 T45
716 // The controller is going too fast. Abandon the transaction.
717 0/1 ==> state_d = WaitForStop;
718 1/1 end else if (tcount_q == 20'd1) begin
Tests: T10 T44 T45
719 1/1 if (!nack_addr_after_timeout_i) begin
Tests: T10 T44 T45
720 // Always ACK addresses in this mode.
721 1/1 state_d = AddrAckSetup;
Tests: T10 T44 T45
722 end else begin
723 1/1 if (nack_transaction_q) begin
Tests: T64 T65 T68
724 // We must have stretched before, and software has been notified
725 // through an ACQ FIFO full event. For writes we should NACK all
726 // bytes in the transfer unconditionally. For reads, we NACK
727 // the address byte, then release SDA for the rest of the
728 // transfer.
729 // Essentially, we're waiting for the end of the transaction.
730 0/1 ==> state_d = WaitForStop;
731 1/1 end else if (stretch_addr) begin
Tests: T64 T65 T68
732 // Not enough bytes to capture the Start/address byte, but might
733 // need to NACK.
734 1/1 state_d = StretchAddrAck;
Tests: T49 T50 T51
735 end else begin
736 // The transaction hasn't already been NACK'd, and there is
737 // room in the ACQ FIFO. Proceed.
738 1/1 state_d = AddrAckSetup;
Tests: T64 T65 T68
739 end
740 end
741 end
==> MISSING_ELSE
742 end
743 // AddrAckSetup: target pulls SDA low while SCL is low
744 AddrAckSetup : begin
745 2/2 if (scl_i) state_d = AddrAckPulse;
Tests: T10 T44 T45 | T10 T44 T45
MISSING_ELSE
746 end
747 // AddrAckPulse: target pulls SDA low while SCL is released
748 AddrAckPulse : begin
749 1/1 if (!scl_i) begin
Tests: T10 T44 T45
750 1/1 state_d = AddrAckHold;
Tests: T10 T44 T45
751 1/1 load_tcount = 1'b1;
Tests: T10 T44 T45
752 1/1 tcount_sel = tHoldData;
Tests: T10 T44 T45
753 end
MISSING_ELSE
754 end
755 // AddrAckHold: target pulls SDA low while SCL is pulled low
756 AddrAckHold : begin
757 1/1 if (tcount_q == 20'd1) begin
Tests: T10 T44 T45
758 // Stretch when requested by software or when there is insufficient
759 // space to hold the start / address format byte.
760 // If there is sufficient space, the format byte is written into the acquisition fifo.
761 // Don't stretch when we are unconditionally nacking the next byte
762 // anyways.
763 1/1 if (nack_transaction_q) begin
Tests: T10 T44 T45
764 // If the Target is set to NACK already, release SDA and wait
765 // for a Stop. This isn't an ideal response for SMBus reads, since
766 // 127 bytes of 0xff will just happen to have a correct PEC. It's
767 // best for software to ensure there is always space in the ACQ
768 // FIFO.
769 0/1 ==> state_d = WaitForStop;
770 1/1 end else if (stretch_addr) begin // !nack_transaction_q
Tests: T10 T44 T45
771 // Stretching because there is insufficient space to hold the
772 // start / address format byte.
773 // We should only reach here with !nack_addr_after_timeout_i, since
774 // we had enough space for nack_addr_after_timeout_i already,
775 // before issuing the ACK.
776 1/1 state_d = StretchAddr;
Tests: T10 T52 T53
777 1/1 end else if (rw_bit_q) begin
Tests: T10 T44 T45
778 // Not NACKing automatically, not stretching, and it's a read.
779 1/1 state_d = TransmitWait;
Tests: T10 T44 T45
780 end else begin
781 // Not NACKing automatically, not stretching, and it's a write.
782 1/1 state_d = AcquireByte;
Tests: T10 T44 T45
783 end
784 end
==> MISSING_ELSE
785 end
786 // TransmitWait: Evaluate whether there are entries to send first
787 TransmitWait : begin
788 1/1 if (stretch_tx) begin
Tests: T10 T44 T45
789 1/1 state_d = StretchTx;
Tests: T10 T45 T46
790 end else begin
791 1/1 state_d = TransmitSetup;
Tests: T10 T44 T45
792 end
793 end
794 // TransmitSetup: target shifts indexed bit onto SDA while SCL is low
795 TransmitSetup : begin
796 2/2 if (scl_i) state_d = TransmitPulse;
Tests: T10 T44 T45 | T10 T44 T45
MISSING_ELSE
797 end
798 // TransmitPulse: target shifts indexed bit onto SDA while SCL is released
799 TransmitPulse : begin
800 1/1 if (!scl_i) begin
Tests: T10 T44 T45
801 1/1 state_d = TransmitHold;
Tests: T10 T44 T45
802 1/1 load_tcount = 1'b1;
Tests: T10 T44 T45
803 1/1 tcount_sel = tHoldData;
Tests: T10 T44 T45
804 end
MISSING_ELSE
805 end
806 // TransmitHold: target shifts indexed bit onto SDA while SCL is pulled low
807 TransmitHold : begin
808 1/1 if (tcount_q == 20'd1) begin
Tests: T10 T44 T45
809 1/1 if (bit_ack) begin
Tests: T10 T44 T45
810 1/1 state_d = TransmitAck;
Tests: T10 T44 T45
811 end else begin
812 1/1 load_tcount = 1'b1;
Tests: T10 T44 T45
813 1/1 tcount_sel = tHoldData;
Tests: T10 T44 T45
814 1/1 state_d = TransmitSetup;
Tests: T10 T44 T45
815 end
816 end
==> MISSING_ELSE
817 end
818 // Wait for clock to become positive.
819 TransmitAck : begin
820 1/1 if (scl_i) begin
Tests: T10 T44 T45
821 1/1 state_d = TransmitAckPulse;
Tests: T10 T44 T45
822 end
MISSING_ELSE
823 end
824 // TransmitAckPulse: target waits for host to ACK transmission
825 // If a nak is received, that means a stop is incoming.
826 TransmitAckPulse : begin
827 1/1 if (!scl_i) begin
Tests: T10 T44 T45
828 // If host acknowledged, that means we must continue
829 1/1 if (host_ack) begin
Tests: T10 T44 T45
830 1/1 state_d = TransmitWait;
Tests: T10 T44 T45
831 end else begin
832 // If host nak'd then the transaction is about to terminate, go to a wait state
833 1/1 state_d = WaitForStop;
Tests: T44 T45 T46
834 end
835 end
MISSING_ELSE
836 end
837 // An inert state just waiting for host to issue a stop
838 // Cannot cycle back to idle directly as other events depend on the system being
839 // non-idle.
840 WaitForStop : begin
841 1/1 state_d = WaitForStop;
Tests: T44 T45 T46
842 end
843 // AcquireByte: target acquires a byte
844 AcquireByte : begin
845 1/1 if (bit_ack) begin
Tests: T10 T44 T45
846 1/1 state_d = AcquireAckWait;
Tests: T10 T44 T45
847 1/1 load_tcount = 1'b1;
Tests: T10 T44 T45
848 1/1 tcount_sel = tHoldData;
Tests: T10 T44 T45
849 end
MISSING_ELSE
850 end
851 // AcquireAckWait: pause for hold time before acknowledging
852 AcquireAckWait : begin
853 1/1 if (scl_i) begin
Tests: T10 T44 T45
854 // The controller is going too fast. Abandon the transaction.
855 0/1 ==> state_d = WaitForStop;
856 1/1 end else if (tcount_q == 20'd1) begin
Tests: T10 T44 T45
857 1/1 if (nack_transaction_q) begin
Tests: T10 T44 T45
858 0/1 ==> state_d = WaitForStop;
859 1/1 end else if (stretch_rx) begin
Tests: T10 T44 T45
860 // If there is no space for the current entry, stretch clocks and
861 // wait for software to make space. Also stretch if ACK Control
862 // Mode is enabled and the auto_ack_cnt is exhausted.
863 1/1 state_d = StretchAcqFull;
Tests: T10 T46 T47
864 end else begin
865 1/1 state_d = AcquireAckSetup;
Tests: T10 T44 T45
866 end
867 end
==> MISSING_ELSE
868 end
869 // AcquireAckSetup: target pulls SDA low while SCL is low
870 AcquireAckSetup : begin
871 2/2 if (scl_i) state_d = AcquireAckPulse;
Tests: T10 T44 T45 | T10 T44 T45
MISSING_ELSE
872 end
873 // AcquireAckPulse: target pulls SDA low while SCL is released
874 AcquireAckPulse : begin
875 1/1 if (!scl_i) begin
Tests: T10 T44 T45
876 1/1 state_d = AcquireAckHold;
Tests: T10 T44 T45
877 1/1 load_tcount = 1'b1;
Tests: T10 T44 T45
878 1/1 tcount_sel = tHoldData;
Tests: T10 T44 T45
879 end
MISSING_ELSE
880 end
881 // AcquireAckHold: target pulls SDA low while SCL is pulled low
882 AcquireAckHold : begin
883 1/1 if (tcount_q == 20'd1) begin
Tests: T10 T44 T45
884 1/1 state_d = AcquireByte;
Tests: T10 T44 T45
885 end
==> MISSING_ELSE
886 end
887 // StretchAddrAck: The address phase can not yet be completed, stretch
888 // clock and wait.
889 StretchAddrAck : begin
890 // When there is space in the FIFO go to the next state.
891 // If we hit our nack timeout, we must nack the full transaction.
892 1/1 if (nack_timeout) begin
Tests: T49 T50 T51
893 1/1 state_d = WaitForStop;
Tests: T49 T50 T51
894 1/1 end else if (!stretch_addr) begin
Tests: T49 T50 T51
895 0/1 ==> state_d = StretchAddrAckSetup;
896 0/1 ==> load_tcount = 1'b1;
897 0/1 ==> tcount_sel = tSetupData;
898 end
MISSING_ELSE
899 end
900 // StretchAddrAckSetup: target pulls SDA low while pulling SCL low for
901 // setup time. This is to prepare the setup time after a stretch.
902 StretchAddrAckSetup : begin
903 0/1 ==> if (tcount_q == 20'd1) begin
904 0/1 ==> state_d = AddrAckSetup;
905 end
==> MISSING_ELSE
906 end
907 // StretchAddr: The address phase can not yet be completed, stretch
908 // clock and wait.
909 StretchAddr : begin
910 // When there is space in the FIFO go to the next state.
911 // If we hit our nack timeout, we must nack the full transaction.
912 1/1 if (nack_timeout) begin
Tests: T10 T52 T53
913 1/1 state_d = WaitForStop;
Tests: T54 T55
914 1/1 end else if (!stretch_addr) begin
Tests: T10 T52 T53
915 // When transmitting after an address stretch, we need to assume
916 // that it looks like a Tx stretch. This is because if we try
917 // to follow the normal path, the logic will release the clock
918 // too early relative to driving the data. This will cause a
919 // setup violation. This is the same case to needing StretchTxSetup.
920 1/1 state_d = rw_bit_q ? StretchTx : AcquireByte;
Tests: T52 T56 T57
921 end
MISSING_ELSE
922 end
923 // StretchTx: target stretches the clock when tx conditions are not satisfied.
924 StretchTx : begin
925 // When in stretch state, always notify software that help is required.
926 1/1 event_tx_stretch_o = 1'b1;
Tests: T10 T45 T46
927 1/1 if (nack_timeout) begin
Tests: T10 T45 T46
928 1/1 state_d = WaitForStop;
Tests: T60 T61 T62
929 1/1 end else if (!stretch_tx) begin
Tests: T10 T45 T46
930 // When data becomes available, we must first drive it onto the line
931 // for at least the "setup" period. If we do not, once the clock is released, the
932 // pull-up in the system will likely immediately trigger a rising clock
933 // edge (since the stretch likely pushed us way beyond the original intended
934 // rise). If we do not artificially create the setup period here, it will
935 // likely create a timing violation.
936 1/1 state_d = StretchTxSetup;
Tests: T10 T45 T46
937 1/1 load_tcount = 1'b1;
Tests: T10 T45 T46
938 1/1 tcount_sel = tSetupData;
Tests: T10 T45 T46
939
940 // When leaving stretch state, de-assert software notification
941 1/1 event_tx_stretch_o = 1'b0;
Tests: T10 T45 T46
942 end
MISSING_ELSE
943 end
944 // StretchTxSetup: Wait for tSetupData before going to transmit
945 StretchTxSetup : begin
946 1/1 if (tcount_q == 20'd1) begin
Tests: T10 T45 T46
947 1/1 state_d = TransmitSetup;
Tests: T45 T46 T69
948 end
MISSING_ELSE
949 end
950 // StretchAcqFull: target stretches the clock when acq_fifo is full
951 // When space becomes available, move on to prepare to ACK. If we hit
952 // our NACK timeout we must continue and unconditionally NACK the next
953 // one.
954 // If ACK Control Mode is enabled, also stretch if the Auto ACK counter
955 // is exhausted. If the conditions for an ACK Control stretch are
956 // present, NACK the transaction if directed by SW.
957 StretchAcqFull : begin
958 1/1 if (nack_timeout || (sw_nack_i && !can_auto_ack)) begin
Tests: T10 T46 T47
959 1/1 state_d = WaitForStop;
Tests: T63 T64 T65
960 1/1 end else if (~stretch_rx) begin
Tests: T10 T46 T47
961 1/1 state_d = StretchAcqSetup;
Tests: T46 T47 T48
962 1/1 load_tcount = 1'b1;
Tests: T46 T47 T48
963 1/1 tcount_sel = tSetupData;
Tests: T46 T47 T48
964 end
MISSING_ELSE
965 end
966 // StretchAcqSetup: Drive the ACK and wait for tSetupData before
967 // releasing SCL
968 StretchAcqSetup : begin
969 1/1 if (tcount_q == 20'd1) begin
Tests: T46 T47 T48
970 1/1 state_d = AcquireAckSetup;
Tests: T46 T47 T48
971 end
MISSING_ELSE
972 end
973 // default
974 default : begin
975 state_d = Idle;
976 load_tcount = 1'b0;
977 tcount_sel = tNoDelay;
978 input_byte_clr = 1'b0;
979 event_tx_stretch_o = 1'b0;
980 end
981 endcase // unique case (state_q)
982
983 // When a start is detected, always go to the acquire start state.
984 // Differences in repeated start / start handling are done in the
985 // other FSM.
986 1/1 if (!target_idle && !target_enable_i) begin
Tests: T1 T2 T3
987 // If the target function is currently not idle but target_enable is suddenly dropped,
988 // (maybe because the host locked up and we want to cycle back to an initial state),
989 // transition immediately.
990 // The same treatment is not given to the host mode because it already attempts to
991 // gracefully terminate. If the host cannot gracefully terminate for whatever reason,
992 // (the other side is holding SCL low), we may need to forcefully reset the module.
993 // ICEBOX(#18004): It may be worth having a force stop condition to force the host back to
994 // Idle in case graceful termination is not possible.
995 0/1 ==> state_d = Idle;
996 1/1 end else if (target_enable_i && start_detect_i) begin
Tests: T1 T2 T3
997 1/1 state_d = AcquireStart;
Tests: T10 T44 T45
998 1/1 end else if (stop_detect_i || bus_timeout_i) begin
Tests: T1 T2 T3
999 1/1 state_d = Idle;
Tests: T2 T4 T5
1000 1/1 end else if (arbitration_lost_i) begin
Tests: T1 T2 T3
1001 0/1 ==> state_d = WaitForStop;
1002 end
MISSING_ELSE
1003 end
1004
1005 // Synchronous state transition
1006 always_ff @ (posedge clk_i or negedge rst_ni) begin : state_transition
1007 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
1008 1/1 state_q <= Idle;
Tests: T1 T2 T3
1009 end else begin
1010 1/1 state_q <= state_d;
Tests: T1 T2 T3
1011 end
1012 end
1013
1014 // Saved sda output used in certain states.
1015 always_ff @(posedge clk_i or negedge rst_ni) begin
1016 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
1017 1/1 sda_q <= 1'b1;
Tests: T1 T2 T3
1018 end else begin
1019 1/1 sda_q <= sda_d;
Tests: T1 T2 T3
1020 end
1021 end
1022
1023 1/1 assign scl_o = scl_d;
Tests: T1 T2 T3
1024 1/1 assign sda_o = sda_d;
Tests: T1 T2 T3
1025
1026 // Fed out for interrupt purposes
1027 1/1 assign acq_fifo_full_o = !acq_fifo_plenty_space;
Tests: T1 T2 T3