Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
85.19	85.19	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	85.19	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.19	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	8	19	70.37

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	8	19	70.37	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

177005

1

T3

97

T4

6

T5

204

ack

266

1

T11

8

T12

5

T13

4

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	659	1			T5	2		T8	1		T14	1
high	37306	1			T3	17		T5	70		T7	2
med	67274	1			T3	40		T4	4		T5	66
sml	71324	1			T3	40		T4	2		T5	64
all_zero	708	1			T5	2		T8	1		T40	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88670

1

T3

53

T4

4

T5

111

auto[1]

88601

1

T3

44

T4

2

T5

93

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120795

1

T3

68

T4

4

T5

139

auto[1]

56476

1

T3

29

T4

2

T5

65

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

173453

1

T3

97

T4

6

T5

204

auto[1]

3818

1

T8

10

T9

26

T11

7

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170485

1

T3

96

T4

4

T5

189

auto[1]

6786

1

T3

1

T4

2

T5

15

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171387

1

T3

96

T4

6

T5

189

auto[1]

5884

1

T3

1

T5

15

T7

1

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88670

1

T3

53

T4

4

T5

111

auto[1]

88601

1

T3

44

T4

2

T5

93

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120795

1

T3

68

T4

4

T5

139

auto[1]

56476

1

T3

29

T4

2

T5

65

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

173453

1

T3

97

T4

6

T5

204

auto[1]

3818

1

T8

10

T9

26

T11

7

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170485

1

T3

96

T4

4

T5

189

auto[1]

6786

1

T3

1

T4

2

T5

15

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171387

1

T3

96

T4

6

T5

189

auto[1]

5884

1

T3

1

T5

15

T7

1

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	8	19	70.37	6
Automatically Generated Cross Bins	15	6	9	60.00	6
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Element holes

cp_fbyte	start	stop	read	rcont	nakok	cp_ack	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[ack]	--	--	2
[all_zero]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[ack]	--	--	2

Uncovered bins

cp_fbyte	start	stop	read	rcont	nakok	cp_ack	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[ack]	0	1	1
[all_zero]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[ack]	0	1	1

Covered bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

5

1

T247

1

T248

1

T249

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T250

1

T251

1

T252

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T253

1

T254

1

T255

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

16

1

T13

1

T253

1

T250

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

9

1

T256

1

T255

1

T257

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

6

1

T37

1

T258

1

T256

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

13

1

T12

1

T253

2

T259

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T250

1

T260

1

T261

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

8

1

T12

1

T258

1

T256

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	54606	1			T3	38		T5	61		T8	42
write_address_byte	6786	1			T3	1		T4	2		T5	15
read_with_ack	901	1			T9	16		T11	4		T28	11
read_with_nack	2917	1			T8	10		T9	10		T11	3
stop_byte	5884	1			T3	1		T5	15		T7	1
write_address_byte_nak	6694	1			T3	1		T4	2		T5	15
data_byte_nack	177005	1			T3	97		T4	6		T5	204
stop_byte_nack	5844	1			T3	1		T5	15		T7	1
nakok_byte_nack	88471	1			T3	44		T4	2		T5	93
nakok_addr_byte_nack	3326	1			T5	7		T8	14		T9	5