Group : tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg
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Group : tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
90.43 90.43 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_protocol_cov_cg 90.43 1 100 1 64 64



Group Instance : i2c_protocol_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
90.43 1 100 1 64 64



Summary for Group Instance i2c_protocol_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 47 6 41 87.23
Crosses 68 5 63 92.65


Variables for Group Instance i2c_protocol_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
RStart_before_read_data_ACK_cp 1 0 1 100.00 100 1 1 0
RStart_during_address_Ack_cp 1 0 1 100.00 100 1 1 0
RStart_during_address_transmission_cp 1 1 0 0.00 100 1 1 0
RStart_during_read_data_cp 1 0 1 100.00 100 1 1 0
RStart_during_rw_bit_cp 1 1 0 0.00 100 1 1 0
RStart_during_write_data_cp 1 0 1 100.00 100 1 1 0
Read_data_ack_before_stop_cp 1 1 0 0.00 100 1 1 0
Rstart_after_Address_Ack_cp 1 0 1 100.00 100 1 1 0
Rstart_after_Address_Nack_cp 1 0 1 100.00 100 1 1 0
Start_followed_by_Rstart_cp 1 0 1 100.00 100 1 1 2
Stop_after_read_data_Nack_cp 1 0 1 100.00 100 1 1 0
Stop_after_read_data_ack_cp 1 1 0 0.00 100 1 1 0
Stop_after_write_data_Nack_cp 1 0 1 100.00 100 1 1 0
Stop_after_write_data_ack_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_addr_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_data_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_read_cp 1 1 0 0.00 100 1 1 0
Stop_without_ACK_after_write_cp 1 1 0 0.00 100 1 1 0
bus_state_cp 17 0 17 100.00 100 1 1 0
ip_mode_cp 2 0 2 100.00 100 1 1 0
num_rd_bytes_cp 5 0 5 100.00 100 1 1 0
num_wr_bytes_cp 5 0 5 100.00 100 1 1 0


Crosses for Group Instance i2c_protocol_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
bus_state_x_ip_mode_cp 34 1 33 97.06 100 1 1 0
num_rd_bytes_x_ip_mode_cp 10 0 10 100.00 100 1 1 0
num_wr_bytes_x_ip_mode_cp 10 0 10 100.00 100 1 1 0
Stop_after_write_data_ack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Stop_after_read_data_ack_x_ip_mode_cp 2 2 0 0.00 100 1 1 0
Stop_after_write_data_Nack_x_ip_mode_cp 2 1 1 50.00 100 1 1 0
Stop_after_read_data_Nack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Rstart_after_Address_Ack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Rstart_after_Address_Nack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Start_followed_by_Rstart_cp_x_ip_mode_cp 2 1 1 50.00 100 1 1 0


Summary for Variable RStart_before_read_data_ACK_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_before_read_data_ACK_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_before_read_data_ACK_Nack 12256 1 T6 2 T10 26 T42 44


Summary for Variable RStart_during_address_Ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_address_Ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Start_during_address_Acknowledge 8 1 T6 4 T51 4


Summary for Variable RStart_during_address_transmission_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for RStart_during_address_transmission_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Start_during_address_transmission 0 1 1


Summary for Variable RStart_during_read_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_read_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Start_during_read_data 24 1 T6 12 T51 12


Summary for Variable RStart_during_rw_bit_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for RStart_during_rw_bit_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Start_during_rw_bit 0 1 1


Summary for Variable RStart_during_write_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_write_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_during_write_data 21575 1 T6 10 T10 34 T47 21


Summary for Variable Read_data_ack_before_stop_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Read_data_ack_before_stop_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Read_data_ack_before_stop 0 1 1


Summary for Variable Rstart_after_Address_Ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Rstart_after_Address_Ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Ack 27 1 T6 10 T51 10 T18 1


Summary for Variable Rstart_after_Address_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Rstart_after_Address_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Nack 67 1 T6 4 T51 4 T12 2


Summary for Variable Start_followed_by_Rstart_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for Start_followed_by_Rstart_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
unused 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[1] 4 1 T262 2 T263 2


Summary for Variable Stop_after_read_data_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_read_data_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_Nack 10806 1 T4 3 T8 11 T9 36


Summary for Variable Stop_after_read_data_ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_after_read_data_ack_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_after_read_data_ack 0 1 1


Summary for Variable Stop_after_write_data_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_write_data_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_Nack 61 1 T12 1 T37 4 T258 1


Summary for Variable Stop_after_write_data_ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_write_data_ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_ack 9262 1 T5 14 T6 37 T8 12


Summary for Variable Stop_without_ACK_after_addr_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_without_ACK_after_addr_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
Stop_without_ACK_after_addr 1 1 T264 1


Summary for Variable Stop_without_ACK_after_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_without_ACK_after_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_without_ACK_after_data 6157 1 T6 37 T10 4 T47 20


Summary for Variable Stop_without_ACK_after_read_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_without_ACK_after_read_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_without_ACK_after_read 0 1 1


Summary for Variable Stop_without_ACK_after_write_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_without_ACK_after_write_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_without_ACK_after_write 0 1 1


Summary for Variable bus_state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 17 0 17 100.00


User Defined Bins for bus_state_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
idle 285508 1 T1 1 T2 8 T3 1
stop 21132 1 T1 2 T4 7 T5 14
write_data_nack 31099 1 T6 6 T11 67 T63 4
write_data_ack 1494399 1 T3 337 T4 14 T5 652
read_data_nack 87648 1 T4 12 T6 2 T8 48
read_data_ack 1150320 1 T4 310 T6 15 T8 142
write_data 10241932 1 T3 2019 T4 91 T5 3991
read_data 8052155 1 T4 2206 T6 185 T8 1296
write_addr_nack 26692 1 T6 4 T11 266 T51 4
write_addr_ack 109074 1 T3 3 T4 12 T5 52
read_addr_nack 80229 1 T11 756 T12 1386 T13 406
read_addr_ack 83533 1 T4 16 T6 55 T8 40
write 130250 1 T3 4 T4 20 T5 60
read 72180 1 T4 18 T6 48 T8 36
addr 1182861 1 T3 17 T4 206 T5 268
rstart 89282 1 T4 3 T6 102 T10 120
start 56887 1 T1 3 T3 3 T4 31


Summary for Variable ip_mode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for ip_mode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device 12752826 1 T6 34367 T10 19364 T42 6040
host 10442355 1 T1 6 T2 8 T3 2384


Summary for Variable num_rd_bytes_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for num_rd_bytes_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sixtyfour 35282 1 T9 54 T14 26 T38 52
high 1269104 1 T9 1271 T10 486 T42 300
mid 1950912 1 T4 782 T9 5673 T10 1686
low 4565121 1 T4 1583 T8 906 T9 13379
one 494555 1 T4 84 T6 21 T8 281


Summary for Variable num_wr_bytes_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for num_wr_bytes_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sixtyfour 43710 1 T3 24 T6 116 T43 28
high 1343286 1 T3 492 T6 2308 T43 578
mid 2080328 1 T3 538 T5 994 T6 2508
low 5241246 1 T3 488 T4 56 T5 3007
one 644055 1 T3 26 T4 26 T5 324


Summary for Cross bus_state_x_ip_mode_cp

Samples crossed: bus_state_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 34 1 33 97.06 1


Automatically Generated Cross Bins for bus_state_x_ip_mode_cp

Uncovered bins
bus_state_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[read_addr_nack] [device] 0 1 1


Covered bins
bus_state_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
idle device 279854 1 T6 1 T10 1 T42 1
idle host 5654 1 T1 1 T2 8 T3 1
stop device 12080 1 T6 39 T10 19 T47 39
stop host 9052 1 T1 2 T4 7 T5 14
write_data_nack device 392 1 T6 6 T63 4 T64 4
write_data_nack host 30707 1 T11 67 T12 1955 T13 73
write_data_ack device 861262 1 T6 4320 T10 792 T43 913
write_data_ack host 633137 1 T3 337 T4 14 T5 652
read_data_nack device 60416 1 T6 2 T10 138 T42 136
read_data_nack host 27232 1 T4 12 T8 48 T9 148
read_data_ack device 472514 1 T6 15 T10 1330 T42 530
read_data_ack host 677806 1 T4 310 T8 142 T9 2726
write_data device 6443041 1 T6 27490 T10 5650 T43 6407
write_data host 3798891 1 T3 2019 T4 91 T5 3991
read_data device 3173502 1 T6 185 T10 8873 T42 4047
read_data host 4878653 1 T4 2206 T8 1296 T9 19924
write_addr_nack device 28 1 T6 4 T51 4 T48 4
write_addr_nack host 26664 1 T11 266 T12 782 T13 843
write_addr_ack device 94706 1 T6 210 T10 133 T43 3
write_addr_ack host 14368 1 T3 3 T4 12 T5 52
read_addr_nack host 80229 1 T11 756 T12 1386 T13 406
read_addr_ack device 63607 1 T6 55 T10 136 T42 156
read_addr_ack host 19926 1 T4 16 T8 40 T9 129
write device 113155 1 T6 232 T10 156 T43 4
write host 17095 1 T3 4 T4 20 T5 60
read device 54603 1 T6 48 T10 123 T42 135
read host 17577 1 T4 18 T8 36 T9 111
addr device 1003593 1 T6 1538 T10 1853 T42 945
addr host 179268 1 T3 17 T4 206 T5 268
rstart device 87424 1 T6 102 T10 120 T42 88
rstart host 1858 1 T4 3 T11 2 T14 3
start device 32649 1 T6 120 T10 40 T42 2
start host 24238 1 T1 3 T3 3 T4 31


Summary for Cross num_rd_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_rd_bytes_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for num_rd_bytes_x_ip_mode_cp

Bins
ip_mode_cpnum_rd_bytes_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device sixtyfour 1601 1 T265 30 T266 72 T90 22
device high 84759 1 T10 486 T42 300 T44 263
device mid 352598 1 T10 1686 T42 588 T44 530
device low 2474798 1 T10 6561 T42 2485 T47 5402
device one 346385 1 T6 21 T10 764 T42 433
host sixtyfour 33681 1 T9 54 T14 26 T38 52
host high 1184345 1 T9 1271 T14 554 T38 7347
host mid 1598314 1 T4 782 T9 5673 T14 604
host low 2090323 1 T4 1583 T8 906 T9 13379
host one 148170 1 T4 84 T8 281 T9 980


Summary for Cross num_wr_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_wr_bytes_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for num_wr_bytes_x_ip_mode_cp

Bins
ip_mode_cpnum_wr_bytes_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device sixtyfour 12063 1 T6 116 T43 28 T69 28
device high 348900 1 T6 2308 T43 578 T69 560
device mid 918011 1 T6 2508 T10 291 T43 632
device low 3961740 1 T6 2284 T10 4411 T43 568
device one 541148 1 T6 252 T10 789 T43 26
host sixtyfour 31647 1 T3 24 T40 26 T38 65
host high 994386 1 T3 492 T40 476 T38 6382
host mid 1162317 1 T3 538 T5 994 T8 531
host low 1279506 1 T3 488 T4 56 T5 3007
host one 102907 1 T3 26 T4 26 T5 324


Summary for Cross Stop_after_write_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Stop_after_write_data_ack_x_ip_mode_cp

Bins
Stop_after_write_data_ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_ack device 6133 1 T6 37 T10 4 T47 20
Stop_after_write_data_ack host 3129 1 T5 14 T8 12 T41 13


Summary for Cross Stop_after_read_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 2 0 0.00 2


Automatically Generated Cross Bins for Stop_after_read_data_ack_x_ip_mode_cp

Uncovered bins
Stop_after_read_data_ack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* * -- -- 2


Summary for Cross Stop_after_write_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Stop_after_write_data_Nack_x_ip_mode_cp

Element holes
Stop_after_write_data_Nack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [device] 0 1 1


Covered bins
Stop_after_write_data_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_Nack host 61 1 T12 1 T37 4 T258 1


Summary for Cross Stop_after_read_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Stop_after_read_data_Nack_x_ip_mode_cp

Bins
Stop_after_read_data_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_Nack device 5534 1 T10 15 T47 19 T44 5
Stop_after_read_data_Nack host 5272 1 T4 3 T8 11 T9 36


Summary for Cross Rstart_after_Address_Ack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Rstart_after_Address_Ack_x_ip_mode_cp

Bins
Rstart_after_Address_Ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Ack device 20 1 T6 10 T51 10 - -
Rstart_after_Address_Ack host 7 1 T18 1 T267 1 T268 1


Summary for Cross Rstart_after_Address_Nack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Rstart_after_Address_Nack_x_ip_mode_cp

Bins
Rstart_after_Address_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Nack device 8 1 T6 4 T51 4 - -
Rstart_after_Address_Nack host 59 1 T12 2 T13 1 T37 3


Summary for Cross Start_followed_by_Rstart_cp_x_ip_mode_cp

Samples crossed: Start_followed_by_Rstart_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Start_followed_by_Rstart_cp_x_ip_mode_cp

Element holes
Start_followed_by_Rstart_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [device] 0 1 1


Excluded/Illegal bins
Start_followed_by_Rstart_cpip_mode_cpCOUNTSTATUS
[auto[0]] [device , host] -- Excluded (2 bins)


Covered bins
Start_followed_by_Rstart_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[1] host 4 1 T262 2 T263 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%