Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27882535	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7454386

1

T1

17

T2

48

T3

1065

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34538350	1			T1	17		T2	120		T3	2850
values[0x0]	398509	1			T1	6		T2	56		T3	61
values[0x1]	400062	1			T1	12		T2	59		T3	50

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19472938	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15863983

1

T1

18

T2

108

T3

1541

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	130448	1			T1	1		T2	1		T4	1
valid_sources[0x01]	130986	1			T2	1		T3	5		T5	23
valid_sources[0x02]	133916	1			T3	16		T4	1		T5	30
valid_sources[0x03]	141317	1			T1	3		T2	3		T3	16
valid_sources[0x04]	144869	1			T3	13		T5	11		T7	33
valid_sources[0x05]	130001	1			T3	9		T5	18		T7	27
valid_sources[0x06]	139068	1			T2	3		T3	1		T4	1
valid_sources[0x07]	129294	1			T3	12		T5	18		T7	58
valid_sources[0x08]	133665	1			T1	5		T2	2		T3	7
valid_sources[0x09]	128171	1			T2	1		T3	9		T5	9
valid_sources[0x0a]	175542	1			T2	3		T3	1		T4	1
valid_sources[0x0b]	131622	1			T1	3		T2	2		T3	5
valid_sources[0x0c]	139487	1			T3	6		T5	12		T7	58
valid_sources[0x0d]	135657	1			T2	1		T3	37		T4	1
valid_sources[0x0e]	156040	1			T3	12		T4	1		T5	14
valid_sources[0x0f]	139999	1			T2	2		T3	19		T4	1
valid_sources[0x10]	145453	1			T2	2		T3	6		T4	1
valid_sources[0x11]	126944	1			T5	12		T7	92		T8	67
valid_sources[0x12]	142700	1			T3	9		T5	9		T6	2
valid_sources[0x13]	163899	1			T3	26		T5	12		T7	90
valid_sources[0x14]	135196	1			T3	7		T4	1		T5	14
valid_sources[0x15]	137940	1			T2	2		T3	1		T5	4
valid_sources[0x16]	151225	1			T2	1		T3	14		T5	7
valid_sources[0x17]	139259	1			T2	1		T3	23		T4	1
valid_sources[0x18]	215399	1			T2	1		T3	11		T5	22
valid_sources[0x19]	141560	1			T2	2		T3	4		T4	1
valid_sources[0x1a]	164360	1			T2	1		T3	11		T5	16
valid_sources[0x1b]	128296	1			T2	2		T3	37		T4	1
valid_sources[0x1c]	139628	1			T2	1		T3	11		T5	14
valid_sources[0x1d]	145717	1			T3	38		T5	29		T7	65
valid_sources[0x1e]	120458	1			T2	2		T3	1		T5	16
valid_sources[0x1f]	140411	1			T3	2		T5	8		T7	123
valid_sources[0x20]	150854	1			T2	1		T3	2		T5	30
valid_sources[0x21]	137236	1			T2	1		T3	15		T4	34
valid_sources[0x22]	145973	1			T3	4		T5	16		T7	78
valid_sources[0x23]	142635	1			T2	1		T3	7		T4	1
valid_sources[0x24]	138530	1			T2	2		T3	19		T4	55
valid_sources[0x25]	136035	1			T1	1		T3	4		T4	1
valid_sources[0x26]	137207	1			T2	1		T3	4		T5	20
valid_sources[0x27]	124156	1			T3	6		T4	2		T5	10
valid_sources[0x28]	136493	1			T1	2		T3	18		T5	7
valid_sources[0x29]	207756	1			T3	5		T5	18		T7	62
valid_sources[0x2a]	128374	1			T3	5		T5	18		T6	1
valid_sources[0x2b]	129601	1			T2	1		T3	21		T4	1
valid_sources[0x2c]	140886	1			T3	14		T4	1		T5	15
valid_sources[0x2d]	150734	1			T3	30		T5	17		T7	75
valid_sources[0x2e]	125586	1			T3	4		T4	1		T5	13
valid_sources[0x2f]	125264	1			T2	1		T3	16		T4	2
valid_sources[0x30]	165015	1			T2	1		T4	1		T5	27
valid_sources[0x31]	130494	1			T2	1		T3	40		T5	10
valid_sources[0x32]	135069	1			T2	2		T3	9		T5	3
valid_sources[0x33]	145626	1			T2	1		T3	37		T4	55
valid_sources[0x34]	134179	1			T2	1		T3	11		T4	2
valid_sources[0x35]	142515	1			T2	1		T3	13		T5	9
valid_sources[0x36]	134543	1			T3	18		T5	9		T7	90
valid_sources[0x37]	133992	1			T3	15		T4	1		T5	18
valid_sources[0x38]	166004	1			T3	13		T5	8		T7	124
valid_sources[0x39]	136861	1			T3	21		T4	1		T5	5
valid_sources[0x3a]	133263	1			T3	15		T4	1		T5	9
valid_sources[0x3b]	131793	1			T2	2		T3	19		T4	1
valid_sources[0x3c]	133367	1			T2	2		T3	7		T4	11
valid_sources[0x3d]	126953	1			T2	1		T3	21		T4	1
valid_sources[0x3e]	132274	1			T2	3		T3	18		T4	1
valid_sources[0x3f]	137585	1			T2	1		T4	43		T5	20
valid_sources[0x40]	144832	1			T2	4		T3	18		T4	2
valid_sources[0x41]	126263	1			T2	2		T3	13		T5	13
valid_sources[0x42]	139692	1			T4	1		T5	18		T7	169
valid_sources[0x43]	130487	1			T2	1		T3	15		T5	19
valid_sources[0x44]	127195	1			T2	1		T3	10		T4	1
valid_sources[0x45]	139586	1			T1	1		T3	11		T5	14
valid_sources[0x46]	131421	1			T3	3		T5	18		T7	133
valid_sources[0x47]	136040	1			T2	3		T3	6		T5	15
valid_sources[0x48]	131485	1			T2	5		T3	7		T4	1
valid_sources[0x49]	142829	1			T2	2		T3	2		T4	1
valid_sources[0x4a]	125295	1			T4	1		T5	32		T6	6
valid_sources[0x4b]	128216	1			T2	1		T3	7		T4	1
valid_sources[0x4c]	131868	1			T2	1		T3	1		T5	8
valid_sources[0x4d]	136588	1			T3	27		T4	1		T5	19
valid_sources[0x4e]	138701	1			T2	2		T3	24		T5	31
valid_sources[0x4f]	128656	1			T2	2		T3	13		T4	1
valid_sources[0x50]	124678	1			T2	1		T3	17		T4	1
valid_sources[0x51]	141581	1			T2	3		T3	27		T5	13
valid_sources[0x52]	135987	1			T3	2		T5	17		T6	8
valid_sources[0x53]	128650	1			T2	1		T3	26		T5	11
valid_sources[0x54]	122813	1			T2	1		T3	11		T4	1
valid_sources[0x55]	134597	1			T2	1		T3	12		T4	1
valid_sources[0x56]	135961	1			T1	1		T2	1		T3	12
valid_sources[0x57]	136696	1			T2	1		T3	27		T4	1
valid_sources[0x58]	129559	1			T3	17		T4	1		T5	11
valid_sources[0x59]	123214	1			T5	21		T7	104		T8	133
valid_sources[0x5a]	161521	1			T3	4		T4	2		T5	19
valid_sources[0x5b]	151771	1			T2	1		T3	5		T4	1
valid_sources[0x5c]	148071	1			T5	17		T7	87		T8	80
valid_sources[0x5d]	141571	1			T2	1		T3	5		T5	15
valid_sources[0x5e]	142117	1			T3	10		T5	25		T7	52
valid_sources[0x5f]	146751	1			T2	1		T4	1		T5	9
valid_sources[0x60]	129582	1			T2	1		T3	5		T5	19
valid_sources[0x61]	132155	1			T2	1		T3	16		T5	12
valid_sources[0x62]	140511	1			T2	1		T3	7		T5	2
valid_sources[0x63]	144115	1			T2	1		T3	13		T5	7
valid_sources[0x64]	135882	1			T3	22		T5	4		T7	165
valid_sources[0x65]	138830	1			T3	30		T4	1		T5	18
valid_sources[0x66]	145326	1			T2	2		T3	18		T4	1
valid_sources[0x67]	128735	1			T2	1		T3	9		T4	1
valid_sources[0x68]	126925	1			T2	1		T3	13		T5	18
valid_sources[0x69]	146482	1			T3	21		T4	1		T5	11
valid_sources[0x6a]	132307	1			T3	8		T5	6		T6	13
valid_sources[0x6b]	145160	1			T2	1		T3	20		T5	15
valid_sources[0x6c]	152849	1			T2	1		T3	11		T4	2
valid_sources[0x6d]	144297	1			T2	2		T4	45		T5	12
valid_sources[0x6e]	136244	1			T2	1		T3	29		T4	1
valid_sources[0x6f]	145364	1			T2	1		T3	9		T4	1
valid_sources[0x70]	130765	1			T3	7		T5	19		T7	134
valid_sources[0x71]	137849	1			T3	14		T4	1		T5	10
valid_sources[0x72]	129905	1			T2	1		T3	34		T4	40
valid_sources[0x73]	139480	1			T2	3		T3	12		T5	17
valid_sources[0x74]	136601	1			T3	13		T5	16		T7	129
valid_sources[0x75]	129789	1			T3	3		T4	1		T5	17
valid_sources[0x76]	136356	1			T2	4		T3	9		T4	1
valid_sources[0x77]	150786	1			T3	25		T5	17		T6	8
valid_sources[0x78]	165758	1			T3	10		T4	1		T5	2
valid_sources[0x79]	130277	1			T3	3		T4	8		T5	10
valid_sources[0x7a]	126066	1			T2	2		T3	14		T5	10
valid_sources[0x7b]	145768	1			T2	2		T3	10		T5	16
valid_sources[0x7c]	135311	1			T3	15		T5	11		T6	7
valid_sources[0x7d]	129046	1			T3	12		T5	20		T7	68
valid_sources[0x7e]	139524	1			T1	4		T2	3		T3	13
valid_sources[0x7f]	140256	1			T2	1		T3	17		T4	1
valid_sources[0x80]	127209	1			T2	1		T3	4		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7100136

1

T1

10

T2

2

T3

1014

values[0x0]

all_enables

biggest_size

210390

1

T1

3

T2

34

T3

38

values[0x1]

all_enables

biggest_size

143860

1

T1

4

T2

12

T3

13