Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	381762084	0	0	0
ctrl_rd_A	381762084	2085	0	0
host_fifo_config_rd_A	381762084	3572	0	0
host_nack_handler_timeout_rd_A	381762084	1728	0	0
host_timeout_ctrl_rd_A	381762084	1515	0	0
intr_enable_rd_A	381762084	3376	0	0
ovrd_rd_A	381762084	1714	0	0
target_fifo_config_rd_A	381762084	1669	0	0
target_id_rd_A	381762084	1689	0	0
target_timeout_ctrl_rd_A	381762084	1720	0	0
timeout_ctrl_rd_A	381762084	1811	0	0
timing0_rd_A	381762084	1644	0	0
timing1_rd_A	381762084	1524	0	0
timing2_rd_A	381762084	1724	0	0
timing3_rd_A	381762084	1576	0	0
timing4_rd_A	381762084	1623	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381762084	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381762084	2085	0	0
T105	1530	29	0	0
T106	3938	7	0	0
T107	9516	95	0	0
T108	4921	30	0	0
T109	6264	128	0	0
T110	3774	25	0	0
T111	26240	208	0	0
T112	7798	118	0	0
T113	3092	22	0	0
T114	13385	37	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381762084	3572	0	0
T17	12167	0	0	0
T28	101152	0	0	0
T38	362176	163	0	0
T39	125374	0	0	0
T46	553039	0	0	0
T51	196157	0	0	0
T81	14323	0	0	0
T115	0	239	0	0
T116	0	270	0	0
T117	0	126	0	0
T118	0	130	0	0
T119	0	153	0	0
T120	0	165	0	0
T121	0	191	0	0
T122	0	222	0	0
T123	0	145	0	0
T124	16402	0	0	0
T125	56612	0	0	0
T126	77453	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381762084	1728	0	0
T105	1530	7	0	0
T106	3938	2	0	0
T107	9516	139	0	0
T108	4921	23	0	0
T109	6264	120	0	0
T110	3774	22	0	0
T111	26240	231	0	0
T112	7798	65	0	0
T113	3092	3	0	0
T114	13385	24	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381762084	1515	0	0
T106	3938	9	0	0
T107	9516	156	0	0
T108	4921	27	0	0
T109	6264	132	0	0
T110	3774	10	0	0
T111	26240	207	0	0
T112	7798	31	0	0
T113	3092	4	0	0
T114	13385	26	0	0
T127	1937	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381762084	3376	0	0
T29	6921	0	0	0
T35	145455	28	0	0
T105	0	37	0	0
T106	0	18	0	0
T107	0	121	0	0
T108	0	63	0	0
T109	0	130	0	0
T110	0	118	0	0
T120	0	16	0	0
T122	0	20	0	0
T128	0	18	0	0
T129	57855	0	0	0
T130	62585	0	0	0
T131	332523	0	0	0
T132	13569	0	0	0
T133	4454	0	0	0
T134	522575	0	0	0
T135	371834	0	0	0
T136	29357	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381762084	1714	0	0
T12	75694	0	0	0
T32	14915	0	0	0
T71	12986	0	0	0
T102	1105	26	0	0
T103	262357	0	0	0
T137	0	20	0	0
T138	0	37	0	0
T139	0	59	0	0
T140	0	38	0	0
T141	0	47	0	0
T142	0	46	0	0
T143	0	46	0	0
T144	0	46	0	0
T145	0	38	0	0
T146	27757	0	0	0
T147	52519	0	0	0
T148	17839	0	0	0
T149	95756	0	0	0
T150	6094	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381762084	1669	0	0
T105	1530	12	0	0
T106	3938	28	0	0
T107	9516	108	0	0
T108	4921	87	0	0
T109	6264	114	0	0
T110	3774	27	0	0
T111	26240	248	0	0
T112	7798	61	0	0
T113	3092	7	0	0
T114	13385	63	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381762084	1689	0	0
T105	1530	8	0	0
T106	3938	18	0	0
T107	9516	136	0	0
T108	4921	24	0	0
T109	6264	117	0	0
T110	3774	36	0	0
T111	26240	221	0	0
T112	7798	47	0	0
T113	3092	6	0	0
T114	13385	14	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381762084	1720	0	0
T105	1530	18	0	0
T106	3938	25	0	0
T107	9516	114	0	0
T108	4921	49	0	0
T109	6264	112	0	0
T110	3774	22	0	0
T111	26240	207	0	0
T112	7798	76	0	0
T113	3092	30	0	0
T114	13385	28	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381762084	1811	0	0
T105	1530	4	0	0
T106	3938	7	0	0
T107	9516	126	0	0
T108	4921	25	0	0
T109	6264	135	0	0
T110	3774	26	0	0
T111	26240	254	0	0
T112	7798	74	0	0
T113	3092	22	0	0
T114	13385	42	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381762084	1644	0	0
T106	3938	8	0	0
T107	9516	107	0	0
T108	4921	34	0	0
T109	6264	119	0	0
T110	3774	16	0	0
T111	26240	229	0	0
T112	7798	68	0	0
T113	3092	37	0	0
T114	13385	41	0	0
T151	1358	1	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381762084	1524	0	0
T105	1530	4	0	0
T106	3938	13	0	0
T107	9516	99	0	0
T108	4921	19	0	0
T109	6264	115	0	0
T110	3774	24	0	0
T111	26240	228	0	0
T112	7798	71	0	0
T113	3092	7	0	0
T114	13385	32	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381762084	1724	0	0
T105	1530	12	0	0
T106	3938	9	0	0
T107	9516	112	0	0
T108	4921	49	0	0
T109	6264	131	0	0
T110	3774	28	0	0
T111	26240	212	0	0
T112	7798	59	0	0
T113	3092	17	0	0
T114	13385	52	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381762084	1576	0	0
T105	1530	6	0	0
T106	3938	16	0	0
T107	9516	113	0	0
T108	4921	48	0	0
T109	6264	152	0	0
T110	3774	27	0	0
T111	26240	231	0	0
T112	7798	82	0	0
T113	3092	38	0	0
T114	13385	42	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381762084	1623	0	0
T105	1530	8	0	0
T106	3938	18	0	0
T107	9516	97	0	0
T108	4921	11	0	0
T109	6264	105	0	0
T110	3774	22	0	0
T111	26240	238	0	0
T112	7798	49	0	0
T113	3092	7	0	0
T114	13385	15	0	0