3d5660d90
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 46.630s | 2.835ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 49.880s | 5.055ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.470s | 123.847us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.620s | 62.915us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 29.950s | 14.355ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 10.840s | 512.235us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.060s | 322.999us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.620s | 62.915us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 10.840s | 512.235us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 2.175m | 11.067ms | 50 | 50 | 100.00 |
V2 | sideload | keymgr_sideload | 45.390s | 6.072ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 58.360s | 8.952ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 46.850s | 3.556ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 44.950s | 1.649ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 33.780s | 2.238ms | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 13.950s | 2.290ms | 48 | 50 | 96.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 59.450s | 1.961ms | 50 | 50 | 100.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 1.856m | 23.746ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 58.170s | 8.197ms | 50 | 50 | 100.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 29.390s | 3.520ms | 50 | 50 | 100.00 |
V2 | stress_all | keymgr_stress_all | 9.522m | 61.445ms | 49 | 50 | 98.00 |
V2 | intr_test | keymgr_intr_test | 1.060s | 25.810us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 0.990s | 24.118us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 4.740s | 526.792us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 4.740s | 526.792us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.470s | 123.847us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.620s | 62.915us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.840s | 512.235us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.730s | 93.393us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.470s | 123.847us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.620s | 62.915us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.840s | 512.235us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.730s | 93.393us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 737 | 740 | 99.59 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 17.310s | 1.505ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 17.310s | 1.505ms | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 1.299m | 4.750ms | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 12.600s | 356.075us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 12.600s | 356.075us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 12.600s | 356.075us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 12.600s | 356.075us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 19.400s | 2.438ms | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 17.310s | 1.505ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 17.310s | 1.505ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 1.299m | 4.750ms | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 12.600s | 356.075us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 2.175m | 11.067ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 49.880s | 5.055ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.620s | 62.915us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 49.880s | 5.055ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.620s | 62.915us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 49.880s | 5.055ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.620s | 62.915us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 13.950s | 2.290ms | 48 | 50 | 96.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 58.170s | 8.197ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 58.170s | 8.197ms | 50 | 50 | 100.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 49.880s | 5.055ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 48.960s | 7.124ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 17.310s | 1.505ms | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 17.310s | 1.505ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 17.310s | 1.505ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 36.420s | 3.354ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 13.950s | 2.290ms | 48 | 50 | 96.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 17.310s | 1.505ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 17.310s | 1.505ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 17.310s | 1.505ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 36.420s | 3.354ms | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 36.420s | 3.354ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 17.310s | 1.505ms | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 36.420s | 3.354ms | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 17.310s | 1.505ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 36.420s | 3.354ms | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 13.740s | 271.160us | 48 | 50 | 96.00 |
V3 | TOTAL | 48 | 50 | 96.00 | |||
TOTAL | 1105 | 1110 | 99.55 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 14 | 87.50 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.78 | 99.09 | 98.13 | 98.09 | 100.00 | 99.17 | 98.38 | 91.63 |
UVM_ERROR (keymgr_scoreboard.sv:674) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*])
has 2 failures:
Test keymgr_lc_disable has 1 failures.
8.keymgr_lc_disable.2622667485
Line 471, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/8.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 93068930 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (2 [0x2] vs 3 [0x3])
UVM_INFO @ 93068930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_stress_all_with_rand_reset has 1 failures.
30.keymgr_stress_all_with_rand_reset.2471340233
Line 1008, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/30.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 815340691 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
UVM_INFO @ 815340691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:281) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 2 failures:
Test keymgr_lc_disable has 1 failures.
25.keymgr_lc_disable.1639903568
Line 522, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/25.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 80356726 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
UVM_INFO @ 80356726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_stress_all has 1 failures.
40.keymgr_stress_all.2367784290
Line 1936, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/40.keymgr_stress_all/latest/run.log
UVM_ERROR @ 5446460642 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 5446460642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:1010) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation
has 1 failures:
44.keymgr_stress_all_with_rand_reset.1783089954
Line 696, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/44.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 149198871 ps: (keymgr_scoreboard.sv:1010) [uvm_test_top.env.scoreboard] Check failed act == exp (5707996733830226204028143345576529233255584091456259735407613400667181622436362230725846610843503850067397832566296468660704289930328332158876521025934363816502260291727033199492146270728780217351158787643781995213334259306034801406487808964191240380628806163633873592938514031167068483337045426107696222657408384357509540950541497964920975228844418599379750628497945771564793575108601487349742707110391109113851409199655800 [0xce4ba6e00c09919a75fdb533558eba5fd0f162faac53ef3a98cec09a700964ba3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78] vs 2110071882106773923431701333060935996808210991847326631862194373351027592030749007113064140642587125957874804221472254397235119843821971589756159543535403304414760665635043068600550505818920357470248335181736012812100637054147119785477404847637189802304366750717378194786810209581738325610854126946516376122045722490970259093234380233138953805754348205274019499685457344320850766146016020093910763857121199188030813325880184 [0x4c42da639b95b8dbf1df0985d02443fe99d42f759637699fadd6a2a271b8f96c3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78]) cdi_type: Attestation
DiversificationKey act: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78, exp: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78
RomDigest act: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507, exp: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507
HealthMeasurement act: 0x5cfbd765ce33f34e, exp: 0x5cfbd765ce33f34e