9f20940d49
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 52.650s | 5.782ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 49.670s | 1.919ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.530s | 28.960us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.870s | 116.911us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 27.990s | 861.337us | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 11.080s | 1.032ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.600s | 46.327us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.870s | 116.911us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 11.080s | 1.032ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 1.861m | 10.500ms | 48 | 50 | 96.00 |
V2 | sideload | keymgr_sideload | 49.370s | 6.171ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 1.111m | 6.209ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 49.470s | 9.044ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 53.440s | 16.958ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 28.760s | 808.894us | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 7.740s | 517.504us | 48 | 50 | 96.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 7.600s | 722.659us | 49 | 50 | 98.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 1.753m | 11.209ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 55.220s | 2.245ms | 50 | 50 | 100.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 30.300s | 4.902ms | 50 | 50 | 100.00 |
V2 | stress_all | keymgr_stress_all | 5.353m | 10.765ms | 49 | 50 | 98.00 |
V2 | intr_test | keymgr_intr_test | 1.290s | 221.096us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.420s | 48.650us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 6.810s | 424.876us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 6.810s | 424.876us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.530s | 28.960us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.870s | 116.911us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 11.080s | 1.032ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.520s | 108.815us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.530s | 28.960us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.870s | 116.911us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 11.080s | 1.032ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.520s | 108.815us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 734 | 740 | 99.19 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 16.160s | 2.294ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 16.160s | 2.294ms | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 13.170s | 561.153us | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 7.030s | 257.518us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 7.030s | 257.518us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 7.030s | 257.518us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 7.030s | 257.518us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 14.740s | 344.996us | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 16.160s | 2.294ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 16.160s | 2.294ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 13.170s | 561.153us | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 7.030s | 257.518us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 1.861m | 10.500ms | 48 | 50 | 96.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 49.670s | 1.919ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.870s | 116.911us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 49.670s | 1.919ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.870s | 116.911us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 49.670s | 1.919ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.870s | 116.911us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 7.740s | 517.504us | 48 | 50 | 96.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 55.220s | 2.245ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 55.220s | 2.245ms | 50 | 50 | 100.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 49.670s | 1.919ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 22.450s | 2.471ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 16.160s | 2.294ms | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 16.160s | 2.294ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 16.160s | 2.294ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 21.420s | 3.547ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 7.740s | 517.504us | 48 | 50 | 96.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 16.160s | 2.294ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 16.160s | 2.294ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 16.160s | 2.294ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 21.420s | 3.547ms | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 21.420s | 3.547ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 16.160s | 2.294ms | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 21.420s | 3.547ms | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 16.160s | 2.294ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 21.420s | 3.547ms | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 26.210s | 1.339ms | 28 | 50 | 56.00 |
V3 | TOTAL | 28 | 50 | 56.00 | |||
TOTAL | 1082 | 1110 | 97.48 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 12 | 75.00 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.78 | 99.04 | 98.07 | 98.77 | 100.00 | 99.02 | 98.41 | 91.14 |
UVM_ERROR (cip_base_vseq.sv:836) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 21 failures:
1.keymgr_stress_all_with_rand_reset.81489113112067604825119735185042947819207650021506259968899947742061521159522
Line 384, in log /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 913929564 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 913929564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.keymgr_stress_all_with_rand_reset.108344501315227262422065924994428170522389788276255909651755311659977307254680
Line 1017, in log /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 715323764 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 715323764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data ==
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 2 failures:
10.keymgr_cfg_regwen.28175880461886502632833885063224407929262819514643359389970202865710600972912
Line 174, in log /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_cfg_regwen/latest/run.log
UVM_ERROR @ 25778824 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
UVM_INFO @ 25778824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.keymgr_cfg_regwen.17238420210491753676977484438472743821108281469451896016937365228854736509321
Line 153, in log /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_cfg_regwen/latest/run.log
UVM_ERROR @ 8657766 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
UVM_INFO @ 8657766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*])
has 1 failures:
12.keymgr_stress_all_with_rand_reset.104096456503917261700395407920005912172755270915382001281635807728992282043737
Line 518, in log /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 502073502 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
UVM_INFO @ 502073502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*])
has 1 failures:
15.keymgr_lc_disable.35859833524634376537325838030776679483067430633249552557755166140314885471736
Line 461, in log /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 70817888 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (3 [0x3] vs 6 [0x6])
UVM_INFO @ 70817888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly
has 1 failures:
16.keymgr_kmac_rsp_err.87421433524148149628229727524127702460549561925461528312116296129662516520491
Line 258, in log /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_kmac_rsp_err/latest/run.log
UVM_ERROR @ 62387995 ps: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
UVM_INFO @ 62387995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StCreatorRootKey for Attestation Kmac
has 1 failures:
26.keymgr_lc_disable.63614950409463951540149566705204306464461990377251601192132249354321688158581
Line 228, in log /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 61712825 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (12558521387397354972845600045882729789398199720581372470297469692749367319329360788772889651600015500536172897471107657193819273417375567129636625811065408 [0xefc8c61b3b8ace7be73c3fe52971439eeb2c650c914fadbf8205d08de5e1b7b51a6ab7e5798ee62f34d3555a2860443fe33aab2ffb4b7a0d4b0d971f4b354a40] vs 12558521387397354972845600045882729789398199720581372470297469692749367319329360788772889651600015500536172897471107657193819273417375567129636625811065408 [0xefc8c61b3b8ace7be73c3fe52971439eeb2c650c914fadbf8205d08de5e1b7b51a6ab7e5798ee62f34d3555a2860443fe33aab2ffb4b7a0d4b0d971f4b354a40]) KMAC key at state StCreatorRootKey for Attestation Kmac
UVM_INFO @ 61712825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 1 failures:
29.keymgr_stress_all.104684491207175423090991736572114485667983326097484962713904341266063464684884
Line 2603, in log /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_stress_all/latest/run.log
UVM_ERROR @ 367880215 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 367880215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---