KEYMGR Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 8.800s 553.168us 50 50 100.00
V1 random keymgr_random 13.730s 934.647us 50 50 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 0.950s 28.761us 5 5 100.00
V1 csr_rw keymgr_csr_rw 0.970s 25.458us 20 20 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 8.630s 778.988us 5 5 100.00
V1 csr_aliasing keymgr_csr_aliasing 5.070s 324.134us 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.120s 37.083us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 0.970s 25.458us 20 20 100.00
keymgr_csr_aliasing 5.070s 324.134us 5 5 100.00
V1 TOTAL 155 155 100.00
V2 cfgen_during_op keymgr_cfg_regwen 23.080s 735.452us 50 50 100.00
V2 sideload keymgr_sideload 10.350s 592.346us 50 50 100.00
keymgr_sideload_kmac 11.220s 620.346us 50 50 100.00
keymgr_sideload_aes 10.840s 620.346us 50 50 100.00
keymgr_sideload_otbn 11.020s 620.346us 50 50 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 4.240s 268.563us 50 50 100.00
V2 lc_disable keymgr_lc_disable 2.320s 95.314us 50 50 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 17.970s 1.002ms 50 50 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 12.120s 754.416us 50 50 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 11.930s 964.915us 50 50 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 4.290s 278.242us 50 50 100.00
V2 stress_all keymgr_stress_all 2.849m 11.555ms 50 50 100.00
V2 intr_test keymgr_intr_test 0.770s 18.922us 50 50 100.00
V2 alert_test keymgr_alert_test 0.760s 17.886us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 2.070s 108.689us 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 2.070s 108.689us 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 0.950s 28.761us 5 5 100.00
keymgr_csr_rw 0.970s 25.458us 20 20 100.00
keymgr_csr_aliasing 5.070s 324.134us 5 5 100.00
keymgr_same_csr_outstanding 1.590s 83.761us 20 20 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 0.950s 28.761us 5 5 100.00
keymgr_csr_rw 0.970s 25.458us 20 20 100.00
keymgr_csr_aliasing 5.070s 324.134us 5 5 100.00
keymgr_same_csr_outstanding 1.590s 83.761us 20 20 100.00
V2 TOTAL 740 740 100.00
V2S sec_cm_additional_check keymgr_sec_cm 33.730s 2.434ms 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 33.730s 2.434ms 5 5 100.00
keymgr_tl_intg_err 8.180s 532.293us 20 20 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 6.340s 474.240us 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 6.340s 474.240us 20 20 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 6.340s 474.240us 20 20 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 6.340s 474.240us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 5.560s 352.830us 20 20 100.00
V2S prim_count_check keymgr_sec_cm 33.730s 2.434ms 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 33.730s 2.434ms 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 8.180s 532.293us 20 20 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 6.340s 474.240us 20 20 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 23.080s 735.452us 50 50 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 13.730s 934.647us 50 50 100.00
keymgr_csr_rw 0.970s 25.458us 20 20 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 13.730s 934.647us 50 50 100.00
keymgr_csr_rw 0.970s 25.458us 20 20 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 13.730s 934.647us 50 50 100.00
keymgr_csr_rw 0.970s 25.458us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 2.320s 95.314us 50 50 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 11.930s 964.915us 50 50 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 11.930s 964.915us 50 50 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 13.730s 934.647us 50 50 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 3.720s 272.617us 50 50 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 33.730s 2.434ms 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 33.730s 2.434ms 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 33.730s 2.434ms 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 3.110s 177.046us 50 50 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 2.320s 95.314us 50 50 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 33.730s 2.434ms 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 33.730s 2.434ms 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 33.730s 2.434ms 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 3.110s 177.046us 50 50 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 3.110s 177.046us 50 50 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 33.730s 2.434ms 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 3.110s 177.046us 50 50 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 33.730s 2.434ms 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 3.110s 177.046us 50 50 100.00
V2S TOTAL 165 165 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 3.410s 166.153us 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1110 1110 100.00

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 16 16 16 100.00
V2S 6 6 6 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
89.73 98.68 93.84 97.77 88.37 97.85 90.89 60.70

Past Results