KEYMGR Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: 877a77116

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 39.900s 1.708ms 50 50 100.00
V1 random keymgr_random 1.852m 9.521ms 50 50 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.450s 243.092us 5 5 100.00
V1 csr_rw keymgr_csr_rw 1.550s 29.011us 20 20 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 14.810s 426.681us 5 5 100.00
V1 csr_aliasing keymgr_csr_aliasing 13.650s 1.288ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.630s 42.905us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.550s 29.011us 20 20 100.00
keymgr_csr_aliasing 13.650s 1.288ms 5 5 100.00
V1 TOTAL 155 155 100.00
V2 cfgen_during_op keymgr_cfg_regwen 1.877m 9.594ms 50 50 100.00
V2 sideload keymgr_sideload 53.330s 7.708ms 50 50 100.00
keymgr_sideload_kmac 42.330s 21.070ms 50 50 100.00
keymgr_sideload_aes 50.590s 1.673ms 50 50 100.00
keymgr_sideload_otbn 1.042m 1.912ms 50 50 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 19.390s 3.496ms 50 50 100.00
V2 lc_disable keymgr_lc_disable 9.410s 4.544ms 49 50 98.00
V2 kmac_error_response keymgr_kmac_rsp_err 1.232m 3.752ms 40 50 80.00
V2 invalid_sw_input keymgr_sw_invalid_input 1.118m 10.587ms 50 50 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 1.357m 7.537ms 50 50 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 13.530s 625.100us 50 50 100.00
V2 stress_all keymgr_stress_all 9.148m 32.022ms 48 50 96.00
V2 intr_test keymgr_intr_test 0.880s 56.153us 50 50 100.00
V2 alert_test keymgr_alert_test 1.030s 38.143us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 4.290s 1.156ms 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 4.290s 1.156ms 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.450s 243.092us 5 5 100.00
keymgr_csr_rw 1.550s 29.011us 20 20 100.00
keymgr_csr_aliasing 13.650s 1.288ms 5 5 100.00
keymgr_same_csr_outstanding 3.560s 191.401us 20 20 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.450s 243.092us 5 5 100.00
keymgr_csr_rw 1.550s 29.011us 20 20 100.00
keymgr_csr_aliasing 13.650s 1.288ms 5 5 100.00
keymgr_same_csr_outstanding 3.560s 191.401us 20 20 100.00
V2 TOTAL 727 740 98.24
V2S sec_cm_additional_check keymgr_sec_cm 3.407m 17.522ms 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 3.407m 17.522ms 5 5 100.00
keymgr_tl_intg_err 32.450s 2.680ms 20 20 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 33.490s 9.399ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 33.490s 9.399ms 20 20 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 33.490s 9.399ms 20 20 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 33.490s 9.399ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 16.820s 2.873ms 20 20 100.00
V2S prim_count_check keymgr_sec_cm 3.407m 17.522ms 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 3.407m 17.522ms 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 32.450s 2.680ms 20 20 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 33.490s 9.399ms 20 20 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 1.877m 9.594ms 50 50 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 1.852m 9.521ms 50 50 100.00
keymgr_csr_rw 1.550s 29.011us 20 20 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 1.852m 9.521ms 50 50 100.00
keymgr_csr_rw 1.550s 29.011us 20 20 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 1.852m 9.521ms 50 50 100.00
keymgr_csr_rw 1.550s 29.011us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 9.410s 4.544ms 49 50 98.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 1.357m 7.537ms 50 50 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 1.357m 7.537ms 50 50 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 1.852m 9.521ms 50 50 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 19.860s 769.124us 50 50 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 3.407m 17.522ms 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 3.407m 17.522ms 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 3.407m 17.522ms 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 1.294m 2.229ms 49 50 98.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 9.410s 4.544ms 49 50 98.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 3.407m 17.522ms 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 3.407m 17.522ms 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 3.407m 17.522ms 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 1.294m 2.229ms 49 50 98.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 1.294m 2.229ms 49 50 98.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 3.407m 17.522ms 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 1.294m 2.229ms 49 50 98.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 3.407m 17.522ms 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 1.294m 2.229ms 49 50 98.00
V2S TOTAL 164 165 99.39
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 19.410s 2.466ms 42 50 84.00
V3 TOTAL 42 50 84.00
TOTAL 1088 1110 98.02

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 16 16 13 81.25
V2S 6 6 5 83.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.77 99.09 98.09 98.14 100.00 99.08 98.38 91.63

Failure Buckets

Past Results