Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4222806	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

625307

1

T1

281

T2

378

T3

255

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4427344	1			T1	645		T2	666		T3	1239
values[0x0]	208577	1			T1	149		T2	129		T3	75
values[0x1]	212192	1			T1	133		T2	124		T3	60

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2874294	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1973819

1

T1

482

T2

534

T3

592

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15796	1			T1	2		T2	5		T15	3
valid_sources[0x01]	17097	1			T1	2		T2	6		T13	3
valid_sources[0x02]	15959	1			T1	4		T2	6		T13	6
valid_sources[0x03]	15726	1			T1	3		T2	8		T13	3
valid_sources[0x04]	16473	1			T1	3		T2	3		T15	5
valid_sources[0x05]	30942	1			T1	5		T2	6		T13	4
valid_sources[0x06]	16891	1			T1	2		T2	1		T13	6
valid_sources[0x07]	16350	1			T1	3		T2	1		T13	2
valid_sources[0x08]	17434	1			T1	5		T2	5		T13	11
valid_sources[0x09]	16364	1			T1	8		T2	15		T18	12
valid_sources[0x0a]	16903	1			T1	9		T18	6		T7	3
valid_sources[0x0b]	15599	1			T1	7		T2	9		T13	8
valid_sources[0x0c]	19599	1			T1	4		T2	1		T13	6
valid_sources[0x0d]	16349	1			T1	3		T2	3		T13	1
valid_sources[0x0e]	16220	1			T1	6		T2	9		T13	6
valid_sources[0x0f]	17264	1			T1	4		T2	3		T15	1
valid_sources[0x10]	20648	1			T1	6		T2	7		T13	7
valid_sources[0x11]	16066	1			T1	2		T2	9		T13	15
valid_sources[0x12]	15937	1			T1	3		T2	5		T13	1
valid_sources[0x13]	17471	1			T1	1		T2	6		T13	4
valid_sources[0x14]	24129	1			T1	3		T2	1		T13	7
valid_sources[0x15]	16815	1			T1	2		T2	10		T15	5
valid_sources[0x16]	16747	1			T1	5		T2	6		T13	1
valid_sources[0x17]	16826	1			T1	4		T2	3		T13	8
valid_sources[0x18]	15460	1			T1	6		T2	8		T13	9
valid_sources[0x19]	15995	1			T1	1		T2	2		T13	4
valid_sources[0x1a]	21011	1			T1	4		T2	3		T14	4725
valid_sources[0x1b]	16954	1			T1	5		T2	2		T15	4
valid_sources[0x1c]	15814	1			T1	1		T2	1		T13	1
valid_sources[0x1d]	17113	1			T1	1		T2	11		T15	3
valid_sources[0x1e]	18531	1			T1	5		T2	3		T13	3
valid_sources[0x1f]	16328	1			T1	6		T2	2		T13	3
valid_sources[0x20]	16714	1			T1	2		T13	2		T18	5
valid_sources[0x21]	17038	1			T1	3		T2	1		T13	3
valid_sources[0x22]	18779	1			T1	3		T15	5		T78	6
valid_sources[0x23]	15569	1			T1	2		T2	2		T13	1
valid_sources[0x24]	17326	1			T1	5		T2	1		T7	8
valid_sources[0x25]	24255	1			T1	3		T2	3		T13	3
valid_sources[0x26]	17214	1			T1	4		T2	1		T15	3
valid_sources[0x27]	17751	1			T1	1		T13	4		T78	7
valid_sources[0x28]	15834	1			T1	2		T2	5		T18	5
valid_sources[0x29]	16299	1			T1	2		T2	3		T13	5
valid_sources[0x2a]	17792	1			T1	7		T2	4		T13	5
valid_sources[0x2b]	17836	1			T1	5		T2	1		T13	1
valid_sources[0x2c]	15632	1			T1	4		T2	4		T19	15
valid_sources[0x2d]	16171	1			T1	3		T2	3		T13	3
valid_sources[0x2e]	15576	1			T1	5		T13	12		T15	1
valid_sources[0x2f]	16441	1			T1	1		T2	7		T13	3
valid_sources[0x30]	15959	1			T1	2		T2	4		T15	1
valid_sources[0x31]	15715	1			T1	5		T2	4		T13	2
valid_sources[0x32]	23826	1			T1	2		T2	3		T15	6
valid_sources[0x33]	16060	1			T1	3		T2	3		T15	1
valid_sources[0x34]	16286	1			T1	4		T18	1		T78	4
valid_sources[0x35]	18227	1			T1	3		T2	4		T13	2
valid_sources[0x36]	17200	1			T1	5		T2	6		T13	4
valid_sources[0x37]	15995	1			T1	3		T2	7		T18	3
valid_sources[0x38]	17684	1			T1	4		T2	3		T15	2
valid_sources[0x39]	15890	1			T1	4		T2	11		T16	88
valid_sources[0x3a]	15912	1			T1	6		T2	2		T13	9
valid_sources[0x3b]	19283	1			T1	3		T2	7		T13	8
valid_sources[0x3c]	17749	1			T1	5		T2	2		T13	6
valid_sources[0x3d]	15838	1			T1	5		T2	2		T18	3
valid_sources[0x3e]	15966	1			T1	1		T2	3		T18	4
valid_sources[0x3f]	34221	1			T1	6		T2	7		T15	4
valid_sources[0x40]	16392	1			T1	6		T2	2		T13	3
valid_sources[0x41]	16045	1			T1	4		T18	6		T7	4
valid_sources[0x42]	22560	1			T1	3		T2	3		T13	18
valid_sources[0x43]	16045	1			T1	4		T13	6		T15	1
valid_sources[0x44]	17059	1			T1	3		T2	3		T13	2
valid_sources[0x45]	16576	1			T1	1		T2	9		T18	5
valid_sources[0x46]	17860	1			T1	4		T2	3		T13	1
valid_sources[0x47]	15947	1			T1	4		T2	5		T15	3
valid_sources[0x48]	16055	1			T1	2		T2	8		T13	5
valid_sources[0x49]	15740	1			T1	2		T2	6		T16	64
valid_sources[0x4a]	18275	1			T1	6		T2	1		T13	2
valid_sources[0x4b]	29257	1			T1	3		T2	3		T13	1
valid_sources[0x4c]	26266	1			T1	3		T13	4		T18	3
valid_sources[0x4d]	15832	1			T1	2		T2	2		T13	7
valid_sources[0x4e]	17181	1			T1	3		T2	3		T15	1
valid_sources[0x4f]	16594	1			T1	5		T2	9		T15	1
valid_sources[0x50]	17023	1			T1	3		T13	4		T15	10
valid_sources[0x51]	18219	1			T1	3		T2	2		T13	11
valid_sources[0x52]	17016	1			T1	6		T2	1		T18	6
valid_sources[0x53]	16230	1			T1	3		T2	12		T13	7
valid_sources[0x54]	15882	1			T1	1		T2	2		T13	8
valid_sources[0x55]	16928	1			T1	3		T2	1		T13	7
valid_sources[0x56]	16209	1			T1	5		T2	2		T13	1
valid_sources[0x57]	16663	1			T1	6		T2	4		T15	3
valid_sources[0x58]	16306	1			T1	3		T2	2		T15	4
valid_sources[0x59]	16746	1			T1	5		T2	1		T13	1
valid_sources[0x5a]	15625	1			T1	3		T2	2		T15	4
valid_sources[0x5b]	16156	1			T1	4		T2	7		T13	4
valid_sources[0x5c]	16541	1			T1	2		T2	3		T13	5
valid_sources[0x5d]	16875	1			T1	2		T2	3		T13	10
valid_sources[0x5e]	22645	1			T1	5		T2	7		T13	1
valid_sources[0x5f]	16199	1			T1	2		T2	4		T13	7
valid_sources[0x60]	16334	1			T1	4		T2	1		T13	1
valid_sources[0x61]	45686	1			T1	2		T2	5		T18	1
valid_sources[0x62]	20357	1			T1	6		T2	3		T13	1
valid_sources[0x63]	16140	1			T1	5		T2	9		T13	14
valid_sources[0x64]	16753	1			T1	1		T2	2		T13	2
valid_sources[0x65]	17964	1			T1	3		T2	6		T13	3
valid_sources[0x66]	16439	1			T1	1		T2	6		T13	6
valid_sources[0x67]	18659	1			T1	2		T2	1		T13	10
valid_sources[0x68]	16714	1			T1	8		T2	3		T13	3
valid_sources[0x69]	21000	1			T1	6		T2	1		T15	2
valid_sources[0x6a]	24741	1			T1	3		T2	3		T13	8
valid_sources[0x6b]	16210	1			T1	3		T2	2		T18	4
valid_sources[0x6c]	16016	1			T1	7		T2	4		T13	2
valid_sources[0x6d]	15460	1			T1	4		T2	2		T13	15
valid_sources[0x6e]	16158	1			T1	6		T2	2		T13	13
valid_sources[0x6f]	15536	1			T1	2		T2	1		T13	1
valid_sources[0x70]	17226	1			T1	2		T2	4		T13	6
valid_sources[0x71]	18417	1			T1	5		T2	3		T13	1
valid_sources[0x72]	15571	1			T1	3		T2	3		T13	5
valid_sources[0x73]	17282	1			T1	2		T2	3		T13	5
valid_sources[0x74]	17433	1			T1	2		T2	4		T13	1
valid_sources[0x75]	16120	1			T1	6		T2	1		T13	6
valid_sources[0x76]	15651	1			T1	5		T2	4		T13	1
valid_sources[0x77]	15902	1			T1	3		T13	2		T15	3
valid_sources[0x78]	15928	1			T1	2		T2	4		T13	9
valid_sources[0x79]	15996	1			T1	2		T2	5		T13	1
valid_sources[0x7a]	16368	1			T1	6		T2	1		T15	3
valid_sources[0x7b]	30559	1			T1	4		T2	12		T13	15
valid_sources[0x7c]	36081	1			T1	1		T2	3		T18	6
valid_sources[0x7d]	17906	1			T1	6		T2	1		T13	7
valid_sources[0x7e]	15683	1			T2	3		T13	8		T16	45
valid_sources[0x7f]	15674	1			T1	7		T18	9		T78	2
valid_sources[0x80]	25894	1			T1	5		T2	1		T13	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

334007

1

T1

69

T2

202

T3

222

values[0x0]

all_enables

biggest_size

152690

1

T1

115

T2

96

T3

20

values[0x1]

all_enables

biggest_size

138610

1

T1

97

T2

80

T3

13