Unified Coverage Report :: Module :: keymgr_kmac_if

Module : keymgr_kmac_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.66	100.00	90.91		54.55	92.86	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_kmac_if	96.75	100.00	90.91		100.00	92.86	100.00

---

Module Instance : tb.dut.u_kmac_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.75	100.00	90.91		100.00	92.86	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.35	100.00	90.91	100.00	100.00	93.18	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cnt	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : keymgr_kmac_if

	Line No.	Total	Covered	Percent
TOTAL		111	111	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	156	3	3	100.00
ALWAYS	164	3	3	100.00
ALWAYS	167	56	56	100.00
CONT_ASSIGN	282	1	1	100.00
ALWAYS	290	8	8	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
ALWAYS	319	9	9	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	333	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
ALWAYS	352	4	4	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
ALWAYS	368	7	7	100.00
CONT_ASSIGN	380	1	1	100.00
CONT_ASSIGN	383	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
130	1	1
131	1	1
132	1	1
134	1	1
156	1	1
157	1	1
159	1	1
164	3	3
167	1	1
168	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
177	1	1
178	1	1
179	1	1
181	1	1
183	1	1
185	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			==> MISSING_ELSE
203	1	1
			MISSING_ELSE
208	1	1
209	1	1
212	1	1
213	1	1
216	1	1
217	1	1
			MISSING_ELSE
			MISSING_ELSE
224	1	1
225	1	1
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
			MISSING_ELSE
236	1	1
237	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
251	1	1
252	1	1
255	1	1
256	1	1
257	1	1
258	1	1
			==> MISSING_ELSE
274	1	1
275	1	1
276	1	1
277	1	1
			MISSING_ELSE
282	1	1
290	1	1
292	1	1
293	1	1
294	1	1
295	1	1
297	1	1
299	1	1
301	1	1
			MISSING_ELSE
307	1	1
310	1	1
311	1	1
312	1	1
317	1	1
319	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	1	1
			MISSING_ELSE
331	1	1
332	1	1
333	1	1
338	1	1
340	1	1
345	1	1
346	1	1
352	1	1
353	1	1
354	1	1
355	1	1
			MISSING_ELSE
358	1	1
364	1	1
368	1	1
369	1	1
370	1	1
371	1	1
373	1	1
374	1	1
375	1	1
380	1	1
383	1	1

---

Cond Coverage for Module : keymgr_kmac_if

	Total	Covered	Percent
Conditions	77	70	90.91
Logical	77	70	90.91
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (adv_en_i | id_en_i | gen_en_i)
             ----1---   ---2---   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       203
 EXPRESSION ((rounds == 5'b0) ? StTxLast : StTx)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       203
 SUB-EXPRESSION (rounds == 5'b0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       216
 EXPRESSION (cnt == 5'(1'b1))
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       237
 EXPRESSION (kmac_data_i.ready ? StOpWait : StTxLast)
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       282
 EXPRESSION ((start && done_o) ? ({kmac_data_i.digest_share1, kmac_data_i.digest_share0}) : ({DecoyOutputCopies {entropy_i[0]}}))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       282
 SUB-EXPRESSION (start && done_o)
                 --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (adv_en_i & (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance]))
             ----1---   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T21
1	0	Covered	T2,T3,T13
1	1	Covered	T1,T22,T23

 LINE       295
 SUB-EXPRESSION (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance])
                 -------------1-------------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T22,T8

 LINE       297
 EXPRESSION (id_en_i & (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId]))
             ---1---   ---------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T8
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       297
 SUB-EXPRESSION (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId])
                 ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T22,T8

 LINE       299
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut]))
             ----1---   ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T16,T24

 LINE       299
 SUB-EXPRESSION (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut])
                 --------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T16,T7

 LINE       301
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut]))
             ----1---   ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T16,T24

 LINE       301
 SUB-EXPRESSION (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut])
                 --------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T16,T7

 LINE       320
 EXPRESSION (((|cmd_error_o)) || inputs_invalid_o || fsm_error_o)
             --------1-------    --------2-------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T10,T11,T12
0	1	0	Covered	T1,T16,T24
1	0	0	Covered	T7,T6,T8

 LINE       322
 EXPRESSION (valid && adv_en_i)
             --1--    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T13

 LINE       324
 EXPRESSION (valid && id_en_i)
             --1--    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       326
 EXPRESSION (valid && gen_en_i)
             --1--    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       338
 EXPRESSION ((((~kmac_done_vld)) & kmac_data_i.done) | kmac_done_err_q)
             -------------------1-------------------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T25,T26,T27
1	0	Covered	T1,T2,T3

 LINE       338
 SUB-EXPRESSION (((~kmac_done_vld)) & kmac_data_i.done)
                 ---------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION ((cmd_chk & (enables_q != enables_d)) | cmd_consty_err_q)
             ------------------1-----------------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T6,T8
1	0	Covered	T7,T6,T8

 LINE       358
 SUB-EXPRESSION (cmd_chk & (enables_q != enables_d))
                 ---1---   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T6,T8

 LINE       358
 SUB-EXPRESSION (enables_q != enables_d)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       364
 EXPRESSION (((|(enables_d & enables_sub))) | one_hot_err_q)
             ---------------1--------------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T28,T29
1	0	Covered	T6,T28,T29

 LINE       380
 EXPRESSION (one_hot_err_q | cmd_consty_err_q)
             ------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T30,T31,T32

 LINE       383
 EXPRESSION (kmac_data_o.valid & kmac_data_i.ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : keymgr_kmac_if

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	11	6	54.55
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StClean	246	Covered	T1,T2,T3
StError	275	Covered	T10,T11,T12
StIdle	258	Covered	T1,T2,T3
StOpWait	237	Covered	T1,T2,T3
StTx	203	Covered	T1,T2,T3
StTxLast	203	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StClean->StError	275	Not Covered
StClean->StIdle	258	Covered	T1,T2,T3
StIdle->StError	275	Covered	T10,T11,T12
StIdle->StTx	203	Covered	T1,T2,T3
StIdle->StTxLast	203	Not Covered
StOpWait->StClean	246	Covered	T1,T2,T3
StOpWait->StError	275	Not Covered
StTx->StError	275	Not Covered
StTx->StTxLast	217	Covered	T1,T2,T3
StTxLast->StError	275	Not Covered
StTxLast->StOpWait	237	Covered	T1,T2,T3

---

Branch Coverage for Module : keymgr_kmac_if

	Line No.	Total	Covered	Percent
Branches		42	39	92.86
TERNARY	282	2	2	100.00
IF	156	2	2	100.00
IF	164	2	2	100.00
CASE	185	21	18	85.71
IF	274	2	2	100.00
IF	292	3	3	100.00
IF	320	5	5	100.00
IF	352	3	3	100.00
IF	368	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	282	((start && done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	185	case (state_q)
-2-:	193	if (start)
-3-:	195	if (adv_en_i)
-4-:	197	if (id_en_i)
-5-:	199	if (gen_en_i)
-6-:	203	((rounds == 5'b0)) ? 
-7-:	212	if (kmac_data_i.ready)
-8-:	216	if ((cnt == 5'(1'b1)))
-9-:	227	if (adv_en_i)
-10-:	229	if (id_en_i)
-11-:	231	if (gen_en_i)
-12-:	237	(kmac_data_i.ready) ? 
-13-:	243	if (kmac_data_i.done)
-14-:	255	if ((!start))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StIdle	1	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	1	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	1	0	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	1	0	0	0	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	1	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
StIdle	1	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StTx	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
StTx	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T1,T2,T3
StTx	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StTxLast	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
StTxLast	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T1,T2,T3
StTxLast	-	-	-	-	-	-	-	0	0	1	-	-	-	Covered	T1,T2,T3
StTxLast	-	-	-	-	-	-	-	0	0	0	-	-	-	Covered	T7,T8,T20
StTxLast	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T2,T3
StTxLast	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
StOpWait	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StOpWait	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
StClean	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
StClean	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	274	if (cnt_err)

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	292	if (clr_err)
-2-:	294	if (valid)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	320	if ((((|cmd_error_o) || inputs_invalid_o) || fsm_error_o))
-2-:	322	if ((valid && adv_en_i))
-3-:	324	if ((valid && id_en_i))
-4-:	326	if ((valid && gen_en_i))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T16,T7
0	1	-	-	Covered	T2,T3,T13
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	352	if ((!rst_ni))
-2-:	354	if (cnt_set)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	368	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr_kmac_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AdvRemBytes_A	886	886	0	0
GenRemBytes_A	886	886	0	0
IdRemBytes_A	886	886	0	0
LastStrb_A	27338117	19784937	0	0
u_state_regs_A	28012983	27848107	0	0

AdvRemBytes_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GenRemBytes_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

IdRemBytes_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

LastStrb_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27338117	19784937	0	0
T1	11109	4553	0	0
T2	4461	904	0	0
T3	4989	1885	0	0
T13	7613	1876	0	0
T14	53712	45404	0	0
T15	3864	412	0	0
T16	13112	830	0	0
T17	3976	256	0	0
T18	14724	2890	0	0
T19	6173	358	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28012983	27848107	0	0
T1	11109	11051	0	0
T2	4461	4379	0	0
T3	4989	4924	0	0
T13	7613	7419	0	0
T14	53712	53558	0	0
T15	3864	3789	0	0
T16	13112	12998	0	0
T17	3976	3833	0	0
T18	14724	14582	0	0
T19	6173	6077	0	0

Line Coverage for Instance : tb.dut.u_kmac_if

	Line No.	Total	Covered	Percent
TOTAL		111	111	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	156	3	3	100.00
ALWAYS	164	3	3	100.00
ALWAYS	167	56	56	100.00
CONT_ASSIGN	282	1	1	100.00
ALWAYS	290	8	8	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
ALWAYS	319	9	9	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	333	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
ALWAYS	352	4	4	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
ALWAYS	368	7	7	100.00
CONT_ASSIGN	380	1	1	100.00
CONT_ASSIGN	383	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
130	1	1
131	1	1
132	1	1
134	1	1
156	1	1
157	1	1
159	1	1
164	3	3
167	1	1
168	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
177	1	1
178	1	1
179	1	1
181	1	1
183	1	1
185	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			==> MISSING_ELSE
203	1	1
			MISSING_ELSE
208	1	1
209	1	1
212	1	1
213	1	1
216	1	1
217	1	1
			MISSING_ELSE
			MISSING_ELSE
224	1	1
225	1	1
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
			MISSING_ELSE
236	1	1
237	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
251	1	1
252	1	1
255	1	1
256	1	1
257	1	1
258	1	1
			==> MISSING_ELSE
274	1	1
275	1	1
276	1	1
277	1	1
			MISSING_ELSE
282	1	1
290	1	1
292	1	1
293	1	1
294	1	1
295	1	1
297	1	1
299	1	1
301	1	1
			MISSING_ELSE
307	1	1
310	1	1
311	1	1
312	1	1
317	1	1
319	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	1	1
			MISSING_ELSE
331	1	1
332	1	1
333	1	1
338	1	1
340	1	1
345	1	1
346	1	1
352	1	1
353	1	1
354	1	1
355	1	1
			MISSING_ELSE
358	1	1
364	1	1
368	1	1
369	1	1
370	1	1
371	1	1
373	1	1
374	1	1
375	1	1
380	1	1
383	1	1

---

Cond Coverage for Instance : tb.dut.u_kmac_if

	Total	Covered	Percent
Conditions	77	70	90.91
Logical	77	70	90.91
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (adv_en_i | id_en_i | gen_en_i)
             ----1---   ---2---   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       203
 EXPRESSION ((rounds == 5'b0) ? StTxLast : StTx)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       203
 SUB-EXPRESSION (rounds == 5'b0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       216
 EXPRESSION (cnt == 5'(1'b1))
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       237
 EXPRESSION (kmac_data_i.ready ? StOpWait : StTxLast)
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       282
 EXPRESSION ((start && done_o) ? ({kmac_data_i.digest_share1, kmac_data_i.digest_share0}) : ({DecoyOutputCopies {entropy_i[0]}}))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       282
 SUB-EXPRESSION (start && done_o)
                 --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (adv_en_i & (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance]))
             ----1---   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T21
1	0	Covered	T2,T3,T13
1	1	Covered	T1,T22,T23

 LINE       295
 SUB-EXPRESSION (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance])
                 -------------1-------------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T22,T8

 LINE       297
 EXPRESSION (id_en_i & (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId]))
             ---1---   ---------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T8
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       297
 SUB-EXPRESSION (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId])
                 ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T22,T8

 LINE       299
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut]))
             ----1---   ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T16,T24

 LINE       299
 SUB-EXPRESSION (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut])
                 --------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T16,T7

 LINE       301
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut]))
             ----1---   ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T16,T24

 LINE       301
 SUB-EXPRESSION (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut])
                 --------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T16,T7

 LINE       320
 EXPRESSION (((|cmd_error_o)) || inputs_invalid_o || fsm_error_o)
             --------1-------    --------2-------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T10,T11,T12
0	1	0	Covered	T1,T16,T24
1	0	0	Covered	T7,T6,T8

 LINE       322
 EXPRESSION (valid && adv_en_i)
             --1--    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T13

 LINE       324
 EXPRESSION (valid && id_en_i)
             --1--    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       326
 EXPRESSION (valid && gen_en_i)
             --1--    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       338
 EXPRESSION ((((~kmac_done_vld)) & kmac_data_i.done) | kmac_done_err_q)
             -------------------1-------------------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T25,T26,T27
1	0	Covered	T1,T2,T3

 LINE       338
 SUB-EXPRESSION (((~kmac_done_vld)) & kmac_data_i.done)
                 ---------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION ((cmd_chk & (enables_q != enables_d)) | cmd_consty_err_q)
             ------------------1-----------------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T6,T8
1	0	Covered	T7,T6,T8

 LINE       358
 SUB-EXPRESSION (cmd_chk & (enables_q != enables_d))
                 ---1---   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T6,T8

 LINE       358
 SUB-EXPRESSION (enables_q != enables_d)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       364
 EXPRESSION (((|(enables_d & enables_sub))) | one_hot_err_q)
             ---------------1--------------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T28,T29
1	0	Covered	T6,T28,T29

 LINE       380
 EXPRESSION (one_hot_err_q | cmd_consty_err_q)
             ------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T30,T31,T32

 LINE       383
 EXPRESSION (kmac_data_o.valid & kmac_data_i.ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_kmac_if

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StClean	246	Covered	T1,T2,T3
StError	275	Covered	T10,T11,T12
StIdle	258	Covered	T1,T2,T3
StOpWait	237	Covered	T1,T2,T3
StTx	203	Covered	T1,T2,T3
StTxLast	203	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StClean->StError	275	Excluded
StClean->StIdle	258	Covered	T1,T2,T3
StIdle->StError	275	Covered	T10,T11,T12
StIdle->StTx	203	Covered	T1,T2,T3
StIdle->StTxLast	203	Excluded
StOpWait->StClean	246	Covered	T1,T2,T3
StOpWait->StError	275	Excluded
StTx->StError	275	Excluded
StTx->StTxLast	217	Covered	T1,T2,T3
StTxLast->StError	275	Excluded
StTxLast->StOpWait	237	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_kmac_if

	Line No.	Total	Covered	Percent
Branches		42	39	92.86
TERNARY	282	2	2	100.00
IF	156	2	2	100.00
IF	164	2	2	100.00
CASE	185	21	18	85.71
IF	274	2	2	100.00
IF	292	3	3	100.00
IF	320	5	5	100.00
IF	352	3	3	100.00
IF	368	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	282	((start && done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	185	case (state_q)
-2-:	193	if (start)
-3-:	195	if (adv_en_i)
-4-:	197	if (id_en_i)
-5-:	199	if (gen_en_i)
-6-:	203	((rounds == 5'b0)) ? 
-7-:	212	if (kmac_data_i.ready)
-8-:	216	if ((cnt == 5'(1'b1)))
-9-:	227	if (adv_en_i)
-10-:	229	if (id_en_i)
-11-:	231	if (gen_en_i)
-12-:	237	(kmac_data_i.ready) ? 
-13-:	243	if (kmac_data_i.done)
-14-:	255	if ((!start))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StIdle	1	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	1	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	1	0	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	1	0	0	0	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	1	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
StIdle	1	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StTx	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
StTx	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T1,T2,T3
StTx	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StTxLast	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
StTxLast	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T1,T2,T3
StTxLast	-	-	-	-	-	-	-	0	0	1	-	-	-	Covered	T1,T2,T3
StTxLast	-	-	-	-	-	-	-	0	0	0	-	-	-	Covered	T7,T8,T20
StTxLast	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T2,T3
StTxLast	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
StOpWait	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StOpWait	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
StClean	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
StClean	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	274	if (cnt_err)

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	292	if (clr_err)
-2-:	294	if (valid)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	320	if ((((|cmd_error_o) || inputs_invalid_o) || fsm_error_o))
-2-:	322	if ((valid && adv_en_i))
-3-:	324	if ((valid && id_en_i))
-4-:	326	if ((valid && gen_en_i))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T16,T7
0	1	-	-	Covered	T2,T3,T13
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	352	if ((!rst_ni))
-2-:	354	if (cnt_set)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	368	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_kmac_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AdvRemBytes_A	886	886	0	0
GenRemBytes_A	886	886	0	0
IdRemBytes_A	886	886	0	0
LastStrb_A	27338117	19784937	0	0
u_state_regs_A	28012983	27848107	0	0

AdvRemBytes_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GenRemBytes_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

IdRemBytes_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

LastStrb_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27338117	19784937	0	0
T1	11109	4553	0	0
T2	4461	904	0	0
T3	4989	1885	0	0
T13	7613	1876	0	0
T14	53712	45404	0	0
T15	3864	412	0	0
T16	13112	830	0	0
T17	3976	256	0	0
T18	14724	2890	0	0
T19	6173	358	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28012983	27848107	0	0
T1	11109	11051	0	0
T2	4461	4379	0	0
T3	4989	4924	0	0
T13	7613	7419	0	0
T14	53712	53558	0	0
T15	3864	3789	0	0
T16	13112	12998	0	0
T17	3976	3833	0	0
T18	14724	14582	0	0
T19	6173	6077	0	0