Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	29817208	23160	0	0
attest_sw_binding_0_rd_A	29817208	2766	0	0
attest_sw_binding_1_rd_A	29817208	2920	0	0
attest_sw_binding_2_rd_A	29817208	2895	0	0
attest_sw_binding_3_rd_A	29817208	2996	0	0
attest_sw_binding_4_rd_A	29817208	2837	0	0
attest_sw_binding_5_rd_A	29817208	2905	0	0
attest_sw_binding_6_rd_A	29817208	2955	0	0
attest_sw_binding_7_rd_A	29817208	2981	0	0
intr_enable_rd_A	29817208	3902	0	0
key_version_rd_A	29817208	2931	0	0
max_creator_key_ver_regwen_rd_A	29817208	3005	0	0
max_owner_int_key_ver_regwen_rd_A	29817208	3005	0	0
max_owner_key_ver_regwen_rd_A	29817208	2902	0	0
reseed_interval_regwen_rd_A	29817208	2917	0	0
salt_0_rd_A	29817208	2906	0	0
salt_1_rd_A	29817208	2957	0	0
salt_2_rd_A	29817208	2866	0	0
salt_3_rd_A	29817208	2899	0	0
salt_4_rd_A	29817208	2928	0	0
salt_5_rd_A	29817208	2970	0	0
salt_6_rd_A	29817208	2903	0	0
salt_7_rd_A	29817208	2964	0	0
sealing_sw_binding_0_rd_A	29817208	2900	0	0
sealing_sw_binding_1_rd_A	29817208	2998	0	0
sealing_sw_binding_2_rd_A	29817208	2710	0	0
sealing_sw_binding_3_rd_A	29817208	2829	0	0
sealing_sw_binding_4_rd_A	29817208	3047	0	0
sealing_sw_binding_5_rd_A	29817208	2835	0	0
sealing_sw_binding_6_rd_A	29817208	2998	0	0
sealing_sw_binding_7_rd_A	29817208	3077	0	0
sideload_clear_rd_A	29817208	2986	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	23160	0	0
T7	9659	0	0	0
T16	13112	534	0	0
T17	3976	0	0	0
T18	14724	0	0	0
T19	6173	0	0	0
T53	7946	0	0	0
T78	22812	0	0	0
T79	185559	0	0	0
T80	8946	0	0	0
T103	0	120	0	0
T114	0	198	0	0
T124	0	468	0	0
T125	0	26	0	0
T127	0	270	0	0
T128	0	316	0	0
T129	0	81	0	0
T130	0	837	0	0
T131	9463	0	0	0
T134	0	81	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2766	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	46	0	0
T114	22409	31	0	0
T116	39873	103	0	0
T125	8432	15	0	0
T126	0	78	0	0
T128	0	1	0	0
T135	130709	0	0	0
T137	0	6	0	0
T139	0	4	0	0
T140	0	97	0	0
T141	0	15	0	0
T181	3452	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2920	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	45	0	0
T114	22409	15	0	0
T116	39873	117	0	0
T126	0	74	0	0
T128	0	3	0	0
T135	130709	0	0	0
T137	2799	2	0	0
T139	0	3	0	0
T140	0	112	0	0
T141	0	52	0	0
T144	0	115	0	0
T181	3452	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2895	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	27	0	0
T114	22409	21	0	0
T116	39873	82	0	0
T125	8432	3	0	0
T126	0	81	0	0
T128	0	14	0	0
T135	130709	0	0	0
T137	0	7	0	0
T139	0	6	0	0
T140	0	103	0	0
T141	0	41	0	0
T181	3452	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2996	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	47	0	0
T114	22409	26	0	0
T116	39873	100	0	0
T125	8432	23	0	0
T126	0	79	0	0
T135	130709	0	0	0
T137	0	7	0	0
T139	0	1	0	0
T140	0	103	0	0
T141	0	55	0	0
T144	0	111	0	0
T181	3452	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2837	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	49	0	0
T114	22409	39	0	0
T116	39873	132	0	0
T125	8432	11	0	0
T126	0	69	0	0
T128	0	8	0	0
T135	130709	0	0	0
T137	0	4	0	0
T139	0	13	0	0
T140	0	92	0	0
T141	0	40	0	0
T181	3452	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2905	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	42	0	0
T114	22409	17	0	0
T116	39873	93	0	0
T125	8432	6	0	0
T126	0	84	0	0
T135	130709	0	0	0
T137	0	6	0	0
T139	0	5	0	0
T140	0	121	0	0
T141	0	18	0	0
T144	0	142	0	0
T181	3452	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2955	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	50	0	0
T114	22409	29	0	0
T116	39873	133	0	0
T125	8432	5	0	0
T126	0	92	0	0
T128	0	14	0	0
T135	130709	0	0	0
T137	0	8	0	0
T140	0	118	0	0
T141	0	67	0	0
T144	0	111	0	0
T181	3452	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2981	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	45	0	0
T114	22409	22	0	0
T116	39873	118	0	0
T125	8432	5	0	0
T126	0	73	0	0
T128	0	4	0	0
T135	130709	0	0	0
T139	0	6	0	0
T140	0	107	0	0
T141	0	22	0	0
T144	0	99	0	0
T181	3452	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	3902	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	59	0	0
T114	22409	58	0	0
T116	39873	99	0	0
T125	0	2	0	0
T126	0	76	0	0
T135	130709	0	0	0
T137	0	12	0	0
T181	3452	0	0	0
T182	1103	7	0	0
T183	0	6	0	0
T184	0	10	0	0
T185	0	21	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2931	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	59	0	0
T114	22409	31	0	0
T116	39873	90	0	0
T125	8432	7	0	0
T126	0	110	0	0
T128	0	2	0	0
T135	130709	0	0	0
T137	0	2	0	0
T139	0	9	0	0
T140	0	103	0	0
T141	0	66	0	0
T181	3452	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	3005	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	24	0	0
T114	22409	26	0	0
T116	39873	148	0	0
T125	8432	8	0	0
T126	0	71	0	0
T128	0	3	0	0
T135	130709	0	0	0
T139	0	8	0	0
T140	0	109	0	0
T141	0	22	0	0
T144	0	100	0	0
T181	3452	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	3005	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	33	0	0
T114	22409	30	0	0
T116	39873	117	0	0
T125	8432	7	0	0
T126	0	60	0	0
T135	130709	0	0	0
T137	0	2	0	0
T139	0	4	0	0
T140	0	98	0	0
T141	0	35	0	0
T144	0	115	0	0
T181	3452	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2902	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	32	0	0
T114	22409	14	0	0
T116	39873	136	0	0
T126	0	75	0	0
T133	0	24	0	0
T135	130709	0	0	0
T137	2799	9	0	0
T140	0	96	0	0
T141	0	28	0	0
T144	0	105	0	0
T181	3452	0	0	0
T186	0	43	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2917	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	53	0	0
T114	22409	23	0	0
T116	39873	104	0	0
T125	8432	17	0	0
T126	0	100	0	0
T128	0	7	0	0
T135	130709	0	0	0
T137	0	11	0	0
T139	0	5	0	0
T140	0	129	0	0
T141	0	43	0	0
T181	3452	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2906	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	44	0	0
T114	22409	45	0	0
T116	39873	111	0	0
T125	8432	7	0	0
T126	0	72	0	0
T133	0	27	0	0
T135	130709	0	0	0
T139	0	9	0	0
T140	0	106	0	0
T141	0	25	0	0
T144	0	114	0	0
T181	3452	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2957	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	33	0	0
T114	22409	53	0	0
T116	39873	131	0	0
T125	8432	5	0	0
T126	0	86	0	0
T128	0	3	0	0
T135	130709	0	0	0
T139	0	3	0	0
T140	0	96	0	0
T141	0	24	0	0
T144	0	88	0	0
T181	3452	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2866	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	54	0	0
T114	22409	40	0	0
T116	39873	121	0	0
T125	8432	13	0	0
T126	0	73	0	0
T128	0	20	0	0
T135	130709	0	0	0
T137	0	1	0	0
T139	0	7	0	0
T140	0	112	0	0
T141	0	43	0	0
T181	3452	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2899	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	33	0	0
T114	22409	46	0	0
T116	39873	112	0	0
T126	56278	59	0	0
T128	0	19	0	0
T133	0	10	0	0
T135	130709	0	0	0
T140	0	99	0	0
T141	0	36	0	0
T144	0	127	0	0
T181	3452	0	0	0
T186	0	21	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2928	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	37	0	0
T114	22409	12	0	0
T116	39873	84	0	0
T125	8432	13	0	0
T126	0	80	0	0
T135	130709	0	0	0
T137	0	1	0	0
T139	0	5	0	0
T140	0	102	0	0
T141	0	37	0	0
T144	0	93	0	0
T181	3452	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2970	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	47	0	0
T114	22409	16	0	0
T116	39873	133	0	0
T126	56278	53	0	0
T128	0	9	0	0
T133	0	25	0	0
T135	130709	0	0	0
T139	0	2	0	0
T140	0	96	0	0
T141	0	35	0	0
T144	0	128	0	0
T181	3452	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2903	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	34	0	0
T114	22409	30	0	0
T116	39873	116	0	0
T125	8432	1	0	0
T126	0	66	0	0
T128	0	2	0	0
T135	130709	0	0	0
T137	0	4	0	0
T139	0	7	0	0
T140	0	102	0	0
T141	0	21	0	0
T181	3452	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2964	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	41	0	0
T114	22409	28	0	0
T116	39873	112	0	0
T126	0	85	0	0
T133	0	31	0	0
T135	130709	0	0	0
T137	2799	2	0	0
T140	0	94	0	0
T141	0	56	0	0
T144	0	97	0	0
T181	3452	0	0	0
T186	0	36	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2900	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	47	0	0
T114	22409	29	0	0
T116	39873	106	0	0
T126	0	86	0	0
T128	0	4	0	0
T135	130709	0	0	0
T137	2799	3	0	0
T139	0	2	0	0
T140	0	87	0	0
T141	0	47	0	0
T144	0	84	0	0
T181	3452	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2998	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	42	0	0
T114	22409	45	0	0
T116	39873	107	0	0
T125	8432	16	0	0
T126	0	83	0	0
T128	0	5	0	0
T135	130709	0	0	0
T137	0	4	0	0
T139	0	4	0	0
T140	0	142	0	0
T141	0	65	0	0
T181	3452	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2710	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	49	0	0
T114	22409	38	0	0
T116	39873	115	0	0
T125	8432	5	0	0
T126	0	70	0	0
T135	130709	0	0	0
T137	0	9	0	0
T139	0	5	0	0
T140	0	94	0	0
T141	0	10	0	0
T144	0	112	0	0
T181	3452	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2829	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	43	0	0
T114	22409	37	0	0
T116	39873	118	0	0
T125	8432	11	0	0
T126	0	72	0	0
T128	0	8	0	0
T133	0	26	0	0
T135	130709	0	0	0
T140	0	109	0	0
T141	0	18	0	0
T144	0	101	0	0
T181	3452	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	3047	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	52	0	0
T114	22409	35	0	0
T116	39873	142	0	0
T125	8432	4	0	0
T126	0	75	0	0
T128	0	15	0	0
T135	130709	0	0	0
T137	0	3	0	0
T140	0	103	0	0
T141	0	26	0	0
T144	0	99	0	0
T181	3452	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2835	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	45	0	0
T114	22409	43	0	0
T116	39873	105	0	0
T125	8432	1	0	0
T126	0	85	0	0
T128	0	1	0	0
T135	130709	0	0	0
T139	0	5	0	0
T140	0	103	0	0
T141	0	40	0	0
T144	0	113	0	0
T181	3452	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2998	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	49	0	0
T114	22409	24	0	0
T116	39873	98	0	0
T125	8432	18	0	0
T126	0	83	0	0
T128	0	1	0	0
T135	130709	0	0	0
T137	0	4	0	0
T139	0	2	0	0
T140	0	87	0	0
T141	0	47	0	0
T181	3452	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	3077	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	41	0	0
T114	22409	22	0	0
T116	39873	138	0	0
T126	0	106	0	0
T128	0	12	0	0
T135	130709	0	0	0
T137	2799	4	0	0
T139	0	1	0	0
T140	0	124	0	0
T141	0	13	0	0
T144	0	130	0	0
T181	3452	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29817208	2986	0	0
T38	10151	0	0	0
T40	154176	0	0	0
T81	48285	0	0	0
T99	975	0	0	0
T103	15103	49	0	0
T114	22409	26	0	0
T116	39873	128	0	0
T125	8432	6	0	0
T126	0	88	0	0
T128	0	7	0	0
T135	130709	0	0	0
T139	0	9	0	0
T140	0	116	0	0
T141	0	73	0	0
T144	0	95	0	0
T181	3452	0	0	0