KEYMGR Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: 17d5a97c3b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 40.200s 5.861ms 49 50 98.00
V1 random keymgr_random 1.864m 17.679ms 47 50 94.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.230s 35.826us 5 5 100.00
V1 csr_rw keymgr_csr_rw 1.650s 128.984us 19 20 95.00
V1 csr_bit_bash keymgr_csr_bit_bash 26.460s 1.743ms 5 5 100.00
V1 csr_aliasing keymgr_csr_aliasing 15.400s 2.104ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.950s 21.251us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.650s 128.984us 19 20 95.00
keymgr_csr_aliasing 15.400s 2.104ms 5 5 100.00
V1 TOTAL 150 155 96.77
V2 cfgen_during_op keymgr_cfg_regwen 2.148m 3.057ms 49 50 98.00
V2 sideload keymgr_sideload 1.011m 5.888ms 49 50 98.00
keymgr_sideload_kmac 45.500s 3.642ms 49 50 98.00
keymgr_sideload_aes 1.091m 1.860ms 49 50 98.00
keymgr_sideload_otbn 59.740s 1.913ms 50 50 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 31.110s 2.792ms 49 50 98.00
V2 lc_disable keymgr_lc_disable 9.220s 767.097us 48 50 96.00
V2 kmac_error_response keymgr_kmac_rsp_err 1.045m 2.272ms 46 50 92.00
V2 invalid_sw_input keymgr_sw_invalid_input 1.810m 9.430ms 50 50 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 1.110m 5.268ms 50 50 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 29.440s 1.146ms 49 50 98.00
V2 stress_all keymgr_stress_all 7.090m 61.917ms 50 50 100.00
V2 intr_test keymgr_intr_test 1.000s 22.804us 50 50 100.00
V2 alert_test keymgr_alert_test 1.060s 81.621us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 4.900s 125.604us 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 4.900s 125.604us 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.230s 35.826us 5 5 100.00
keymgr_csr_rw 1.650s 128.984us 19 20 95.00
keymgr_csr_aliasing 15.400s 2.104ms 5 5 100.00
keymgr_same_csr_outstanding 4.140s 288.510us 20 20 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.230s 35.826us 5 5 100.00
keymgr_csr_rw 1.650s 128.984us 19 20 95.00
keymgr_csr_aliasing 15.400s 2.104ms 5 5 100.00
keymgr_same_csr_outstanding 4.140s 288.510us 20 20 100.00
V2 TOTAL 728 740 98.38
V2S sec_cm_additional_check keymgr_sec_cm 37.960s 2.421ms 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 37.960s 2.421ms 5 5 100.00
keymgr_tl_intg_err 13.220s 1.104ms 20 20 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 7.710s 1.287ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 7.710s 1.287ms 20 20 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 7.710s 1.287ms 20 20 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 7.710s 1.287ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 16.000s 1.934ms 20 20 100.00
V2S prim_count_check keymgr_sec_cm 37.960s 2.421ms 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 37.960s 2.421ms 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 13.220s 1.104ms 20 20 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 7.710s 1.287ms 20 20 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 2.148m 3.057ms 49 50 98.00
V2S sec_cm_reseed_config_regwen keymgr_random 1.864m 17.679ms 47 50 94.00
keymgr_csr_rw 1.650s 128.984us 19 20 95.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 1.864m 17.679ms 47 50 94.00
keymgr_csr_rw 1.650s 128.984us 19 20 95.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 1.864m 17.679ms 47 50 94.00
keymgr_csr_rw 1.650s 128.984us 19 20 95.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 9.220s 767.097us 48 50 96.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 1.110m 5.268ms 50 50 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 1.110m 5.268ms 50 50 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 1.864m 17.679ms 47 50 94.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 22.960s 2.005ms 49 50 98.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 37.960s 2.421ms 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 37.960s 2.421ms 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 37.960s 2.421ms 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 42.320s 10.278ms 49 50 98.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 9.220s 767.097us 48 50 96.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 37.960s 2.421ms 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 37.960s 2.421ms 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 37.960s 2.421ms 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 42.320s 10.278ms 49 50 98.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 42.320s 10.278ms 49 50 98.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 37.960s 2.421ms 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 42.320s 10.278ms 49 50 98.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 37.960s 2.421ms 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 42.320s 10.278ms 49 50 98.00
V2S TOTAL 163 165 98.79
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 25.480s 394.929us 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 1090 1110 98.20

Testplan Progress

Items Total Written Passing Progress
V1 7 7 4 57.14
V2 16 16 8 50.00
V2S 6 6 4 66.67
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.87 99.07 98.03 98.90 100.00 99.11 98.41 91.61

Failure Buckets

Past Results