Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3968940	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

600096

1

T1

456

T2

2106

T3

147

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4166967	1			T1	609		T2	5154		T3	270
values[0x0]	199425	1			T1	210		T2	635		T3	49
values[0x1]	202644	1			T1	205		T2	641		T3	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2700768	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1868268

1

T1

619

T2

3267

T3

191

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16774	1			T3	7		T4	6		T13	29
valid_sources[0x01]	25294	1			T4	6		T13	7		T14	2
valid_sources[0x02]	15245	1			T3	5		T4	4		T13	4
valid_sources[0x03]	14494	1			T4	3		T13	18		T15	6
valid_sources[0x04]	23454	1			T3	6		T4	2		T13	2
valid_sources[0x05]	15371	1			T4	1		T13	27		T14	3
valid_sources[0x06]	15742	1			T3	2		T4	3		T13	17
valid_sources[0x07]	15896	1			T3	2		T4	2		T13	18
valid_sources[0x08]	16996	1			T4	8		T13	9		T14	6
valid_sources[0x09]	21047	1			T4	2		T13	13		T18	9
valid_sources[0x0a]	15071	1			T4	4		T13	5		T15	11
valid_sources[0x0b]	17192	1			T3	4		T4	6		T13	13
valid_sources[0x0c]	29865	1			T4	1		T13	23		T18	11
valid_sources[0x0d]	15426	1			T13	11		T15	6		T18	2
valid_sources[0x0e]	15765	1			T3	2		T4	7		T13	42
valid_sources[0x0f]	17691	1			T3	2		T4	2		T13	17
valid_sources[0x10]	17915	1			T4	7		T13	16		T15	1
valid_sources[0x11]	15434	1			T3	6		T4	6		T13	18
valid_sources[0x12]	22366	1			T4	1		T13	5		T15	9
valid_sources[0x13]	14924	1			T3	1		T4	6		T13	15
valid_sources[0x14]	16213	1			T4	5		T13	30		T14	8
valid_sources[0x15]	21087	1			T4	2		T13	5		T14	3
valid_sources[0x16]	15200	1			T3	4		T4	5		T13	10
valid_sources[0x17]	14957	1			T3	3		T4	1		T13	3
valid_sources[0x18]	59430	1			T3	7		T4	4		T13	25
valid_sources[0x19]	15464	1			T4	4		T13	27		T15	11
valid_sources[0x1a]	20563	1			T4	4		T13	22		T14	1
valid_sources[0x1b]	23229	1			T4	5		T13	23		T15	12
valid_sources[0x1c]	16378	1			T4	2		T13	14		T14	1
valid_sources[0x1d]	14780	1			T4	3		T13	10		T14	3
valid_sources[0x1e]	29405	1			T4	5		T13	8		T15	5
valid_sources[0x1f]	15372	1			T4	5		T13	14		T14	4
valid_sources[0x20]	19698	1			T4	3		T13	17		T14	1
valid_sources[0x21]	15487	1			T13	9		T14	8		T15	1
valid_sources[0x22]	19956	1			T3	2		T4	8		T13	7
valid_sources[0x23]	14352	1			T4	4		T13	19		T14	5
valid_sources[0x24]	15481	1			T3	2		T4	6		T13	34
valid_sources[0x25]	20115	1			T4	4		T13	4		T14	5
valid_sources[0x26]	15517	1			T4	4		T13	19		T14	2
valid_sources[0x27]	15675	1			T4	3		T13	12		T14	6
valid_sources[0x28]	14953	1			T3	2		T13	16		T18	13
valid_sources[0x29]	15060	1			T3	6		T4	6		T13	5
valid_sources[0x2a]	17550	1			T3	6		T13	42		T14	1
valid_sources[0x2b]	15435	1			T3	1		T4	5		T13	15
valid_sources[0x2c]	15346	1			T4	5		T13	15		T14	2
valid_sources[0x2d]	15365	1			T3	12		T4	4		T13	11
valid_sources[0x2e]	14892	1			T3	4		T4	3		T13	3
valid_sources[0x2f]	23086	1			T3	3		T4	5		T13	11
valid_sources[0x30]	16136	1			T4	3		T13	17		T14	1
valid_sources[0x31]	15351	1			T3	1		T4	3		T13	1
valid_sources[0x32]	15526	1			T4	5		T13	23		T15	3
valid_sources[0x33]	14862	1			T3	4		T13	33		T14	1
valid_sources[0x34]	15104	1			T4	1		T13	43		T14	4
valid_sources[0x35]	16184	1			T3	4		T4	4		T13	4
valid_sources[0x36]	15421	1			T4	5		T13	19		T14	4
valid_sources[0x37]	16984	1			T4	1		T13	40		T15	5
valid_sources[0x38]	15899	1			T4	2		T13	33		T14	4
valid_sources[0x39]	14875	1			T3	1		T4	5		T13	9
valid_sources[0x3a]	15145	1			T3	3		T4	5		T13	8
valid_sources[0x3b]	14689	1			T3	8		T13	6		T15	7
valid_sources[0x3c]	110035	1			T4	5		T13	40		T16	4
valid_sources[0x3d]	14825	1			T4	2		T13	19		T14	3
valid_sources[0x3e]	19109	1			T3	3		T4	3		T15	9
valid_sources[0x3f]	15481	1			T4	4		T13	7		T15	3
valid_sources[0x40]	15992	1			T4	3		T13	14		T15	28
valid_sources[0x41]	15242	1			T3	5		T4	4		T13	19
valid_sources[0x42]	16125	1			T4	1		T13	5		T15	17
valid_sources[0x43]	16043	1			T4	6		T13	18		T14	3
valid_sources[0x44]	29980	1			T4	3		T13	30		T15	12
valid_sources[0x45]	14639	1			T3	4		T4	5		T14	6
valid_sources[0x46]	19598	1			T4	6		T13	23		T15	12
valid_sources[0x47]	15277	1			T4	3		T13	28		T14	4
valid_sources[0x48]	20743	1			T4	5		T13	23		T14	1
valid_sources[0x49]	21777	1			T3	3		T4	6		T13	21
valid_sources[0x4a]	15943	1			T4	1		T13	7		T14	4
valid_sources[0x4b]	14808	1			T13	17		T14	12		T18	10
valid_sources[0x4c]	17122	1			T4	4		T13	38		T14	6
valid_sources[0x4d]	15879	1			T4	4		T13	14		T14	1
valid_sources[0x4e]	17905	1			T4	8		T13	29		T15	6
valid_sources[0x4f]	15456	1			T3	3		T4	2		T13	3
valid_sources[0x50]	14717	1			T4	5		T13	47		T14	5
valid_sources[0x51]	19493	1			T13	22		T15	25		T18	2
valid_sources[0x52]	14863	1			T3	1		T4	5		T13	8
valid_sources[0x53]	20184	1			T13	17		T14	2		T15	7
valid_sources[0x54]	15029	1			T4	4		T13	3		T14	1
valid_sources[0x55]	14863	1			T4	4		T13	25		T15	7
valid_sources[0x56]	17596	1			T4	1		T13	19		T14	1
valid_sources[0x57]	15035	1			T4	4		T13	8		T14	4
valid_sources[0x58]	15399	1			T4	2		T13	28		T18	1
valid_sources[0x59]	16564	1			T4	3		T13	24		T18	10
valid_sources[0x5a]	15514	1			T4	4		T13	6		T14	1
valid_sources[0x5b]	14893	1			T4	7		T13	38		T18	11
valid_sources[0x5c]	15599	1			T4	2		T13	29		T14	4
valid_sources[0x5d]	18488	1			T4	4		T13	16		T18	7
valid_sources[0x5e]	14928	1			T4	3		T13	20		T15	1
valid_sources[0x5f]	15656	1			T3	2		T13	7		T18	7
valid_sources[0x60]	15975	1			T3	2		T4	6		T13	31
valid_sources[0x61]	14165	1			T4	2		T13	22		T14	1
valid_sources[0x62]	16128	1			T4	6		T13	21		T18	12
valid_sources[0x63]	15567	1			T3	3		T4	10		T13	1
valid_sources[0x64]	15614	1			T3	4		T4	3		T13	29
valid_sources[0x65]	26160	1			T2	6430		T3	5		T4	5
valid_sources[0x66]	16140	1			T3	2		T4	4		T13	8
valid_sources[0x67]	14810	1			T4	1		T13	6		T14	3
valid_sources[0x68]	15547	1			T3	1		T4	5		T13	12
valid_sources[0x69]	15290	1			T3	5		T4	2		T13	4
valid_sources[0x6a]	14740	1			T4	2		T14	5		T15	4
valid_sources[0x6b]	15679	1			T3	1		T4	2		T13	26
valid_sources[0x6c]	14729	1			T4	4		T13	14		T14	1
valid_sources[0x6d]	15829	1			T3	2		T4	5		T13	29
valid_sources[0x6e]	14747	1			T4	4		T13	3		T14	13
valid_sources[0x6f]	16883	1			T4	8		T13	28		T14	3
valid_sources[0x70]	26314	1			T4	3		T13	10		T14	1
valid_sources[0x71]	16281	1			T4	3		T13	9		T14	2
valid_sources[0x72]	21797	1			T4	7		T13	14		T14	5
valid_sources[0x73]	16158	1			T3	3		T4	2		T13	8
valid_sources[0x74]	15965	1			T3	1		T4	1		T13	17
valid_sources[0x75]	17897	1			T3	5		T4	3		T13	19
valid_sources[0x76]	15611	1			T4	3		T13	5		T16	10
valid_sources[0x77]	22416	1			T3	2		T4	6		T13	34
valid_sources[0x78]	16638	1			T4	5		T13	28		T14	6
valid_sources[0x79]	14596	1			T3	3		T4	2		T13	1
valid_sources[0x7a]	16030	1			T4	5		T13	2		T18	11
valid_sources[0x7b]	15689	1			T13	4		T14	2		T16	4
valid_sources[0x7c]	15157	1			T4	5		T13	12		T14	3
valid_sources[0x7d]	14965	1			T4	4		T13	15		T15	14
valid_sources[0x7e]	15461	1			T3	5		T4	5		T13	16
valid_sources[0x7f]	15394	1			T4	4		T13	12		T18	11
valid_sources[0x80]	17535	1			T4	3		T13	22		T15	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

323053

1

T1

150

T2

1405

T3

115

values[0x0]

all_enables

biggest_size

145594

1

T1

162

T2

382

T3

22

values[0x1]

all_enables

biggest_size

131449

1

T1

144

T2

319

T3

10