Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4049669	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

624581

1

T1

284

T2

2271

T3

263

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4273706	1			T1	686		T2	2575		T3	492
values[0x0]	198551	1			T1	117		T2	581		T3	138
values[0x1]	201993	1			T1	107		T2	783		T3	129

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2758892	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1915358

1

T1

446

T2

2730

T3

393

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10324	1			T1	2		T2	11		T12	9
valid_sources[0x01]	16368	1			T1	7		T2	19		T3	1
valid_sources[0x02]	13844	1			T1	1		T2	16		T12	3
valid_sources[0x03]	10473	1			T1	4		T2	22		T3	1
valid_sources[0x04]	11895	1			T1	6		T2	20		T3	2
valid_sources[0x05]	11544	1			T1	3		T2	12		T3	1
valid_sources[0x06]	10700	1			T1	7		T2	20		T12	2
valid_sources[0x07]	10922	1			T1	2		T2	16		T3	1
valid_sources[0x08]	10132	1			T1	1		T2	20		T12	10
valid_sources[0x09]	10720	1			T1	8		T2	19		T3	6
valid_sources[0x0a]	10505	1			T1	3		T2	7		T3	3
valid_sources[0x0b]	11260	1			T1	2		T2	20		T12	22
valid_sources[0x0c]	10881	1			T1	3		T2	24		T3	6
valid_sources[0x0d]	10944	1			T1	6		T2	15		T3	4
valid_sources[0x0e]	11180	1			T1	4		T2	18		T3	2
valid_sources[0x0f]	14117	1			T2	14		T3	4		T12	70
valid_sources[0x10]	10776	1			T1	4		T2	13		T3	5
valid_sources[0x11]	15536	1			T1	2		T2	20		T3	2
valid_sources[0x12]	11053	1			T1	3		T2	22		T12	15
valid_sources[0x13]	14661	1			T1	9		T2	14		T3	2
valid_sources[0x14]	12349	1			T1	1		T2	16		T3	4
valid_sources[0x15]	11277	1			T1	2		T2	26		T3	5
valid_sources[0x16]	12413	1			T1	8		T2	14		T12	16
valid_sources[0x17]	55664	1			T1	6		T2	15		T3	2
valid_sources[0x18]	11690	1			T1	3		T2	20		T3	3
valid_sources[0x19]	11433	1			T1	4		T2	17		T3	3
valid_sources[0x1a]	13635	1			T1	1		T2	18		T12	16
valid_sources[0x1b]	11683	1			T1	1		T2	20		T3	2
valid_sources[0x1c]	13477	1			T1	5		T2	14		T3	6
valid_sources[0x1d]	23238	1			T1	3		T2	22		T3	6
valid_sources[0x1e]	13661	1			T1	11		T2	13		T3	4
valid_sources[0x1f]	68902	1			T1	3		T2	12		T3	5
valid_sources[0x20]	12064	1			T1	2		T2	11		T3	3
valid_sources[0x21]	12458	1			T1	7		T2	15		T3	1
valid_sources[0x22]	10972	1			T1	2		T2	15		T3	2
valid_sources[0x23]	14368	1			T1	1		T2	18		T3	3
valid_sources[0x24]	11105	1			T1	5		T2	17		T3	1
valid_sources[0x25]	11052	1			T1	2		T2	20		T3	5
valid_sources[0x26]	11221	1			T1	2		T2	17		T3	7
valid_sources[0x27]	11133	1			T1	4		T2	16		T3	3
valid_sources[0x28]	10597	1			T1	4		T2	17		T3	6
valid_sources[0x29]	13102	1			T1	4		T2	16		T3	2
valid_sources[0x2a]	10723	1			T1	7		T2	9		T3	2
valid_sources[0x2b]	10682	1			T1	5		T2	18		T12	24
valid_sources[0x2c]	10585	1			T1	3		T2	11		T3	6
valid_sources[0x2d]	13018	1			T1	7		T2	15		T3	6
valid_sources[0x2e]	11922	1			T1	2		T2	16		T3	6
valid_sources[0x2f]	17928	1			T1	3		T2	17		T12	35
valid_sources[0x30]	20407	1			T1	1		T2	15		T3	2
valid_sources[0x31]	11432	1			T1	4		T2	13		T3	3
valid_sources[0x32]	68763	1			T1	2		T2	19		T3	2
valid_sources[0x33]	11189	1			T2	13		T3	2		T12	19
valid_sources[0x34]	12043	1			T1	7		T2	17		T3	2
valid_sources[0x35]	31798	1			T1	3		T2	5		T3	3
valid_sources[0x36]	11504	1			T1	1		T2	20		T12	28
valid_sources[0x37]	13036	1			T1	5		T2	11		T3	1
valid_sources[0x38]	10503	1			T1	3		T2	15		T12	43
valid_sources[0x39]	23508	1			T1	2		T2	11		T3	2
valid_sources[0x3a]	11191	1			T1	2		T2	14		T3	11
valid_sources[0x3b]	110576	1			T1	4		T2	14		T3	4
valid_sources[0x3c]	13054	1			T1	2		T2	14		T12	47
valid_sources[0x3d]	12239	1			T1	1		T2	16		T3	3
valid_sources[0x3e]	10882	1			T1	3		T2	15		T3	7
valid_sources[0x3f]	17258	1			T1	4		T2	15		T12	24
valid_sources[0x40]	233638	1			T1	1		T2	15		T3	2
valid_sources[0x41]	13835	1			T1	2		T2	15		T3	4
valid_sources[0x42]	11023	1			T1	2		T2	12		T3	1
valid_sources[0x43]	16486	1			T1	5		T2	12		T3	1
valid_sources[0x44]	13890	1			T1	6		T2	14		T3	7
valid_sources[0x45]	10977	1			T1	7		T2	13		T3	4
valid_sources[0x46]	24435	1			T1	3		T2	22		T3	4
valid_sources[0x47]	11626	1			T1	5		T2	21		T3	5
valid_sources[0x48]	11439	1			T1	7		T2	13		T3	4
valid_sources[0x49]	12837	1			T1	7		T2	15		T3	1
valid_sources[0x4a]	12793	1			T2	14		T3	3		T12	4
valid_sources[0x4b]	85065	1			T1	1		T2	9		T12	29
valid_sources[0x4c]	12091	1			T1	3		T2	11		T3	4
valid_sources[0x4d]	14697	1			T2	15		T3	6		T12	20
valid_sources[0x4e]	11234	1			T1	1		T2	12		T3	6
valid_sources[0x4f]	11843	1			T1	2		T2	18		T3	1
valid_sources[0x50]	16887	1			T1	5		T2	16		T3	1
valid_sources[0x51]	13265	1			T1	4		T2	8		T3	6
valid_sources[0x52]	12402	1			T1	3		T2	13		T3	7
valid_sources[0x53]	13639	1			T1	1		T2	17		T3	8
valid_sources[0x54]	10832	1			T1	3		T2	16		T12	28
valid_sources[0x55]	11265	1			T1	4		T2	13		T3	1
valid_sources[0x56]	14423	1			T1	4		T2	16		T3	1
valid_sources[0x57]	12190	1			T1	2		T2	10		T12	1
valid_sources[0x58]	12166	1			T1	1		T2	21		T3	3
valid_sources[0x59]	11182	1			T1	5		T2	14		T3	1
valid_sources[0x5a]	12052	1			T1	1		T2	9		T3	1
valid_sources[0x5b]	10793	1			T1	6		T2	12		T3	1
valid_sources[0x5c]	29628	1			T1	2		T2	12		T3	2
valid_sources[0x5d]	11811	1			T1	3		T2	24		T3	6
valid_sources[0x5e]	15356	1			T1	7		T2	13		T3	7
valid_sources[0x5f]	10623	1			T1	6		T2	17		T3	4
valid_sources[0x60]	13316	1			T1	2		T2	14		T3	1
valid_sources[0x61]	23610	1			T1	4		T2	15		T3	3
valid_sources[0x62]	27420	1			T1	3		T2	15		T3	3
valid_sources[0x63]	17306	1			T1	3		T2	15		T3	3
valid_sources[0x64]	14159	1			T1	4		T2	17		T3	7
valid_sources[0x65]	29814	1			T1	3		T2	22		T3	1
valid_sources[0x66]	20591	1			T1	2		T2	14		T3	2
valid_sources[0x67]	10988	1			T1	2		T2	18		T3	4
valid_sources[0x68]	11890	1			T1	2		T2	18		T3	10
valid_sources[0x69]	15354	1			T1	4		T2	10		T12	38
valid_sources[0x6a]	11941	1			T1	2		T2	10		T3	3
valid_sources[0x6b]	11520	1			T1	5		T2	22		T3	4
valid_sources[0x6c]	12755	1			T1	3		T2	15		T3	2
valid_sources[0x6d]	16956	1			T1	3		T2	18		T3	3
valid_sources[0x6e]	13285	1			T1	3		T2	17		T3	2
valid_sources[0x6f]	23768	1			T1	5		T2	13		T3	4
valid_sources[0x70]	38940	1			T1	2		T2	12		T12	34
valid_sources[0x71]	10619	1			T1	1		T2	15		T3	4
valid_sources[0x72]	11078	1			T1	4		T2	14		T3	1
valid_sources[0x73]	12047	1			T1	1		T2	16		T3	6
valid_sources[0x74]	11508	1			T1	2		T2	13		T3	4
valid_sources[0x75]	11205	1			T1	2		T2	22		T12	21
valid_sources[0x76]	11460	1			T1	3		T2	21		T3	5
valid_sources[0x77]	10877	1			T1	7		T2	11		T3	3
valid_sources[0x78]	12703	1			T1	2		T2	16		T3	1
valid_sources[0x79]	10417	1			T1	4		T2	21		T3	3
valid_sources[0x7a]	11429	1			T1	8		T2	19		T3	4
valid_sources[0x7b]	13400	1			T1	5		T2	15		T3	2
valid_sources[0x7c]	29873	1			T1	2		T2	18		T3	5
valid_sources[0x7d]	20435	1			T1	5		T2	16		T3	5
valid_sources[0x7e]	11777	1			T1	4		T2	15		T3	5
valid_sources[0x7f]	12106	1			T1	4		T2	14		T12	10
valid_sources[0x80]	10896	1			T1	1		T2	8		T12	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

348511

1

T1

142

T2

1212

T3

73

values[0x0]

all_enables

biggest_size

144898

1

T1

82

T2

507

T3

100

values[0x1]

all_enables

biggest_size

131172

1

T1

60

T2

552

T3

90