Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.93	95.95	97.85	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	29748186	19279	0	0
attest_sw_binding_0_rd_A	29748186	2404	0	0
attest_sw_binding_1_rd_A	29748186	2585	0	0
attest_sw_binding_2_rd_A	29748186	2327	0	0
attest_sw_binding_3_rd_A	29748186	2448	0	0
attest_sw_binding_4_rd_A	29748186	2506	0	0
attest_sw_binding_5_rd_A	29748186	2417	0	0
attest_sw_binding_6_rd_A	29748186	2576	0	0
attest_sw_binding_7_rd_A	29748186	2482	0	0
intr_enable_rd_A	29748186	2989	0	0
key_version_rd_A	29748186	2546	0	0
max_creator_key_ver_regwen_rd_A	29748186	2310	0	0
max_owner_int_key_ver_regwen_rd_A	29748186	2334	0	0
max_owner_key_ver_regwen_rd_A	29748186	2457	0	0
reseed_interval_regwen_rd_A	29748186	2335	0	0
salt_0_rd_A	29748186	2294	0	0
salt_1_rd_A	29748186	2432	0	0
salt_2_rd_A	29748186	2342	0	0
salt_3_rd_A	29748186	2376	0	0
salt_4_rd_A	29748186	2472	0	0
salt_5_rd_A	29748186	2484	0	0
salt_6_rd_A	29748186	2507	0	0
salt_7_rd_A	29748186	2565	0	0
sealing_sw_binding_0_rd_A	29748186	2459	0	0
sealing_sw_binding_1_rd_A	29748186	2450	0	0
sealing_sw_binding_2_rd_A	29748186	2483	0	0
sealing_sw_binding_3_rd_A	29748186	2597	0	0
sealing_sw_binding_4_rd_A	29748186	2494	0	0
sealing_sw_binding_5_rd_A	29748186	2499	0	0
sealing_sw_binding_6_rd_A	29748186	2369	0	0
sealing_sw_binding_7_rd_A	29748186	2455	0	0
sideload_clear_rd_A	29748186	2441	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	19279	0	0
T2	11843	429	0	0
T3	9342	0	0	0
T12	17920	0	0	0
T13	25569	0	0	0
T14	14310	0	0	0
T15	7323	0	0	0
T16	10738	0	0	0
T17	4774	0	0	0
T18	14421	0	0	0
T31	34840	0	0	0
T89	0	8	0	0
T90	0	810	0	0
T105	0	620	0	0
T106	0	716	0	0
T107	0	37	0	0
T108	0	130	0	0
T109	0	230	0	0
T110	0	245	0	0
T170	0	2	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2404	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	23	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	28	0	0
T123	0	142	0	0
T129	0	230	0	0
T133	0	46	0	0
T146	0	32	0	0
T167	0	36	0	0
T170	0	19	0	0
T171	0	2	0	0
T172	0	12	0	0
T173	5217	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2585	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	40	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	22	0	0
T123	0	148	0	0
T129	0	241	0	0
T133	0	47	0	0
T146	0	45	0	0
T167	0	25	0	0
T171	0	1	0	0
T172	0	16	0	0
T173	5217	0	0	0
T174	0	16	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2327	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	17	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	29	0	0
T123	0	135	0	0
T129	0	261	0	0
T133	0	18	0	0
T146	0	26	0	0
T167	0	38	0	0
T170	0	1	0	0
T171	0	9	0	0
T172	0	6	0	0
T173	5217	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2448	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	17	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	32	0	0
T123	0	124	0	0
T129	0	245	0	0
T133	0	48	0	0
T146	0	26	0	0
T167	0	51	0	0
T171	0	7	0	0
T172	0	9	0	0
T173	5217	0	0	0
T174	0	4	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2506	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	30	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	26	0	0
T123	0	158	0	0
T129	0	261	0	0
T133	0	27	0	0
T146	0	42	0	0
T167	0	30	0	0
T170	0	4	0	0
T171	0	3	0	0
T173	5217	0	0	0
T174	0	8	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2417	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	23	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	24	0	0
T123	0	111	0	0
T129	0	268	0	0
T133	0	50	0	0
T146	0	40	0	0
T167	0	47	0	0
T170	0	3	0	0
T171	0	7	0	0
T173	5217	0	0	0
T174	0	3	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2576	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	12	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	26	0	0
T123	0	143	0	0
T129	0	274	0	0
T133	0	84	0	0
T146	0	16	0	0
T167	0	29	0	0
T170	0	7	0	0
T171	0	2	0	0
T173	5217	0	0	0
T174	0	10	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2482	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	18	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	29	0	0
T123	0	171	0	0
T129	0	241	0	0
T133	0	29	0	0
T134	0	57	0	0
T146	0	38	0	0
T167	0	12	0	0
T171	0	6	0	0
T172	0	8	0	0
T173	5217	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2989	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	30	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	19	0	0
T123	0	93	0	0
T129	0	230	0	0
T130	0	13	0	0
T131	0	14	0	0
T171	0	1	0	0
T173	5217	0	0	0
T175	0	10	0	0
T176	0	18	0	0
T177	0	9	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2546	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	16	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	20	0	0
T123	0	112	0	0
T129	0	293	0	0
T133	0	55	0	0
T146	0	38	0	0
T167	0	36	0	0
T170	0	2	0	0
T171	0	3	0	0
T172	0	8	0	0
T173	5217	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2310	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	21	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	30	0	0
T123	0	110	0	0
T129	0	215	0	0
T133	0	41	0	0
T146	0	32	0	0
T167	0	39	0	0
T170	0	9	0	0
T171	0	6	0	0
T172	0	2	0	0
T173	5217	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2334	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	23	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	35	0	0
T123	0	146	0	0
T129	0	227	0	0
T133	0	45	0	0
T146	0	52	0	0
T167	0	27	0	0
T170	0	9	0	0
T171	0	6	0	0
T172	0	11	0	0
T173	5217	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2457	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	28	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	21	0	0
T123	0	150	0	0
T129	0	267	0	0
T133	0	45	0	0
T134	0	56	0	0
T146	0	38	0	0
T167	0	18	0	0
T170	0	9	0	0
T171	0	9	0	0
T173	5217	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2335	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	32	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	25	0	0
T123	0	171	0	0
T129	0	226	0	0
T133	0	14	0	0
T146	0	39	0	0
T167	0	41	0	0
T170	0	6	0	0
T171	0	2	0	0
T172	0	10	0	0
T173	5217	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2294	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	36	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	33	0	0
T123	0	109	0	0
T129	0	237	0	0
T133	0	45	0	0
T146	0	32	0	0
T167	0	26	0	0
T171	0	2	0	0
T172	0	10	0	0
T173	5217	0	0	0
T174	0	2	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2432	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	32	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	36	0	0
T123	0	138	0	0
T129	0	219	0	0
T133	0	43	0	0
T146	0	43	0	0
T167	0	32	0	0
T170	0	5	0	0
T171	0	3	0	0
T173	5217	0	0	0
T174	0	3	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2342	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	11	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	12	0	0
T123	0	149	0	0
T129	0	232	0	0
T133	0	30	0	0
T134	0	73	0	0
T146	0	36	0	0
T167	0	35	0	0
T170	0	6	0	0
T171	0	6	0	0
T173	5217	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2376	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	44	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	22	0	0
T123	0	130	0	0
T129	0	231	0	0
T133	0	34	0	0
T146	0	26	0	0
T167	0	51	0	0
T170	0	9	0	0
T171	0	6	0	0
T173	5217	0	0	0
T174	0	7	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2472	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	33	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	28	0	0
T123	0	171	0	0
T129	0	247	0	0
T133	0	42	0	0
T146	0	27	0	0
T167	0	28	0	0
T170	0	20	0	0
T171	0	7	0	0
T172	0	2	0	0
T173	5217	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2484	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	18	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	34	0	0
T123	0	150	0	0
T129	0	243	0	0
T133	0	5	0	0
T146	0	45	0	0
T167	0	34	0	0
T170	0	10	0	0
T171	0	4	0	0
T173	5217	0	0	0
T174	0	9	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2507	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	23	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	31	0	0
T123	0	113	0	0
T129	0	257	0	0
T133	0	39	0	0
T146	0	42	0	0
T167	0	41	0	0
T170	0	15	0	0
T171	0	5	0	0
T173	5217	0	0	0
T174	0	4	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2565	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	18	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	21	0	0
T123	0	138	0	0
T129	0	222	0	0
T133	0	48	0	0
T146	0	27	0	0
T167	0	22	0	0
T170	0	2	0	0
T171	0	6	0	0
T173	5217	0	0	0
T174	0	8	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2459	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	24	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	27	0	0
T123	0	102	0	0
T129	0	260	0	0
T133	0	49	0	0
T146	0	46	0	0
T167	0	41	0	0
T170	0	1	0	0
T171	0	10	0	0
T173	5217	0	0	0
T174	0	2	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2450	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	27	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	26	0	0
T123	0	149	0	0
T129	0	273	0	0
T133	0	52	0	0
T134	0	55	0	0
T146	0	29	0	0
T167	0	31	0	0
T170	0	5	0	0
T171	0	4	0	0
T173	5217	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2483	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	19	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	29	0	0
T123	0	122	0	0
T129	0	235	0	0
T133	0	17	0	0
T146	0	30	0	0
T167	0	29	0	0
T170	0	2	0	0
T171	0	2	0	0
T172	0	7	0	0
T173	5217	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2597	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	26	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	28	0	0
T123	0	123	0	0
T129	0	236	0	0
T133	0	10	0	0
T134	0	62	0	0
T146	0	31	0	0
T167	0	21	0	0
T170	0	8	0	0
T172	0	26	0	0
T173	5217	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2494	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	21	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	27	0	0
T123	0	144	0	0
T129	0	307	0	0
T133	0	70	0	0
T146	0	52	0	0
T167	0	30	0	0
T170	0	2	0	0
T171	0	4	0	0
T172	0	21	0	0
T173	5217	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2499	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	17	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	28	0	0
T123	0	134	0	0
T129	0	231	0	0
T133	0	73	0	0
T134	0	55	0	0
T146	0	33	0	0
T167	0	33	0	0
T170	0	4	0	0
T173	5217	0	0	0
T178	0	13	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2369	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	11	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	30	0	0
T123	0	125	0	0
T129	0	276	0	0
T133	0	37	0	0
T146	0	55	0	0
T167	0	38	0	0
T170	0	4	0	0
T171	0	3	0	0
T173	5217	0	0	0
T174	0	1	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2455	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	13	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	44	0	0
T123	0	133	0	0
T129	0	245	0	0
T133	0	79	0	0
T146	0	37	0	0
T167	0	34	0	0
T170	0	6	0	0
T171	0	3	0	0
T173	5217	0	0	0
T174	0	1	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29748186	2441	0	0
T23	12894	0	0	0
T47	84331	0	0	0
T50	40420	0	0	0
T89	6123	7	0	0
T90	14760	0	0	0
T93	35395	0	0	0
T94	5184	0	0	0
T95	6364	0	0	0
T96	11847	0	0	0
T100	0	32	0	0
T123	0	82	0	0
T129	0	214	0	0
T133	0	42	0	0
T146	0	19	0	0
T167	0	48	0	0
T170	0	15	0	0
T171	0	2	0	0
T173	5217	0	0	0
T174	0	2	0	0