Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3846436	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

558333

1

T1

206

T2

9

T3

862

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4020781	1			T1	1005		T2	1		T3	973
values[0x0]	189937	1			T1	91		T2	19		T3	342
values[0x1]	194051	1			T1	88		T2	17		T3	328

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2616863	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1787906

1

T1

520

T2

14

T3

1040

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13631	1			T1	4		T3	3		T14	114
valid_sources[0x01]	13778	1			T1	1		T3	11		T14	152
valid_sources[0x02]	13134	1			T1	7		T3	7		T14	144
valid_sources[0x03]	14041	1			T1	3		T3	3		T14	174
valid_sources[0x04]	13148	1			T1	10		T3	1		T14	185
valid_sources[0x05]	13445	1			T1	4		T3	4		T14	141
valid_sources[0x06]	13907	1			T1	8		T3	3		T14	152
valid_sources[0x07]	14724	1			T1	2		T3	6		T14	155
valid_sources[0x08]	13261	1			T1	3		T3	6		T14	173
valid_sources[0x09]	12220	1			T1	1		T3	11		T14	127
valid_sources[0x0a]	13240	1			T1	7		T3	6		T14	130
valid_sources[0x0b]	13344	1			T1	9		T3	2		T14	197
valid_sources[0x0c]	12896	1			T1	4		T3	9		T14	125
valid_sources[0x0d]	13587	1			T1	2		T3	18		T14	110
valid_sources[0x0e]	12386	1			T1	4		T14	154		T17	6
valid_sources[0x0f]	26192	1			T1	3		T3	15		T14	154
valid_sources[0x10]	12726	1			T1	1		T3	3		T14	139
valid_sources[0x11]	21007	1			T1	9		T3	3		T14	172
valid_sources[0x12]	13093	1			T1	7		T3	1		T14	152
valid_sources[0x13]	12860	1			T1	5		T2	1		T3	6
valid_sources[0x14]	12525	1			T1	7		T3	4		T14	116
valid_sources[0x15]	13146	1			T1	1		T3	3		T14	140
valid_sources[0x16]	14268	1			T1	2		T3	4		T14	157
valid_sources[0x17]	13480	1			T1	7		T3	14		T14	174
valid_sources[0x18]	16275	1			T1	2		T3	13		T14	91
valid_sources[0x19]	20772	1			T1	2		T14	107		T17	5
valid_sources[0x1a]	13506	1			T1	3		T3	13		T14	131
valid_sources[0x1b]	12870	1			T1	2		T3	3		T14	110
valid_sources[0x1c]	28813	1			T1	2		T3	9		T14	153
valid_sources[0x1d]	12565	1			T1	5		T14	114		T16	1
valid_sources[0x1e]	12633	1			T1	2		T3	3		T14	164
valid_sources[0x1f]	18704	1			T3	4		T14	179		T17	7
valid_sources[0x20]	12421	1			T1	9		T3	1		T14	166
valid_sources[0x21]	46619	1			T1	5		T14	206		T17	6
valid_sources[0x22]	26732	1			T1	4		T3	12		T14	151
valid_sources[0x23]	12852	1			T1	6		T3	2		T14	163
valid_sources[0x24]	14001	1			T1	6		T2	2		T14	162
valid_sources[0x25]	15025	1			T1	1		T3	9		T14	180
valid_sources[0x26]	13411	1			T1	9		T3	10		T14	174
valid_sources[0x27]	19667	1			T14	205		T16	1		T17	6
valid_sources[0x28]	13041	1			T1	2		T3	19		T14	160
valid_sources[0x29]	38368	1			T1	9		T3	4		T14	143
valid_sources[0x2a]	61852	1			T3	4		T14	162		T17	9
valid_sources[0x2b]	12596	1			T1	7		T3	12		T14	113
valid_sources[0x2c]	13234	1			T1	6		T3	8		T14	185
valid_sources[0x2d]	12360	1			T1	6		T14	179		T17	6
valid_sources[0x2e]	12857	1			T1	6		T3	3		T14	107
valid_sources[0x2f]	12570	1			T3	6		T14	139		T16	1
valid_sources[0x30]	25697	1			T1	4		T3	1		T14	154
valid_sources[0x31]	14405	1			T1	4		T3	3		T14	158
valid_sources[0x32]	13136	1			T1	9		T3	7		T14	157
valid_sources[0x33]	24124	1			T1	1		T3	2		T14	120
valid_sources[0x34]	14362	1			T1	1		T3	3		T14	183
valid_sources[0x35]	13021	1			T1	1		T3	4		T14	191
valid_sources[0x36]	12622	1			T3	2		T14	148		T17	6
valid_sources[0x37]	14201	1			T1	6		T14	143		T17	6
valid_sources[0x38]	13792	1			T1	18		T3	5		T14	137
valid_sources[0x39]	19604	1			T1	5		T14	137		T16	1
valid_sources[0x3a]	20721	1			T1	1		T3	2		T14	168
valid_sources[0x3b]	13020	1			T1	13		T3	12		T14	129
valid_sources[0x3c]	12962	1			T1	4		T3	10		T14	138
valid_sources[0x3d]	76925	1			T1	4		T3	16		T14	113
valid_sources[0x3e]	12556	1			T1	5		T3	19		T14	178
valid_sources[0x3f]	13017	1			T1	7		T3	11		T14	145
valid_sources[0x40]	15376	1			T1	5		T3	5		T14	193
valid_sources[0x41]	25547	1			T1	7		T3	11		T14	163
valid_sources[0x42]	13229	1			T1	9		T3	1		T14	132
valid_sources[0x43]	13671	1			T1	2		T3	1		T14	157
valid_sources[0x44]	14009	1			T1	6		T3	11		T14	182
valid_sources[0x45]	14821	1			T1	4		T2	2		T3	11
valid_sources[0x46]	13725	1			T1	8		T3	37		T14	136
valid_sources[0x47]	13069	1			T2	2		T3	1		T14	164
valid_sources[0x48]	13997	1			T1	6		T3	5		T14	191
valid_sources[0x49]	14668	1			T1	9		T3	1		T14	141
valid_sources[0x4a]	13811	1			T2	1		T3	6		T14	193
valid_sources[0x4b]	21883	1			T1	2		T3	9		T14	153
valid_sources[0x4c]	17516	1			T1	4		T3	9		T14	143
valid_sources[0x4d]	17690	1			T1	3		T3	5		T14	139
valid_sources[0x4e]	13732	1			T1	2		T3	10		T14	163
valid_sources[0x4f]	13157	1			T1	2		T2	1		T3	20
valid_sources[0x50]	14869	1			T1	2		T3	5		T14	163
valid_sources[0x51]	13538	1			T1	3		T3	8		T14	152
valid_sources[0x52]	14059	1			T1	3		T3	8		T14	137
valid_sources[0x53]	12659	1			T1	5		T3	2		T14	120
valid_sources[0x54]	29399	1			T3	3		T14	141		T16	2
valid_sources[0x55]	13109	1			T1	6		T3	14		T14	153
valid_sources[0x56]	15018	1			T1	4		T2	1		T3	1
valid_sources[0x57]	13005	1			T1	6		T3	13		T14	160
valid_sources[0x58]	15367	1			T1	5		T3	8		T14	176
valid_sources[0x59]	13176	1			T1	15		T3	11		T14	155
valid_sources[0x5a]	13270	1			T2	1		T3	3		T14	121
valid_sources[0x5b]	12333	1			T1	2		T3	7		T14	160
valid_sources[0x5c]	16414	1			T1	1		T14	177		T17	8
valid_sources[0x5d]	29328	1			T1	9		T3	8		T14	137
valid_sources[0x5e]	27855	1			T1	1		T2	1		T3	8
valid_sources[0x5f]	52818	1			T1	3		T3	4		T14	162
valid_sources[0x60]	14065	1			T1	3		T3	8		T14	209
valid_sources[0x61]	13418	1			T1	8		T3	2		T14	151
valid_sources[0x62]	13328	1			T1	4		T3	17		T14	184
valid_sources[0x63]	15425	1			T1	5		T3	1		T14	193
valid_sources[0x64]	35102	1			T1	4		T14	122		T17	14
valid_sources[0x65]	13582	1			T1	15		T3	17		T14	106
valid_sources[0x66]	20938	1			T1	9		T3	14		T14	186
valid_sources[0x67]	12565	1			T3	6		T14	136		T17	7
valid_sources[0x68]	15810	1			T1	1		T14	121		T16	3
valid_sources[0x69]	16803	1			T2	2		T3	7		T14	134
valid_sources[0x6a]	13652	1			T1	6		T3	9		T14	236
valid_sources[0x6b]	15558	1			T1	1		T3	18		T14	145
valid_sources[0x6c]	13328	1			T1	4		T3	4		T14	123
valid_sources[0x6d]	12266	1			T1	1		T3	11		T14	164
valid_sources[0x6e]	12659	1			T1	6		T14	151		T17	7
valid_sources[0x6f]	29468	1			T1	3		T2	3		T3	12
valid_sources[0x70]	12860	1			T3	5		T14	132		T16	1
valid_sources[0x71]	19493	1			T1	9		T3	5		T14	181
valid_sources[0x72]	14355	1			T1	7		T2	1		T3	1
valid_sources[0x73]	13394	1			T1	2		T3	9		T14	110
valid_sources[0x74]	22550	1			T1	5		T3	5		T14	145
valid_sources[0x75]	12740	1			T3	7		T14	178		T17	5
valid_sources[0x76]	13778	1			T1	7		T14	128		T17	9
valid_sources[0x77]	12705	1			T1	8		T14	149		T16	1
valid_sources[0x78]	12873	1			T1	4		T3	13		T14	186
valid_sources[0x79]	13223	1			T1	1		T3	12		T14	161
valid_sources[0x7a]	15897	1			T1	2		T3	6		T14	167
valid_sources[0x7b]	13316	1			T1	5		T3	4		T14	217
valid_sources[0x7c]	16724	1			T1	9		T3	13		T14	140
valid_sources[0x7d]	13538	1			T1	3		T3	9		T14	137
valid_sources[0x7e]	13323	1			T1	4		T2	1		T3	13
valid_sources[0x7f]	12653	1			T1	2		T3	6		T14	143
valid_sources[0x80]	12667	1			T1	5		T3	8		T14	164

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

299015

1

T1

83

T3

383

T4

157

values[0x0]

all_enables

biggest_size

136260

1

T1

64

T2

7

T3

249

values[0x1]

all_enables

biggest_size

123058

1

T1

59

T2

2

T3

230