Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	28989889	21066	0	0
attest_sw_binding_0_rd_A	28989889	2501	0	0
attest_sw_binding_1_rd_A	28989889	2396	0	0
attest_sw_binding_2_rd_A	28989889	2275	0	0
attest_sw_binding_3_rd_A	28989889	2424	0	0
attest_sw_binding_4_rd_A	28989889	2264	0	0
attest_sw_binding_5_rd_A	28989889	2501	0	0
attest_sw_binding_6_rd_A	28989889	2492	0	0
attest_sw_binding_7_rd_A	28989889	2456	0	0
intr_enable_rd_A	28989889	2776	0	0
key_version_rd_A	28989889	2382	0	0
max_creator_key_ver_regwen_rd_A	28989889	2440	0	0
max_owner_int_key_ver_regwen_rd_A	28989889	2433	0	0
max_owner_key_ver_regwen_rd_A	28989889	2434	0	0
reseed_interval_regwen_rd_A	28989889	2339	0	0
salt_0_rd_A	28989889	2293	0	0
salt_1_rd_A	28989889	2485	0	0
salt_2_rd_A	28989889	2356	0	0
salt_3_rd_A	28989889	2497	0	0
salt_4_rd_A	28989889	2402	0	0
salt_5_rd_A	28989889	2425	0	0
salt_6_rd_A	28989889	2386	0	0
salt_7_rd_A	28989889	2467	0	0
sealing_sw_binding_0_rd_A	28989889	2344	0	0
sealing_sw_binding_1_rd_A	28989889	2427	0	0
sealing_sw_binding_2_rd_A	28989889	2434	0	0
sealing_sw_binding_3_rd_A	28989889	2414	0	0
sealing_sw_binding_4_rd_A	28989889	2496	0	0
sealing_sw_binding_5_rd_A	28989889	2391	0	0
sealing_sw_binding_6_rd_A	28989889	2526	0	0
sealing_sw_binding_7_rd_A	28989889	2405	0	0
sideload_clear_rd_A	28989889	2344	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	21066	0	0
T6	543081	0	0	0
T25	17991	0	0	0
T28	35162	0	0	0
T37	5431	0	0	0
T42	26034	1958	0	0
T47	5208	0	0	0
T60	121911	0	0	0
T73	0	2222	0	0
T109	0	941	0	0
T110	0	1008	0	0
T123	0	1286	0	0
T125	0	1060	0	0
T127	6032	0	0	0
T128	13324	0	0	0
T129	1810	0	0	0
T132	0	925	0	0
T135	0	251	0	0
T184	0	1	0	0
T185	0	1	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2501	0	0
T115	10114	26	0	0
T117	42474	220	0	0
T136	6269	1	0	0
T142	10253	59	0	0
T160	23114	233	0	0
T176	17600	50	0	0
T186	3332	12	0	0
T187	13625	3	0	0
T188	128628	515	0	0
T189	12522	5	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2396	0	0
T115	10114	29	0	0
T117	42474	205	0	0
T136	6269	13	0	0
T142	10253	23	0	0
T160	23114	283	0	0
T176	17600	32	0	0
T187	13625	8	0	0
T188	128628	494	0	0
T189	12522	5	0	0
T190	10708	46	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2275	0	0
T115	10114	34	0	0
T117	42474	184	0	0
T142	10253	70	0	0
T160	23114	228	0	0
T176	17600	30	0	0
T186	3332	15	0	0
T187	13625	12	0	0
T188	128628	422	0	0
T189	12522	9	0	0
T190	10708	10	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2424	0	0
T115	10114	13	0	0
T117	42474	217	0	0
T136	6269	8	0	0
T142	10253	76	0	0
T160	23114	234	0	0
T176	17600	35	0	0
T186	3332	14	0	0
T188	128628	437	0	0
T189	12522	20	0	0
T190	10708	42	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2264	0	0
T115	10114	18	0	0
T117	42474	275	0	0
T136	6269	3	0	0
T142	10253	14	0	0
T160	23114	194	0	0
T176	17600	39	0	0
T186	3332	6	0	0
T187	13625	3	0	0
T188	128628	442	0	0
T189	12522	2	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2501	0	0
T115	10114	23	0	0
T117	42474	227	0	0
T136	6269	5	0	0
T142	10253	49	0	0
T160	23114	244	0	0
T176	17600	37	0	0
T186	3332	6	0	0
T188	128628	465	0	0
T189	12522	7	0	0
T190	10708	40	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2492	0	0
T115	10114	30	0	0
T117	42474	208	0	0
T142	10253	9	0	0
T160	23114	276	0	0
T176	17600	23	0	0
T186	3332	10	0	0
T187	13625	9	0	0
T188	128628	462	0	0
T189	12522	8	0	0
T190	10708	107	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2456	0	0
T115	10114	27	0	0
T117	42474	216	0	0
T136	6269	27	0	0
T142	10253	23	0	0
T160	23114	231	0	0
T176	17600	52	0	0
T186	3332	9	0	0
T187	13625	3	0	0
T188	128628	498	0	0
T189	12522	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2776	0	0
T6	543081	13	0	0
T28	35162	0	0	0
T44	4150	0	0	0
T67	0	61	0	0
T71	0	16	0	0
T72	0	21	0	0
T74	0	28	0	0
T128	13324	0	0	0
T129	1810	0	0	0
T149	3277	0	0	0
T191	0	27	0	0
T192	0	24	0	0
T193	0	4	0	0
T194	0	2	0	0
T195	0	21	0	0
T196	12677	0	0	0
T197	1476	0	0	0
T198	3958	0	0	0
T199	13929	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2382	0	0
T115	10114	20	0	0
T117	42474	250	0	0
T136	6269	1	0	0
T142	10253	71	0	0
T160	23114	236	0	0
T176	17600	45	0	0
T186	3332	9	0	0
T188	128628	456	0	0
T190	10708	17	0	0
T200	5617	25	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2440	0	0
T115	10114	29	0	0
T117	42474	209	0	0
T136	6269	1	0	0
T142	10253	27	0	0
T160	23114	222	0	0
T176	17600	43	0	0
T186	3332	7	0	0
T187	13625	1	0	0
T188	128628	464	0	0
T189	12522	2	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2433	0	0
T115	10114	19	0	0
T117	42474	222	0	0
T136	6269	17	0	0
T142	10253	74	0	0
T160	23114	261	0	0
T176	17600	50	0	0
T186	3332	12	0	0
T187	13625	6	0	0
T188	128628	455	0	0
T189	12522	19	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2434	0	0
T115	10114	36	0	0
T117	42474	235	0	0
T136	6269	12	0	0
T142	10253	13	0	0
T160	23114	236	0	0
T176	17600	24	0	0
T186	3332	9	0	0
T187	13625	3	0	0
T188	128628	425	0	0
T189	12522	11	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2339	0	0
T115	10114	16	0	0
T117	42474	198	0	0
T136	6269	7	0	0
T142	10253	50	0	0
T160	23114	249	0	0
T176	17600	42	0	0
T186	3332	8	0	0
T188	128628	419	0	0
T190	10708	80	0	0
T200	5617	9	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2293	0	0
T115	10114	26	0	0
T117	42474	183	0	0
T136	6269	16	0	0
T142	10253	22	0	0
T160	23114	243	0	0
T176	17600	27	0	0
T186	3332	13	0	0
T187	13625	4	0	0
T188	128628	431	0	0
T190	10708	28	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2485	0	0
T115	10114	28	0	0
T117	42474	211	0	0
T136	6269	19	0	0
T142	10253	14	0	0
T160	23114	279	0	0
T176	17600	42	0	0
T188	128628	423	0	0
T189	12522	11	0	0
T190	10708	56	0	0
T200	5617	30	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2356	0	0
T115	10114	28	0	0
T117	42474	206	0	0
T136	6269	7	0	0
T142	10253	39	0	0
T160	23114	240	0	0
T176	17600	32	0	0
T186	3332	6	0	0
T188	128628	434	0	0
T189	12522	1	0	0
T190	10708	31	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2497	0	0
T115	10114	40	0	0
T117	42474	234	0	0
T136	6269	6	0	0
T142	10253	19	0	0
T160	23114	276	0	0
T176	17600	47	0	0
T186	3332	14	0	0
T187	13625	17	0	0
T188	128628	508	0	0
T189	12522	19	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2402	0	0
T115	10114	22	0	0
T117	42474	237	0	0
T136	6269	11	0	0
T142	10253	56	0	0
T160	23114	233	0	0
T176	17600	43	0	0
T186	3332	17	0	0
T187	13625	10	0	0
T188	128628	441	0	0
T190	10708	18	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2425	0	0
T115	10114	29	0	0
T117	42474	219	0	0
T136	6269	4	0	0
T142	10253	43	0	0
T160	23114	262	0	0
T176	17600	39	0	0
T186	3332	4	0	0
T188	128628	415	0	0
T189	12522	5	0	0
T190	10708	66	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2386	0	0
T115	10114	35	0	0
T117	42474	193	0	0
T136	6269	4	0	0
T142	10253	43	0	0
T160	23114	257	0	0
T176	17600	36	0	0
T186	3332	12	0	0
T187	13625	16	0	0
T188	128628	488	0	0
T190	10708	23	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2467	0	0
T115	10114	15	0	0
T117	42474	244	0	0
T136	6269	4	0	0
T142	10253	26	0	0
T160	23114	226	0	0
T176	17600	32	0	0
T186	3332	9	0	0
T187	13625	8	0	0
T188	128628	479	0	0
T189	12522	3	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2344	0	0
T23	20424	0	0	0
T115	0	28	0	0
T117	0	206	0	0
T136	0	1	0	0
T142	0	49	0	0
T160	0	243	0	0
T176	0	35	0	0
T186	0	11	0	0
T187	0	9	0	0
T188	0	427	0	0
T201	12543	4	0	0
T202	1544	0	0	0
T203	3308	0	0	0
T204	7721	0	0	0
T205	133221	0	0	0
T206	27702	0	0	0
T207	4210	0	0	0
T208	8460	0	0	0
T209	6595	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2427	0	0
T115	10114	29	0	0
T117	42474	205	0	0
T136	6269	5	0	0
T142	10253	29	0	0
T160	23114	233	0	0
T176	17600	38	0	0
T186	3332	7	0	0
T187	13625	3	0	0
T188	128628	456	0	0
T190	10708	17	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2434	0	0
T115	10114	12	0	0
T117	42474	240	0	0
T136	6269	1	0	0
T142	10253	44	0	0
T160	23114	251	0	0
T176	17600	31	0	0
T186	3332	9	0	0
T188	128628	461	0	0
T189	12522	6	0	0
T190	10708	28	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2414	0	0
T115	10114	31	0	0
T117	42474	246	0	0
T136	6269	10	0	0
T142	10253	62	0	0
T160	23114	255	0	0
T176	17600	29	0	0
T186	3332	8	0	0
T188	128628	434	0	0
T189	12522	7	0	0
T190	10708	43	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2496	0	0
T115	10114	15	0	0
T117	42474	183	0	0
T136	6269	8	0	0
T142	10253	69	0	0
T160	23114	268	0	0
T176	17600	41	0	0
T188	128628	446	0	0
T189	12522	9	0	0
T190	10708	81	0	0
T200	5617	18	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2391	0	0
T11	156306	0	0	0
T100	3585	0	0	0
T101	15985	0	0	0
T102	9461	0	0	0
T103	14551	0	0	0
T104	2903	0	0	0
T105	11659	0	0	0
T115	0	32	0	0
T117	0	192	0	0
T142	0	59	0	0
T160	0	227	0	0
T176	0	51	0	0
T186	0	1	0	0
T187	0	8	0	0
T188	0	468	0	0
T189	0	12	0	0
T210	3522	6	0	0
T211	2561	0	0	0
T212	3469	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2526	0	0
T115	10114	30	0	0
T117	42474	204	0	0
T136	6269	20	0	0
T142	10253	51	0	0
T160	23114	234	0	0
T176	17600	37	0	0
T186	3332	12	0	0
T188	128628	473	0	0
T189	12522	6	0	0
T190	10708	28	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2405	0	0
T115	10114	32	0	0
T117	42474	207	0	0
T136	6269	21	0	0
T142	10253	24	0	0
T160	23114	246	0	0
T176	17600	37	0	0
T186	3332	2	0	0
T188	128628	444	0	0
T190	10708	59	0	0
T200	5617	8	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28989889	2344	0	0
T115	10114	41	0	0
T117	42474	239	0	0
T136	6269	14	0	0
T142	10253	73	0	0
T160	23114	234	0	0
T176	17600	44	0	0
T186	3332	2	0	0
T187	13625	2	0	0
T188	128628	406	0	0
T189	12522	8	0	0