Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3798772	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

627885

1

T1

230

T2

157

T3

862

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4016551	1			T1	2591		T2	368		T3	2078
values[0x0]	204431	1			T1	52		T2	39		T3	357
values[0x1]	205675	1			T1	69		T2	44		T3	343

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2594545	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1832112

1

T1

992

T2

212

T3

1413

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	33893	1			T1	9		T2	1		T3	6
valid_sources[0x01]	15449	1			T1	9		T2	2		T3	13
valid_sources[0x02]	20130	1			T1	9		T3	8		T10	10
valid_sources[0x03]	16528	1			T1	4		T2	3		T3	11
valid_sources[0x04]	14629	1			T1	15		T2	2		T3	11
valid_sources[0x05]	14981	1			T1	11		T2	2		T3	9
valid_sources[0x06]	15962	1			T1	7		T2	6		T3	3
valid_sources[0x07]	14673	1			T1	9		T2	5		T3	6
valid_sources[0x08]	17963	1			T1	18		T2	1		T3	11
valid_sources[0x09]	14385	1			T1	15		T2	4		T3	25
valid_sources[0x0a]	13880	1			T1	13		T3	4		T10	8
valid_sources[0x0b]	14774	1			T1	16		T2	1		T3	16
valid_sources[0x0c]	15518	1			T1	16		T2	3		T3	15
valid_sources[0x0d]	14867	1			T1	10		T2	1		T3	10
valid_sources[0x0e]	33542	1			T1	6		T2	1		T3	13
valid_sources[0x0f]	14853	1			T1	14		T2	3		T3	11
valid_sources[0x10]	14567	1			T1	7		T2	1		T3	11
valid_sources[0x11]	15456	1			T1	7		T2	5		T3	10
valid_sources[0x12]	15165	1			T1	8		T2	2		T3	10
valid_sources[0x13]	14974	1			T1	14		T3	11		T10	13
valid_sources[0x14]	20269	1			T1	13		T2	2		T3	12
valid_sources[0x15]	35102	1			T1	17		T2	2		T3	6
valid_sources[0x16]	31301	1			T1	4		T2	1		T3	12
valid_sources[0x17]	25785	1			T1	8		T2	2		T3	8
valid_sources[0x18]	24357	1			T1	9		T2	3		T3	13
valid_sources[0x19]	16656	1			T1	16		T3	10		T11	5
valid_sources[0x1a]	15905	1			T1	7		T2	3		T3	5
valid_sources[0x1b]	13919	1			T1	3		T2	2		T3	9
valid_sources[0x1c]	14500	1			T1	10		T2	1		T3	20
valid_sources[0x1d]	14936	1			T1	15		T2	5		T3	11
valid_sources[0x1e]	15562	1			T1	4		T2	5		T3	12
valid_sources[0x1f]	20026	1			T1	10		T2	1		T3	2
valid_sources[0x20]	19638	1			T1	12		T3	8		T10	5
valid_sources[0x21]	19967	1			T1	6		T2	1		T3	17
valid_sources[0x22]	14895	1			T1	10		T3	11		T10	2
valid_sources[0x23]	14294	1			T1	6		T2	5		T3	11
valid_sources[0x24]	15187	1			T1	10		T2	5		T3	7
valid_sources[0x25]	14529	1			T1	7		T2	4		T3	2
valid_sources[0x26]	14332	1			T1	7		T2	2		T3	14
valid_sources[0x27]	14903	1			T1	12		T2	2		T3	15
valid_sources[0x28]	15977	1			T1	9		T2	2		T3	14
valid_sources[0x29]	17644	1			T1	9		T2	2		T3	11
valid_sources[0x2a]	17464	1			T1	9		T2	3		T3	5
valid_sources[0x2b]	16662	1			T1	13		T2	1		T3	16
valid_sources[0x2c]	15274	1			T1	11		T2	2		T3	16
valid_sources[0x2d]	16106	1			T1	9		T3	11		T10	2
valid_sources[0x2e]	15275	1			T1	11		T2	3		T3	9
valid_sources[0x2f]	19879	1			T1	10		T2	2		T3	3
valid_sources[0x30]	15348	1			T1	12		T2	3		T3	5
valid_sources[0x31]	14278	1			T1	8		T2	3		T3	8
valid_sources[0x32]	15184	1			T1	13		T2	1		T3	14
valid_sources[0x33]	15633	1			T1	5		T2	3		T3	9
valid_sources[0x34]	28159	1			T1	12		T2	4		T3	8
valid_sources[0x35]	16051	1			T1	16		T2	4		T3	17
valid_sources[0x36]	16857	1			T1	8		T3	20		T10	10
valid_sources[0x37]	14160	1			T1	11		T2	4		T3	9
valid_sources[0x38]	15015	1			T1	12		T2	3		T3	14
valid_sources[0x39]	15269	1			T1	11		T2	2		T3	13
valid_sources[0x3a]	14856	1			T1	17		T2	2		T3	12
valid_sources[0x3b]	14875	1			T1	10		T2	2		T3	14
valid_sources[0x3c]	23157	1			T1	15		T2	3		T3	11
valid_sources[0x3d]	19025	1			T1	11		T2	1		T3	25
valid_sources[0x3e]	14906	1			T1	6		T2	2		T3	11
valid_sources[0x3f]	15218	1			T1	17		T2	1		T3	8
valid_sources[0x40]	14920	1			T1	4		T3	12		T10	2
valid_sources[0x41]	14285	1			T1	9		T2	1		T3	16
valid_sources[0x42]	15215	1			T1	12		T2	4		T3	8
valid_sources[0x43]	14081	1			T1	12		T2	2		T3	9
valid_sources[0x44]	14350	1			T1	6		T2	2		T3	6
valid_sources[0x45]	15518	1			T1	6		T2	5		T3	8
valid_sources[0x46]	19245	1			T1	8		T2	2		T3	11
valid_sources[0x47]	28710	1			T1	15		T3	10		T10	1
valid_sources[0x48]	14564	1			T1	13		T2	2		T3	16
valid_sources[0x49]	15342	1			T1	13		T2	1		T3	12
valid_sources[0x4a]	18584	1			T1	6		T2	1		T3	7
valid_sources[0x4b]	16964	1			T1	23		T2	2		T3	13
valid_sources[0x4c]	14896	1			T1	11		T2	2		T3	11
valid_sources[0x4d]	15045	1			T1	10		T2	3		T3	8
valid_sources[0x4e]	14441	1			T1	23		T2	1		T3	10
valid_sources[0x4f]	13916	1			T1	13		T2	3		T3	12
valid_sources[0x50]	14239	1			T1	5		T2	3		T3	6
valid_sources[0x51]	16760	1			T1	12		T2	1		T3	9
valid_sources[0x52]	18851	1			T1	8		T2	2		T3	10
valid_sources[0x53]	15407	1			T1	13		T2	2		T3	10
valid_sources[0x54]	15269	1			T1	5		T2	1		T3	9
valid_sources[0x55]	16234	1			T1	7		T3	9		T10	3
valid_sources[0x56]	13987	1			T1	12		T2	1		T3	7
valid_sources[0x57]	16893	1			T1	9		T3	6		T10	9
valid_sources[0x58]	14743	1			T1	13		T2	1		T3	9
valid_sources[0x59]	14237	1			T1	7		T3	10		T11	6
valid_sources[0x5a]	17517	1			T1	10		T2	2		T3	14
valid_sources[0x5b]	17600	1			T1	10		T2	1		T3	10
valid_sources[0x5c]	18589	1			T1	11		T3	13		T10	3
valid_sources[0x5d]	13933	1			T1	7		T2	4		T3	12
valid_sources[0x5e]	14525	1			T1	9		T3	5		T10	23
valid_sources[0x5f]	14298	1			T1	13		T2	4		T3	8
valid_sources[0x60]	15558	1			T1	7		T2	1		T10	11
valid_sources[0x61]	18462	1			T1	4		T2	2		T3	10
valid_sources[0x62]	33098	1			T1	7		T3	9		T10	3
valid_sources[0x63]	15056	1			T1	7		T2	2		T3	10
valid_sources[0x64]	14920	1			T1	5		T2	1		T3	12
valid_sources[0x65]	14845	1			T1	23		T2	2		T3	11
valid_sources[0x66]	18099	1			T1	7		T2	6		T3	7
valid_sources[0x67]	15172	1			T1	10		T2	3		T3	10
valid_sources[0x68]	15231	1			T1	7		T2	1		T3	8
valid_sources[0x69]	14289	1			T1	14		T2	2		T3	21
valid_sources[0x6a]	16080	1			T1	12		T2	2		T3	6
valid_sources[0x6b]	16249	1			T1	4		T2	1		T3	10
valid_sources[0x6c]	21845	1			T1	14		T2	1		T3	9
valid_sources[0x6d]	15676	1			T1	7		T3	5		T11	5
valid_sources[0x6e]	15495	1			T1	12		T2	5		T3	7
valid_sources[0x6f]	14185	1			T1	13		T2	4		T3	13
valid_sources[0x70]	15016	1			T1	9		T2	3		T3	12
valid_sources[0x71]	14442	1			T1	10		T2	2		T3	8
valid_sources[0x72]	14770	1			T1	6		T2	1		T3	8
valid_sources[0x73]	14737	1			T1	7		T3	12		T10	16
valid_sources[0x74]	18701	1			T1	9		T2	4		T3	10
valid_sources[0x75]	15470	1			T1	12		T2	2		T3	7
valid_sources[0x76]	15605	1			T1	7		T3	8		T10	16
valid_sources[0x77]	38209	1			T1	9		T2	5		T3	18
valid_sources[0x78]	14831	1			T1	14		T2	1		T3	5
valid_sources[0x79]	37293	1			T1	12		T2	1		T3	15
valid_sources[0x7a]	20639	1			T1	16		T2	3		T3	8
valid_sources[0x7b]	14298	1			T1	19		T2	1		T3	13
valid_sources[0x7c]	14916	1			T1	6		T2	3		T3	10
valid_sources[0x7d]	18668	1			T1	12		T3	19		T10	10
valid_sources[0x7e]	16640	1			T1	15		T2	2		T3	9
valid_sources[0x7f]	15429	1			T1	10		T2	2		T3	14
valid_sources[0x80]	15617	1			T1	14		T2	4		T3	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

347345

1

T1

198

T2

128

T3

392

values[0x0]

all_enables

biggest_size

147585

1

T1

17

T2

18

T3

259

values[0x1]

all_enables

biggest_size

132955

1

T1

15

T2

11

T3

211