Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	27775122	10633	0	0
attest_sw_binding_0_rd_A	27775122	2819	0	0
attest_sw_binding_1_rd_A	27775122	2892	0	0
attest_sw_binding_2_rd_A	27775122	2913	0	0
attest_sw_binding_3_rd_A	27775122	2828	0	0
attest_sw_binding_4_rd_A	27775122	2981	0	0
attest_sw_binding_5_rd_A	27775122	2899	0	0
attest_sw_binding_6_rd_A	27775122	2820	0	0
attest_sw_binding_7_rd_A	27775122	2850	0	0
intr_enable_rd_A	27775122	3694	0	0
key_version_rd_A	27775122	2875	0	0
max_creator_key_ver_regwen_rd_A	27775122	2797	0	0
max_owner_int_key_ver_regwen_rd_A	27775122	2844	0	0
max_owner_key_ver_regwen_rd_A	27775122	2707	0	0
reseed_interval_regwen_rd_A	27775122	2922	0	0
salt_0_rd_A	27775122	2971	0	0
salt_1_rd_A	27775122	2920	0	0
salt_2_rd_A	27775122	2876	0	0
salt_3_rd_A	27775122	2908	0	0
salt_4_rd_A	27775122	2973	0	0
salt_5_rd_A	27775122	2897	0	0
salt_6_rd_A	27775122	2748	0	0
salt_7_rd_A	27775122	2892	0	0
sealing_sw_binding_0_rd_A	27775122	2639	0	0
sealing_sw_binding_1_rd_A	27775122	2954	0	0
sealing_sw_binding_2_rd_A	27775122	2892	0	0
sealing_sw_binding_3_rd_A	27775122	2812	0	0
sealing_sw_binding_4_rd_A	27775122	2793	0	0
sealing_sw_binding_5_rd_A	27775122	2895	0	0
sealing_sw_binding_6_rd_A	27775122	2904	0	0
sealing_sw_binding_7_rd_A	27775122	2933	0	0
sideload_clear_rd_A	27775122	2768	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	10633	0	0
T8	8527	0	0	0
T22	23152	0	0	0
T32	10006	0	0	0
T40	0	56	0	0
T44	47718	895	0	0
T48	15744	0	0	0
T51	0	27	0	0
T70	19213	0	0	0
T71	10958	0	0	0
T72	6913	0	0	0
T73	8572	0	0	0
T74	3515	0	0	0
T90	0	140	0	0
T108	0	25	0	0
T110	0	913	0	0
T111	0	159	0	0
T112	0	271	0	0
T113	0	23	0	0
T114	0	71	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2819	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	46	0	0
T108	14887	14	0	0
T113	0	15	0	0
T171	0	20	0	0
T172	0	104	0	0
T173	0	55	0	0
T174	0	31	0	0
T175	0	19	0	0
T176	0	6	0	0
T177	0	430	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2892	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	51	0	0
T108	14887	8	0	0
T113	0	1	0	0
T124	0	23	0	0
T171	0	19	0	0
T172	0	66	0	0
T173	0	60	0	0
T174	0	26	0	0
T175	0	12	0	0
T177	0	453	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2913	0	0
T22	23152	0	0	0
T30	10879	3	0	0
T31	4339	0	0	0
T32	10006	0	0	0
T44	47718	0	0	0
T70	19213	0	0	0
T71	10958	0	0	0
T72	6913	0	0	0
T103	0	46	0	0
T108	0	8	0	0
T113	0	11	0	0
T171	0	18	0	0
T172	0	52	0	0
T173	0	39	0	0
T174	0	30	0	0
T175	0	26	0	0
T176	0	10	0	0
T185	21279	0	0	0
T186	19605	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2828	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	61	0	0
T108	14887	27	0	0
T113	0	12	0	0
T171	0	10	0	0
T172	0	88	0	0
T173	0	80	0	0
T174	0	18	0	0
T175	0	12	0	0
T176	0	13	0	0
T177	0	405	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2981	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	61	0	0
T108	14887	31	0	0
T113	0	11	0	0
T124	0	24	0	0
T171	0	21	0	0
T172	0	99	0	0
T173	0	54	0	0
T174	0	33	0	0
T175	0	53	0	0
T177	0	425	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2899	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	74	0	0
T108	14887	8	0	0
T113	0	2	0	0
T171	0	25	0	0
T172	0	80	0	0
T173	0	55	0	0
T174	0	22	0	0
T175	0	30	0	0
T176	0	2	0	0
T177	0	431	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2820	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	52	0	0
T108	14887	32	0	0
T113	0	1	0	0
T171	0	9	0	0
T172	0	58	0	0
T173	0	64	0	0
T174	0	32	0	0
T175	0	24	0	0
T176	0	4	0	0
T177	0	461	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2850	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	34	0	0
T108	14887	29	0	0
T113	0	10	0	0
T171	0	4	0	0
T172	0	66	0	0
T173	0	49	0	0
T174	0	18	0	0
T175	0	33	0	0
T176	0	9	0	0
T177	0	410	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	3694	0	0
T39	0	37	0	0
T42	0	23	0	0
T47	0	17	0	0
T49	881577	77	0	0
T65	0	15	0	0
T81	5027	0	0	0
T108	14887	21	0	0
T113	0	18	0	0
T171	0	31	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0
T187	0	12	0	0
T188	0	43	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2875	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	70	0	0
T108	14887	23	0	0
T113	0	19	0	0
T124	0	27	0	0
T171	0	18	0	0
T172	0	55	0	0
T173	0	72	0	0
T174	0	20	0	0
T175	0	30	0	0
T177	0	392	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2797	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	51	0	0
T108	14887	29	0	0
T113	0	8	0	0
T124	0	29	0	0
T171	0	20	0	0
T172	0	81	0	0
T173	0	77	0	0
T174	0	14	0	0
T175	0	32	0	0
T177	0	447	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2844	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	45	0	0
T108	14887	17	0	0
T113	0	18	0	0
T171	0	2	0	0
T172	0	73	0	0
T173	0	68	0	0
T174	0	26	0	0
T175	0	19	0	0
T176	0	1	0	0
T177	0	459	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2707	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	43	0	0
T108	14887	11	0	0
T113	0	15	0	0
T124	0	12	0	0
T171	0	4	0	0
T172	0	69	0	0
T173	0	34	0	0
T174	0	34	0	0
T175	0	12	0	0
T177	0	377	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2922	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	72	0	0
T108	14887	31	0	0
T113	0	13	0	0
T124	0	28	0	0
T171	0	31	0	0
T172	0	46	0	0
T173	0	56	0	0
T174	0	41	0	0
T175	0	30	0	0
T177	0	414	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2971	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	43	0	0
T108	14887	26	0	0
T113	0	24	0	0
T124	0	29	0	0
T171	0	16	0	0
T172	0	90	0	0
T173	0	50	0	0
T174	0	47	0	0
T175	0	22	0	0
T177	0	465	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2920	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	66	0	0
T108	14887	9	0	0
T113	0	25	0	0
T171	0	28	0	0
T172	0	55	0	0
T173	0	38	0	0
T174	0	20	0	0
T175	0	30	0	0
T176	0	17	0	0
T177	0	472	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2876	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	63	0	0
T108	14887	4	0	0
T113	0	6	0	0
T124	0	8	0	0
T171	0	2	0	0
T172	0	64	0	0
T173	0	72	0	0
T174	0	21	0	0
T175	0	34	0	0
T177	0	414	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2908	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	48	0	0
T108	14887	18	0	0
T113	0	15	0	0
T124	0	4	0	0
T171	0	8	0	0
T172	0	78	0	0
T173	0	48	0	0
T174	0	24	0	0
T175	0	23	0	0
T177	0	471	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2973	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	61	0	0
T108	14887	19	0	0
T113	0	9	0	0
T124	0	46	0	0
T171	0	14	0	0
T172	0	91	0	0
T173	0	41	0	0
T174	0	28	0	0
T175	0	21	0	0
T177	0	438	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2897	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	48	0	0
T108	14887	17	0	0
T113	0	10	0	0
T171	0	14	0	0
T172	0	73	0	0
T173	0	53	0	0
T174	0	23	0	0
T175	0	38	0	0
T176	0	8	0	0
T177	0	444	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2748	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	58	0	0
T108	14887	39	0	0
T113	0	7	0	0
T171	0	19	0	0
T172	0	74	0	0
T173	0	44	0	0
T174	0	26	0	0
T175	0	21	0	0
T176	0	7	0	0
T177	0	450	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2892	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	51	0	0
T108	14887	5	0	0
T113	0	9	0	0
T171	0	20	0	0
T172	0	93	0	0
T173	0	50	0	0
T174	0	45	0	0
T175	0	26	0	0
T176	0	3	0	0
T177	0	464	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2639	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	58	0	0
T108	14887	21	0	0
T113	0	9	0	0
T124	0	1	0	0
T171	0	6	0	0
T172	0	53	0	0
T173	0	39	0	0
T174	0	28	0	0
T175	0	13	0	0
T177	0	440	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2954	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	52	0	0
T108	14887	9	0	0
T113	0	12	0	0
T171	0	8	0	0
T172	0	41	0	0
T173	0	48	0	0
T174	0	44	0	0
T175	0	22	0	0
T176	0	7	0	0
T177	0	473	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2892	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	60	0	0
T108	14887	17	0	0
T113	0	15	0	0
T171	0	9	0	0
T172	0	71	0	0
T173	0	39	0	0
T174	0	15	0	0
T175	0	64	0	0
T176	0	3	0	0
T177	0	410	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2812	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	48	0	0
T108	14887	16	0	0
T113	0	10	0	0
T171	0	7	0	0
T172	0	55	0	0
T173	0	61	0	0
T174	0	26	0	0
T175	0	34	0	0
T177	0	467	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0
T189	0	2	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2793	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	58	0	0
T108	14887	4	0	0
T113	0	12	0	0
T124	0	59	0	0
T171	0	2	0	0
T172	0	66	0	0
T173	0	47	0	0
T174	0	18	0	0
T175	0	33	0	0
T177	0	422	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2895	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	72	0	0
T108	14887	11	0	0
T113	0	11	0	0
T171	0	14	0	0
T172	0	42	0	0
T173	0	60	0	0
T174	0	29	0	0
T175	0	27	0	0
T176	0	8	0	0
T177	0	437	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2904	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	52	0	0
T108	14887	11	0	0
T113	0	3	0	0
T124	0	8	0	0
T171	0	15	0	0
T172	0	78	0	0
T173	0	53	0	0
T174	0	40	0	0
T175	0	32	0	0
T177	0	495	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2933	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	52	0	0
T108	14887	16	0	0
T113	0	20	0	0
T171	0	26	0	0
T172	0	90	0	0
T173	0	61	0	0
T174	0	24	0	0
T175	0	17	0	0
T176	0	10	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0
T190	0	2	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27775122	2768	0	0
T49	881577	0	0	0
T81	5027	0	0	0
T103	0	48	0	0
T108	14887	14	0	0
T124	0	9	0	0
T125	0	12	0	0
T171	0	16	0	0
T172	0	77	0	0
T173	0	28	0	0
T174	0	18	0	0
T175	0	15	0	0
T177	0	401	0	0
T178	12735	0	0	0
T179	5944	0	0	0
T180	6477	0	0	0
T181	4226	0	0	0
T182	7046	0	0	0
T183	2875	0	0	0
T184	16380	0	0	0