Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4144907	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

627439

1

T1

650

T2

273

T3

257

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4352418	1			T1	911		T2	4083		T3	5003
values[0x0]	208386	1			T1	273		T2	107		T3	100
values[0x1]	211542	1			T1	238		T2	123		T3	122

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2823746	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1948600

1

T1

857

T2

1574

T3

1961

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20104	1			T1	6		T2	6		T3	63
valid_sources[0x01]	22095	1			T1	4		T2	20		T3	21
valid_sources[0x02]	16476	1			T1	7		T2	16		T3	8
valid_sources[0x03]	18298	1			T1	5		T2	12		T3	6
valid_sources[0x04]	22604	1			T1	9		T2	11		T3	24
valid_sources[0x05]	15652	1			T1	10		T2	11		T3	5
valid_sources[0x06]	38668	1			T1	5		T2	16		T3	2
valid_sources[0x07]	14902	1			T1	4		T2	20		T3	7
valid_sources[0x08]	16126	1			T1	3		T2	23		T3	23
valid_sources[0x09]	15962	1			T1	6		T2	18		T3	6
valid_sources[0x0a]	26227	1			T1	5		T2	27		T3	12
valid_sources[0x0b]	16569	1			T1	6		T2	12		T3	16
valid_sources[0x0c]	15731	1			T1	5		T2	8		T3	4
valid_sources[0x0d]	16907	1			T1	4		T2	17		T3	3
valid_sources[0x0e]	45809	1			T1	12		T2	23		T3	17
valid_sources[0x0f]	29257	1			T1	6		T2	27		T3	50
valid_sources[0x10]	18174	1			T1	8		T2	12		T3	31
valid_sources[0x11]	15450	1			T1	7		T2	16		T3	26
valid_sources[0x12]	15421	1			T1	2		T2	14		T3	30
valid_sources[0x13]	16429	1			T1	3		T2	14		T3	13
valid_sources[0x14]	14384	1			T1	7		T2	11		T3	31
valid_sources[0x15]	16462	1			T1	7		T2	11		T3	7
valid_sources[0x16]	15284	1			T1	5		T2	13		T3	7
valid_sources[0x17]	14912	1			T1	6		T2	16		T3	39
valid_sources[0x18]	15553	1			T1	9		T2	24		T3	7
valid_sources[0x19]	90454	1			T1	9		T2	11		T3	36
valid_sources[0x1a]	84674	1			T1	4		T2	17		T3	25
valid_sources[0x1b]	15694	1			T1	3		T2	16		T3	11
valid_sources[0x1c]	19657	1			T1	6		T2	24		T3	21
valid_sources[0x1d]	19422	1			T1	1		T2	23		T3	58
valid_sources[0x1e]	15134	1			T1	6		T2	17		T3	3
valid_sources[0x1f]	16546	1			T1	2		T2	25		T3	13
valid_sources[0x20]	16372	1			T1	5		T2	11		T3	12
valid_sources[0x21]	14742	1			T1	9		T2	21		T3	42
valid_sources[0x22]	16154	1			T1	8		T2	22		T3	5
valid_sources[0x23]	14822	1			T1	9		T2	15		T3	19
valid_sources[0x24]	15731	1			T1	1		T2	22		T7	108
valid_sources[0x25]	19593	1			T1	5		T2	21		T3	10
valid_sources[0x26]	16516	1			T1	3		T2	16		T3	11
valid_sources[0x27]	18799	1			T1	8		T2	13		T3	20
valid_sources[0x28]	15642	1			T1	5		T2	20		T3	35
valid_sources[0x29]	16036	1			T1	5		T2	17		T3	3
valid_sources[0x2a]	15524	1			T1	7		T2	14		T3	12
valid_sources[0x2b]	16313	1			T1	5		T2	22		T3	23
valid_sources[0x2c]	14235	1			T1	6		T2	12		T3	8
valid_sources[0x2d]	15791	1			T1	10		T2	7		T3	6
valid_sources[0x2e]	15124	1			T1	1		T2	13		T3	4
valid_sources[0x2f]	17155	1			T1	4		T2	18		T3	14
valid_sources[0x30]	21312	1			T1	5		T2	15		T3	33
valid_sources[0x31]	19531	1			T1	3		T2	18		T3	7
valid_sources[0x32]	20132	1			T1	3		T2	26		T3	24
valid_sources[0x33]	17416	1			T1	8		T2	31		T3	10
valid_sources[0x34]	14237	1			T1	6		T2	11		T3	36
valid_sources[0x35]	17782	1			T1	5		T2	21		T3	3
valid_sources[0x36]	15032	1			T1	6		T2	8		T3	27
valid_sources[0x37]	58118	1			T1	7		T2	12		T3	32
valid_sources[0x38]	17949	1			T1	4		T2	19		T3	21
valid_sources[0x39]	15407	1			T1	8		T2	22		T3	3
valid_sources[0x3a]	16945	1			T1	4		T2	20		T3	6
valid_sources[0x3b]	15400	1			T1	3		T2	15		T3	23
valid_sources[0x3c]	17106	1			T1	4		T2	18		T3	7
valid_sources[0x3d]	36291	1			T1	2		T2	18		T3	22
valid_sources[0x3e]	15674	1			T1	4		T2	16		T3	8
valid_sources[0x3f]	16941	1			T1	3		T2	14		T3	38
valid_sources[0x40]	20165	1			T1	4		T2	12		T3	51
valid_sources[0x41]	15297	1			T1	7		T2	15		T3	41
valid_sources[0x42]	15285	1			T1	8		T2	22		T3	22
valid_sources[0x43]	16433	1			T1	7		T2	19		T3	20
valid_sources[0x44]	17296	1			T1	4		T2	22		T3	41
valid_sources[0x45]	16252	1			T1	4		T2	21		T3	17
valid_sources[0x46]	19870	1			T1	3		T2	17		T3	12
valid_sources[0x47]	16917	1			T1	5		T2	23		T3	26
valid_sources[0x48]	14705	1			T1	14		T2	17		T3	5
valid_sources[0x49]	15348	1			T1	3		T2	19		T3	5
valid_sources[0x4a]	14667	1			T1	7		T2	15		T3	14
valid_sources[0x4b]	15613	1			T1	5		T2	11		T7	107
valid_sources[0x4c]	15648	1			T1	5		T2	27		T7	135
valid_sources[0x4d]	21314	1			T1	10		T2	20		T3	40
valid_sources[0x4e]	15000	1			T1	7		T2	17		T3	9
valid_sources[0x4f]	41954	1			T1	9		T2	22		T3	11
valid_sources[0x50]	17550	1			T1	7		T2	10		T3	29
valid_sources[0x51]	20364	1			T1	10		T2	19		T3	27
valid_sources[0x52]	15245	1			T1	5		T2	15		T3	22
valid_sources[0x53]	15254	1			T1	8		T2	10		T3	46
valid_sources[0x54]	27109	1			T1	7		T2	11		T3	26
valid_sources[0x55]	16830	1			T1	6		T2	15		T3	36
valid_sources[0x56]	15991	1			T1	5		T2	13		T3	34
valid_sources[0x57]	16065	1			T1	12		T2	14		T3	8
valid_sources[0x58]	18566	1			T1	12		T2	12		T3	31
valid_sources[0x59]	15169	1			T1	8		T2	17		T3	30
valid_sources[0x5a]	16508	1			T1	4		T2	12		T3	34
valid_sources[0x5b]	14885	1			T1	8		T2	14		T3	5
valid_sources[0x5c]	56881	1			T1	3		T2	15		T3	28
valid_sources[0x5d]	27023	1			T1	6		T2	20		T3	26
valid_sources[0x5e]	14572	1			T1	6		T2	27		T3	21
valid_sources[0x5f]	15174	1			T1	4		T2	19		T3	26
valid_sources[0x60]	23589	1			T1	4		T2	15		T3	17
valid_sources[0x61]	17534	1			T1	6		T2	12		T3	30
valid_sources[0x62]	16892	1			T1	7		T2	20		T3	54
valid_sources[0x63]	19176	1			T1	5		T2	21		T3	48
valid_sources[0x64]	16136	1			T1	6		T2	23		T3	15
valid_sources[0x65]	15218	1			T1	3		T2	13		T3	38
valid_sources[0x66]	17330	1			T1	5		T2	14		T3	22
valid_sources[0x67]	14909	1			T1	6		T2	15		T7	139
valid_sources[0x68]	16929	1			T1	5		T2	16		T3	27
valid_sources[0x69]	17734	1			T1	2		T2	22		T3	35
valid_sources[0x6a]	15065	1			T1	8		T2	18		T3	43
valid_sources[0x6b]	16385	1			T1	1		T2	12		T3	5
valid_sources[0x6c]	15657	1			T1	3		T2	13		T3	20
valid_sources[0x6d]	15201	1			T1	14		T2	9		T3	24
valid_sources[0x6e]	15023	1			T1	2		T2	13		T3	50
valid_sources[0x6f]	17162	1			T1	2		T2	23		T3	26
valid_sources[0x70]	16411	1			T1	6		T2	11		T3	17
valid_sources[0x71]	15547	1			T1	6		T2	13		T3	16
valid_sources[0x72]	19082	1			T1	12		T2	18		T3	12
valid_sources[0x73]	16291	1			T1	10		T2	21		T3	6
valid_sources[0x74]	16872	1			T1	4		T2	22		T3	31
valid_sources[0x75]	16790	1			T1	2		T2	13		T3	22
valid_sources[0x76]	16948	1			T1	6		T2	23		T3	10
valid_sources[0x77]	15503	1			T1	4		T2	24		T3	57
valid_sources[0x78]	16951	1			T1	1		T2	18		T3	54
valid_sources[0x79]	22686	1			T1	4		T2	19		T3	32
valid_sources[0x7a]	17558	1			T1	1		T2	15		T3	5
valid_sources[0x7b]	15156	1			T1	4		T2	16		T3	19
valid_sources[0x7c]	15512	1			T1	10		T2	11		T3	12
valid_sources[0x7d]	18333	1			T1	7		T2	19		T3	15
valid_sources[0x7e]	15983	1			T1	5		T2	20		T3	5
valid_sources[0x7f]	15821	1			T1	4		T2	12		T3	37
valid_sources[0x80]	19253	1			T1	9		T2	6		T3	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

341147

1

T1

252

T2

134

T3

116

values[0x0]

all_enables

biggest_size

150732

1

T1

218

T2

74

T3

67

values[0x1]

all_enables

biggest_size

135560

1

T1

180

T2

65

T3

74