Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3252454	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

589207

1

T1

211

T2

683

T3

126

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3450607	1			T1	888		T2	2274		T3	298
values[0x0]	193826	1			T1	40		T2	279		T3	45
values[0x1]	197228	1			T1	39		T2	305		T3	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2226463	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1615198

1

T1

433

T2

1340

T3

179

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12050	1			T1	4		T2	11		T4	8
valid_sources[0x01]	16611	1			T1	5		T2	9		T4	8
valid_sources[0x02]	13119	1			T1	1		T2	7		T4	5
valid_sources[0x03]	12369	1			T1	2		T2	16		T4	2
valid_sources[0x04]	12011	1			T1	4		T2	4		T4	6
valid_sources[0x05]	13409	1			T2	12		T4	5		T13	17
valid_sources[0x06]	14220	1			T1	5		T2	17		T4	9
valid_sources[0x07]	13072	1			T1	2		T2	11		T4	8
valid_sources[0x08]	12810	1			T1	5		T2	11		T4	7
valid_sources[0x09]	12931	1			T1	4		T2	10		T4	10
valid_sources[0x0a]	13170	1			T1	2		T2	11		T4	4
valid_sources[0x0b]	12196	1			T1	3		T2	13		T4	3
valid_sources[0x0c]	12218	1			T1	7		T2	9		T4	4
valid_sources[0x0d]	14505	1			T1	4		T2	16		T4	1
valid_sources[0x0e]	16589	1			T1	3		T2	5		T4	4
valid_sources[0x0f]	14878	1			T1	1		T2	17		T4	5
valid_sources[0x10]	12608	1			T1	1		T2	11		T4	3
valid_sources[0x11]	12273	1			T1	2		T2	12		T4	5
valid_sources[0x12]	12482	1			T1	3		T2	9		T13	35
valid_sources[0x13]	30080	1			T1	7		T2	11		T4	6
valid_sources[0x14]	12493	1			T1	4		T2	10		T4	12
valid_sources[0x15]	12344	1			T1	1		T2	14		T4	1
valid_sources[0x16]	12203	1			T1	2		T2	13		T4	4
valid_sources[0x17]	12332	1			T1	10		T2	11		T4	3
valid_sources[0x18]	12160	1			T1	2		T2	10		T4	6
valid_sources[0x19]	12784	1			T2	15		T4	5		T13	11
valid_sources[0x1a]	13219	1			T1	5		T2	14		T4	10
valid_sources[0x1b]	11880	1			T1	3		T2	10		T4	4
valid_sources[0x1c]	13450	1			T1	8		T2	13		T4	7
valid_sources[0x1d]	12265	1			T1	4		T2	17		T4	11
valid_sources[0x1e]	12318	1			T1	3		T2	10		T4	6
valid_sources[0x1f]	12592	1			T1	2		T2	9		T4	20
valid_sources[0x20]	12372	1			T1	1		T2	8		T4	2
valid_sources[0x21]	12323	1			T1	2		T2	7		T4	4
valid_sources[0x22]	11731	1			T1	4		T2	9		T4	1
valid_sources[0x23]	12128	1			T1	5		T2	9		T4	4
valid_sources[0x24]	13166	1			T1	5		T2	5		T4	21
valid_sources[0x25]	13288	1			T1	8		T2	9		T4	2
valid_sources[0x26]	25761	1			T1	2		T2	8		T4	1
valid_sources[0x27]	11797	1			T1	5		T2	14		T4	8
valid_sources[0x28]	12823	1			T1	7		T2	16		T4	12
valid_sources[0x29]	13138	1			T1	4		T2	13		T4	10
valid_sources[0x2a]	14603	1			T1	5		T2	10		T4	6
valid_sources[0x2b]	12733	1			T1	3		T2	18		T4	5
valid_sources[0x2c]	16416	1			T1	5		T2	16		T4	9
valid_sources[0x2d]	13790	1			T1	3		T2	10		T4	12
valid_sources[0x2e]	14919	1			T1	8		T2	11		T4	8
valid_sources[0x2f]	24645	1			T1	1		T2	13		T4	9
valid_sources[0x30]	12189	1			T1	5		T2	22		T4	6
valid_sources[0x31]	12115	1			T1	6		T2	10		T13	18
valid_sources[0x32]	18786	1			T1	6		T2	5		T4	7
valid_sources[0x33]	12706	1			T1	3		T2	7		T4	1
valid_sources[0x34]	12128	1			T1	5		T2	10		T4	10
valid_sources[0x35]	45010	1			T1	5		T2	16		T4	7
valid_sources[0x36]	12199	1			T1	5		T2	9		T4	2
valid_sources[0x37]	14682	1			T1	6		T2	8		T4	3
valid_sources[0x38]	18320	1			T1	3		T2	8		T4	5
valid_sources[0x39]	11504	1			T1	7		T2	10		T4	13
valid_sources[0x3a]	12164	1			T1	7		T2	11		T4	8
valid_sources[0x3b]	12400	1			T1	3		T2	5		T4	1
valid_sources[0x3c]	13881	1			T1	1		T2	14		T4	10
valid_sources[0x3d]	12215	1			T1	4		T2	6		T4	5
valid_sources[0x3e]	13959	1			T1	7		T2	19		T4	9
valid_sources[0x3f]	11827	1			T1	5		T2	13		T4	4
valid_sources[0x40]	12515	1			T1	4		T2	11		T4	2
valid_sources[0x41]	15209	1			T1	4		T2	9		T4	6
valid_sources[0x42]	12896	1			T1	1		T2	13		T4	7
valid_sources[0x43]	12651	1			T1	4		T2	9		T4	2
valid_sources[0x44]	13431	1			T1	4		T2	8		T4	6
valid_sources[0x45]	17664	1			T1	6		T2	12		T4	6
valid_sources[0x46]	12765	1			T1	4		T2	14		T4	3
valid_sources[0x47]	12378	1			T1	7		T2	8		T4	2
valid_sources[0x48]	12305	1			T1	1		T2	16		T4	3
valid_sources[0x49]	15336	1			T1	3		T2	8		T4	8
valid_sources[0x4a]	12677	1			T1	3		T2	8		T4	17
valid_sources[0x4b]	12547	1			T1	2		T2	13		T4	4
valid_sources[0x4c]	15508	1			T1	3		T2	6		T4	5
valid_sources[0x4d]	12280	1			T1	8		T2	7		T4	9
valid_sources[0x4e]	12884	1			T1	3		T2	11		T4	3
valid_sources[0x4f]	12250	1			T1	2		T2	13		T4	20
valid_sources[0x50]	12841	1			T1	1		T2	9		T4	7
valid_sources[0x51]	11723	1			T1	4		T2	9		T4	1
valid_sources[0x52]	12104	1			T1	2		T2	14		T4	4
valid_sources[0x53]	13204	1			T1	1		T2	16		T4	4
valid_sources[0x54]	16144	1			T1	6		T2	12		T4	3
valid_sources[0x55]	14066	1			T1	5		T2	10		T4	3
valid_sources[0x56]	13782	1			T1	10		T2	9		T4	7
valid_sources[0x57]	11867	1			T1	6		T2	9		T4	9
valid_sources[0x58]	14871	1			T1	5		T2	14		T4	13
valid_sources[0x59]	13938	1			T1	1		T2	15		T4	9
valid_sources[0x5a]	11859	1			T1	3		T2	12		T4	12
valid_sources[0x5b]	12787	1			T1	4		T2	14		T13	16
valid_sources[0x5c]	12458	1			T1	2		T2	13		T4	7
valid_sources[0x5d]	13416	1			T1	3		T2	9		T4	1
valid_sources[0x5e]	13265	1			T1	3		T2	10		T4	4
valid_sources[0x5f]	12697	1			T1	2		T2	9		T4	1
valid_sources[0x60]	12286	1			T1	5		T2	11		T4	6
valid_sources[0x61]	12560	1			T1	3		T2	18		T4	2
valid_sources[0x62]	12572	1			T1	2		T2	11		T4	5
valid_sources[0x63]	12681	1			T1	2		T2	9		T4	11
valid_sources[0x64]	13112	1			T1	2		T2	7		T4	9
valid_sources[0x65]	12848	1			T1	6		T2	12		T4	4
valid_sources[0x66]	129546	1			T1	6		T2	8		T4	2
valid_sources[0x67]	13099	1			T1	6		T2	7		T4	9
valid_sources[0x68]	16003	1			T1	6		T2	12		T4	3
valid_sources[0x69]	12851	1			T1	2		T2	13		T4	10
valid_sources[0x6a]	12419	1			T1	6		T2	7		T4	7
valid_sources[0x6b]	14207	1			T1	4		T2	9		T4	4
valid_sources[0x6c]	14959	1			T1	6		T2	13		T4	7
valid_sources[0x6d]	12600	1			T1	5		T2	11		T4	10
valid_sources[0x6e]	12197	1			T1	1		T2	18		T4	20
valid_sources[0x6f]	14801	1			T1	4		T2	6		T4	3
valid_sources[0x70]	12588	1			T1	5		T2	8		T4	9
valid_sources[0x71]	13191	1			T1	3		T2	10		T4	16
valid_sources[0x72]	13795	1			T1	2		T2	13		T4	1
valid_sources[0x73]	12534	1			T1	4		T2	11		T4	11
valid_sources[0x74]	13041	1			T1	7		T2	10		T4	2
valid_sources[0x75]	15210	1			T1	9		T2	11		T4	3
valid_sources[0x76]	12658	1			T1	4		T2	10		T4	2
valid_sources[0x77]	12775	1			T1	7		T2	13		T4	4
valid_sources[0x78]	21505	1			T1	6		T2	6		T4	13
valid_sources[0x79]	12662	1			T1	4		T2	6		T4	16
valid_sources[0x7a]	12499	1			T1	5		T2	8		T4	5
valid_sources[0x7b]	13523	1			T2	16		T4	1		T13	19
valid_sources[0x7c]	13574	1			T1	3		T2	7		T4	3
valid_sources[0x7d]	12081	1			T1	5		T2	11		T4	1
valid_sources[0x7e]	12624	1			T1	7		T2	15		T4	3
valid_sources[0x7f]	12819	1			T1	5		T2	10		T4	8
valid_sources[0x80]	12145	1			T1	2		T2	17		T4	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

324963

1

T1

179

T2

329

T3

104

values[0x0]

all_enables

biggest_size

139011

1

T1

19

T2

185

T3

14

values[0x1]

all_enables

biggest_size

125233

1

T1

13

T2

169

T3

8