Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	26848541	13840	0	0
attest_sw_binding_0_rd_A	26848541	2766	0	0
attest_sw_binding_1_rd_A	26848541	2714	0	0
attest_sw_binding_2_rd_A	26848541	2543	0	0
attest_sw_binding_3_rd_A	26848541	2794	0	0
attest_sw_binding_4_rd_A	26848541	2714	0	0
attest_sw_binding_5_rd_A	26848541	2667	0	0
attest_sw_binding_6_rd_A	26848541	2657	0	0
attest_sw_binding_7_rd_A	26848541	2737	0	0
intr_enable_rd_A	26848541	3193	0	0
key_version_rd_A	26848541	2865	0	0
max_creator_key_ver_regwen_rd_A	26848541	2524	0	0
max_owner_int_key_ver_regwen_rd_A	26848541	2834	0	0
max_owner_key_ver_regwen_rd_A	26848541	2714	0	0
reseed_interval_regwen_rd_A	26848541	2503	0	0
salt_0_rd_A	26848541	2820	0	0
salt_1_rd_A	26848541	2708	0	0
salt_2_rd_A	26848541	2687	0	0
salt_3_rd_A	26848541	2700	0	0
salt_4_rd_A	26848541	2789	0	0
salt_5_rd_A	26848541	2690	0	0
salt_6_rd_A	26848541	2655	0	0
salt_7_rd_A	26848541	2588	0	0
sealing_sw_binding_0_rd_A	26848541	2853	0	0
sealing_sw_binding_1_rd_A	26848541	2421	0	0
sealing_sw_binding_2_rd_A	26848541	2743	0	0
sealing_sw_binding_3_rd_A	26848541	2630	0	0
sealing_sw_binding_4_rd_A	26848541	2756	0	0
sealing_sw_binding_5_rd_A	26848541	2552	0	0
sealing_sw_binding_6_rd_A	26848541	2651	0	0
sealing_sw_binding_7_rd_A	26848541	2811	0	0
sideload_clear_rd_A	26848541	2512	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	13840	0	0
T48	0	46	0	0
T50	17855	766	0	0
T51	0	34	0	0
T56	5256	0	0	0
T58	0	703	0	0
T66	0	465	0	0
T132	0	49	0	0
T133	0	324	0	0
T134	0	172	0	0
T135	0	175	0	0
T137	5538	0	0	0
T138	15855	0	0	0
T139	67435	0	0	0
T140	19253	0	0	0
T141	22155	0	0	0
T142	4350	0	0	0
T143	77753	0	0	0
T144	18393	0	0	0
T146	0	400	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2766	0	0
T48	0	20	0	0
T49	0	37	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	63	0	0
T133	85630	79	0	0
T134	0	34	0	0
T135	0	33	0	0
T169	0	2	0	0
T201	0	7	0	0
T202	0	27	0	0
T203	0	11	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2714	0	0
T48	0	42	0	0
T49	0	22	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	36	0	0
T133	85630	71	0	0
T134	0	39	0	0
T135	0	11	0	0
T165	0	9	0	0
T169	0	7	0	0
T202	0	25	0	0
T203	0	6	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2543	0	0
T48	0	10	0	0
T49	0	33	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	25	0	0
T133	85630	51	0	0
T134	0	24	0	0
T135	0	22	0	0
T165	0	24	0	0
T169	0	7	0	0
T202	0	21	0	0
T203	0	23	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2794	0	0
T48	0	29	0	0
T49	0	47	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	40	0	0
T133	85630	84	0	0
T134	0	37	0	0
T135	0	22	0	0
T165	0	14	0	0
T169	0	2	0	0
T202	0	20	0	0
T203	0	9	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2714	0	0
T48	0	22	0	0
T49	0	21	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	26	0	0
T133	85630	66	0	0
T134	0	25	0	0
T135	0	13	0	0
T165	0	12	0	0
T169	0	4	0	0
T202	0	24	0	0
T203	0	10	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2667	0	0
T48	0	28	0	0
T49	0	57	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	36	0	0
T133	85630	35	0	0
T134	0	34	0	0
T135	0	11	0	0
T165	0	3	0	0
T169	0	2	0	0
T202	0	17	0	0
T203	0	7	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2657	0	0
T48	0	28	0	0
T49	0	21	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	44	0	0
T133	85630	39	0	0
T134	0	25	0	0
T135	0	16	0	0
T165	0	12	0	0
T169	0	7	0	0
T202	0	28	0	0
T203	0	16	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2737	0	0
T48	0	24	0	0
T49	0	25	0	0
T68	0	7	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	32	0	0
T133	85630	49	0	0
T134	0	27	0	0
T135	0	9	0	0
T202	0	20	0	0
T203	0	15	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0
T209	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	3193	0	0
T5	6600	0	0	0
T48	0	41	0	0
T53	35143	0	0	0
T59	87872	58	0	0
T78	0	16	0	0
T80	0	36	0	0
T132	0	26	0	0
T133	0	81	0	0
T134	0	37	0	0
T135	0	29	0	0
T150	6208	0	0	0
T204	0	21	0	0
T210	0	23	0	0
T211	4797	0	0	0
T212	2036	0	0	0
T213	5765	0	0	0
T214	7928	0	0	0
T215	31763	0	0	0
T216	5393	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2865	0	0
T48	0	22	0	0
T49	0	35	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	58	0	0
T133	85630	55	0	0
T134	0	44	0	0
T135	0	7	0	0
T165	0	30	0	0
T169	0	1	0	0
T202	0	23	0	0
T203	0	13	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2524	0	0
T48	0	33	0	0
T49	0	33	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	32	0	0
T133	85630	62	0	0
T134	0	18	0	0
T135	0	16	0	0
T165	0	13	0	0
T169	0	4	0	0
T202	0	24	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0
T217	0	16	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2834	0	0
T48	0	36	0	0
T49	0	14	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	33	0	0
T133	85630	66	0	0
T134	0	24	0	0
T135	0	14	0	0
T165	0	20	0	0
T169	0	1	0	0
T202	0	36	0	0
T203	0	25	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2714	0	0
T48	0	32	0	0
T49	0	22	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	29	0	0
T133	85630	51	0	0
T134	0	14	0	0
T135	0	23	0	0
T165	0	46	0	0
T169	0	6	0	0
T202	0	22	0	0
T203	0	19	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2503	0	0
T48	0	18	0	0
T49	0	8	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	42	0	0
T133	85630	69	0	0
T134	0	21	0	0
T135	0	13	0	0
T165	0	7	0	0
T169	0	4	0	0
T202	0	39	0	0
T203	0	22	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2820	0	0
T48	0	30	0	0
T49	0	31	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	28	0	0
T133	85630	44	0	0
T134	0	20	0	0
T135	0	15	0	0
T165	0	22	0	0
T202	0	34	0	0
T203	0	20	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0
T217	0	18	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2708	0	0
T48	0	36	0	0
T49	0	43	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	26	0	0
T133	85630	73	0	0
T134	0	32	0	0
T135	0	6	0	0
T165	0	27	0	0
T169	0	2	0	0
T202	0	18	0	0
T203	0	8	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2687	0	0
T48	0	40	0	0
T49	0	46	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	23	0	0
T133	85630	43	0	0
T134	0	51	0	0
T135	0	25	0	0
T165	0	38	0	0
T169	0	3	0	0
T202	0	30	0	0
T203	0	7	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2700	0	0
T48	0	44	0	0
T49	0	20	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	32	0	0
T133	85630	65	0	0
T134	0	45	0	0
T135	0	6	0	0
T165	0	11	0	0
T169	0	6	0	0
T202	0	12	0	0
T203	0	37	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2789	0	0
T48	0	28	0	0
T49	0	34	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	41	0	0
T133	85630	60	0	0
T134	0	26	0	0
T135	0	5	0	0
T165	0	18	0	0
T169	0	1	0	0
T202	0	17	0	0
T203	0	9	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2690	0	0
T48	0	31	0	0
T49	0	33	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	36	0	0
T133	85630	45	0	0
T134	0	71	0	0
T135	0	12	0	0
T165	0	32	0	0
T202	0	20	0	0
T203	0	32	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0
T217	0	4	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2655	0	0
T48	0	26	0	0
T49	0	34	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	26	0	0
T133	85630	74	0	0
T134	0	30	0	0
T135	0	19	0	0
T165	0	40	0	0
T169	0	1	0	0
T202	0	47	0	0
T203	0	13	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2588	0	0
T48	0	16	0	0
T49	0	43	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	35	0	0
T133	85630	30	0	0
T134	0	42	0	0
T135	0	24	0	0
T165	0	15	0	0
T169	0	8	0	0
T202	0	29	0	0
T203	0	27	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2853	0	0
T48	0	26	0	0
T49	0	37	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	63	0	0
T133	85630	75	0	0
T134	0	29	0	0
T135	0	17	0	0
T165	0	50	0	0
T202	0	26	0	0
T203	0	3	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0
T217	0	9	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2421	0	0
T48	0	27	0	0
T49	0	42	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	15	0	0
T133	85630	46	0	0
T134	0	17	0	0
T135	0	19	0	0
T165	0	22	0	0
T202	0	5	0	0
T203	0	18	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0
T217	0	21	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2743	0	0
T48	0	21	0	0
T49	0	20	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	52	0	0
T133	85630	56	0	0
T134	0	51	0	0
T135	0	23	0	0
T165	0	30	0	0
T169	0	2	0	0
T202	0	24	0	0
T203	0	9	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2630	0	0
T48	0	29	0	0
T49	0	61	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	18	0	0
T133	85630	64	0	0
T134	0	31	0	0
T135	0	15	0	0
T165	0	37	0	0
T169	0	1	0	0
T202	0	22	0	0
T203	0	4	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2756	0	0
T48	0	23	0	0
T49	0	32	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	20	0	0
T133	85630	59	0	0
T134	0	41	0	0
T135	0	16	0	0
T165	0	33	0	0
T202	0	26	0	0
T203	0	2	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0
T217	0	5	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2552	0	0
T48	0	19	0	0
T49	0	35	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	24	0	0
T133	85630	55	0	0
T134	0	33	0	0
T135	0	1	0	0
T165	0	7	0	0
T169	0	9	0	0
T202	0	23	0	0
T203	0	9	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2651	0	0
T48	0	20	0	0
T49	0	32	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	20	0	0
T133	85630	33	0	0
T134	0	34	0	0
T135	0	17	0	0
T165	0	42	0	0
T169	0	1	0	0
T202	0	20	0	0
T203	0	29	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2811	0	0
T48	0	32	0	0
T49	0	39	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	47	0	0
T133	85630	61	0	0
T134	0	39	0	0
T135	0	24	0	0
T165	0	21	0	0
T169	0	4	0	0
T202	0	11	0	0
T203	0	41	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26848541	2512	0	0
T48	0	15	0	0
T49	0	29	0	0
T74	6033	0	0	0
T82	5057	0	0	0
T83	5079	0	0	0
T132	35496	24	0	0
T133	85630	37	0	0
T134	0	9	0	0
T135	0	3	0	0
T165	0	5	0	0
T169	0	6	0	0
T202	0	21	0	0
T203	0	9	0	0
T204	182259	0	0	0
T205	7142	0	0	0
T206	2276	0	0	0
T207	2028	0	0	0
T208	6162	0	0	0