Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5138180	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

616293

1

T1

132

T2

220

T3

272

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5339357	1			T1	849		T2	8895		T3	642
values[0x0]	205741	1			T1	35		T2	74		T3	66
values[0x1]	209375	1			T1	51		T2	49		T3	77

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3484336	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2270137

1

T1

367

T2

3040

T3

396

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52036	1			T2	41		T4	20		T5	1
valid_sources[0x01]	22417	1			T2	45		T4	23		T5	1
valid_sources[0x02]	27586	1			T1	9		T2	14		T4	20
valid_sources[0x03]	21637	1			T1	1		T2	26		T4	19
valid_sources[0x04]	15132	1			T2	21		T4	21		T5	2
valid_sources[0x05]	19691	1			T1	5		T2	21		T4	16
valid_sources[0x06]	15993	1			T1	1		T2	28		T4	12
valid_sources[0x07]	16302	1			T1	6		T2	53		T4	20
valid_sources[0x08]	16940	1			T1	12		T2	17		T4	11
valid_sources[0x09]	24970	1			T1	1		T2	54		T4	30
valid_sources[0x0a]	16807	1			T1	15		T2	63		T4	16
valid_sources[0x0b]	36520	1			T1	13		T2	73		T4	28
valid_sources[0x0c]	15349	1			T2	11		T4	40		T5	2
valid_sources[0x0d]	19219	1			T1	3		T2	26		T4	22
valid_sources[0x0e]	16517	1			T1	4		T2	44		T4	27
valid_sources[0x0f]	15014	1			T1	4		T2	65		T4	24
valid_sources[0x10]	16038	1			T1	8		T2	24		T4	19
valid_sources[0x11]	20559	1			T1	2		T2	2		T4	19
valid_sources[0x12]	14220	1			T1	3		T2	17		T4	23
valid_sources[0x13]	19810	1			T1	1		T2	8		T4	24
valid_sources[0x14]	72477	1			T1	10		T2	18		T4	32
valid_sources[0x15]	15920	1			T1	7		T2	62		T4	15
valid_sources[0x16]	15519	1			T1	8		T2	33		T4	34
valid_sources[0x17]	23812	1			T1	10		T2	24		T4	22
valid_sources[0x18]	17276	1			T2	54		T4	15		T5	2
valid_sources[0x19]	20521	1			T1	2		T2	38		T4	32
valid_sources[0x1a]	19408	1			T1	1		T2	36		T4	14
valid_sources[0x1b]	16126	1			T2	95		T4	18		T5	1
valid_sources[0x1c]	15028	1			T1	1		T2	31		T4	25
valid_sources[0x1d]	16300	1			T1	5		T2	59		T4	23
valid_sources[0x1e]	16451	1			T1	3		T2	29		T4	23
valid_sources[0x1f]	17281	1			T1	1		T2	27		T4	29
valid_sources[0x20]	19452	1			T1	2		T2	44		T4	25
valid_sources[0x21]	25021	1			T1	2		T2	47		T4	23
valid_sources[0x22]	16722	1			T1	6		T2	45		T4	17
valid_sources[0x23]	16380	1			T1	5		T2	23		T4	15
valid_sources[0x24]	14393	1			T2	24		T4	21		T16	23
valid_sources[0x25]	14836	1			T1	7		T2	30		T4	28
valid_sources[0x26]	19772	1			T1	1		T2	43		T4	9
valid_sources[0x27]	16764	1			T1	2		T2	46		T4	19
valid_sources[0x28]	16186	1			T1	2		T2	39		T4	23
valid_sources[0x29]	16135	1			T2	38		T4	18		T5	2
valid_sources[0x2a]	14592	1			T2	27		T4	17		T5	3
valid_sources[0x2b]	102395	1			T1	3		T2	39		T4	21
valid_sources[0x2c]	18870	1			T1	3		T2	34		T4	18
valid_sources[0x2d]	15776	1			T1	2		T2	15		T4	18
valid_sources[0x2e]	21437	1			T1	8		T2	29		T4	19
valid_sources[0x2f]	16207	1			T1	3		T2	32		T4	20
valid_sources[0x30]	17031	1			T1	1		T2	49		T4	24
valid_sources[0x31]	17708	1			T1	2		T2	37		T4	26
valid_sources[0x32]	15733	1			T1	3		T2	28		T4	13
valid_sources[0x33]	45000	1			T1	7		T2	34		T4	9
valid_sources[0x34]	18931	1			T1	6		T2	33		T4	27
valid_sources[0x35]	25991	1			T1	15		T2	32		T4	19
valid_sources[0x36]	19170	1			T1	3		T2	13		T4	24
valid_sources[0x37]	14904	1			T1	1		T2	33		T4	19
valid_sources[0x38]	14936	1			T1	4		T2	20		T4	34
valid_sources[0x39]	16861	1			T2	33		T4	17		T5	2
valid_sources[0x3a]	16172	1			T1	19		T2	20		T4	17
valid_sources[0x3b]	20662	1			T1	1		T2	24		T4	17
valid_sources[0x3c]	22391	1			T1	1		T2	26		T4	12
valid_sources[0x3d]	18660	1			T1	5		T2	48		T4	16
valid_sources[0x3e]	15509	1			T1	2		T2	23		T4	30
valid_sources[0x3f]	16753	1			T1	4		T2	17		T4	19
valid_sources[0x40]	16343	1			T1	9		T2	38		T4	19
valid_sources[0x41]	16074	1			T1	1		T2	37		T4	26
valid_sources[0x42]	22672	1			T1	4		T2	29		T4	12
valid_sources[0x43]	18585	1			T1	9		T2	29		T4	17
valid_sources[0x44]	15628	1			T1	7		T2	45		T4	20
valid_sources[0x45]	15261	1			T2	15		T4	26		T16	25
valid_sources[0x46]	16123	1			T1	10		T2	14		T4	19
valid_sources[0x47]	15256	1			T1	6		T2	83		T4	18
valid_sources[0x48]	15303	1			T1	2		T2	26		T4	13
valid_sources[0x49]	15110	1			T1	1		T2	31		T4	23
valid_sources[0x4a]	19562	1			T1	7		T2	7		T4	20
valid_sources[0x4b]	14682	1			T1	3		T2	21		T4	16
valid_sources[0x4c]	17423	1			T1	4		T2	73		T4	16
valid_sources[0x4d]	16452	1			T1	7		T2	15		T4	22
valid_sources[0x4e]	15336	1			T1	4		T2	39		T4	16
valid_sources[0x4f]	20788	1			T1	4		T2	51		T4	18
valid_sources[0x50]	14461	1			T2	39		T4	15		T5	4
valid_sources[0x51]	16799	1			T1	5		T2	55		T4	26
valid_sources[0x52]	15224	1			T1	8		T2	63		T4	15
valid_sources[0x53]	16491	1			T1	1		T2	62		T4	19
valid_sources[0x54]	14932	1			T1	1		T2	26		T4	16
valid_sources[0x55]	14886	1			T1	6		T2	47		T4	14
valid_sources[0x56]	15525	1			T1	9		T2	65		T4	25
valid_sources[0x57]	20552	1			T1	4		T2	46		T4	15
valid_sources[0x58]	21211	1			T1	7		T2	52		T4	23
valid_sources[0x59]	19811	1			T1	6		T2	39		T4	24
valid_sources[0x5a]	15807	1			T2	62		T4	29		T5	3
valid_sources[0x5b]	16878	1			T1	10		T2	22		T4	9
valid_sources[0x5c]	17838	1			T1	6		T2	95		T4	16
valid_sources[0x5d]	14727	1			T1	1		T2	48		T4	20
valid_sources[0x5e]	14950	1			T1	3		T2	29		T4	16
valid_sources[0x5f]	15052	1			T1	1		T2	30		T4	17
valid_sources[0x60]	15376	1			T1	4		T2	52		T4	28
valid_sources[0x61]	16573	1			T1	1		T2	67		T3	785
valid_sources[0x62]	15090	1			T1	6		T2	55		T4	15
valid_sources[0x63]	16904	1			T1	4		T2	14		T4	27
valid_sources[0x64]	15926	1			T1	10		T2	25		T4	19
valid_sources[0x65]	15509	1			T1	4		T2	80		T4	20
valid_sources[0x66]	17725	1			T1	3		T2	56		T4	9
valid_sources[0x67]	16212	1			T1	14		T2	23		T4	20
valid_sources[0x68]	15139	1			T2	41		T4	20		T16	31
valid_sources[0x69]	865489	1			T2	11		T4	13		T5	3
valid_sources[0x6a]	29613	1			T1	3		T2	7		T4	23
valid_sources[0x6b]	15594	1			T1	4		T2	55		T4	25
valid_sources[0x6c]	15376	1			T1	5		T2	37		T4	12
valid_sources[0x6d]	16073	1			T1	10		T2	29		T4	15
valid_sources[0x6e]	26564	1			T1	7		T2	49		T4	21
valid_sources[0x6f]	16765	1			T1	1		T2	11		T4	21
valid_sources[0x70]	15227	1			T1	1		T2	4		T4	13
valid_sources[0x71]	20495	1			T1	4		T2	18		T4	25
valid_sources[0x72]	24395	1			T1	5		T2	28		T4	15
valid_sources[0x73]	15842	1			T1	5		T2	12		T4	18
valid_sources[0x74]	15449	1			T1	1		T2	29		T4	23
valid_sources[0x75]	14297	1			T1	4		T2	27		T4	17
valid_sources[0x76]	33083	1			T1	3		T2	18		T4	21
valid_sources[0x77]	16447	1			T1	12		T2	67		T4	11
valid_sources[0x78]	15430	1			T2	41		T4	20		T5	3
valid_sources[0x79]	37181	1			T1	2		T2	34		T4	23
valid_sources[0x7a]	15108	1			T1	2		T2	41		T4	12
valid_sources[0x7b]	31706	1			T2	49		T4	31		T5	4
valid_sources[0x7c]	15294	1			T1	5		T2	34		T4	21
valid_sources[0x7d]	33586	1			T2	31		T4	29		T16	35
valid_sources[0x7e]	17285	1			T1	2		T2	55		T4	26
valid_sources[0x7f]	17095	1			T1	2		T2	22		T4	24
valid_sources[0x80]	14378	1			T2	45		T4	29		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

333974

1

T1

116

T2

184

T3

232

values[0x0]

all_enables

biggest_size

148299

1

T1

8

T2

26

T3

22

values[0x1]

all_enables

biggest_size

134020

1

T1

8

T2

10

T3

18