Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3355615	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

587873

1

T1

456

T2

205

T3

485

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3542359	1			T1	632		T2	428		T3	1191
values[0x0]	199121	1			T1	161		T2	77		T3	145
values[0x1]	202008	1			T1	158		T2	60		T3	154

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2292477	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1651011

1

T1

586

T2

290

T3

758

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30710	1			T1	3		T13	2		T4	9
valid_sources[0x01]	11875	1			T1	1		T13	2		T4	7
valid_sources[0x02]	15229	1			T1	2		T13	2		T4	4
valid_sources[0x03]	12268	1			T1	3		T2	6		T13	1
valid_sources[0x04]	12809	1			T1	3		T13	3		T4	6
valid_sources[0x05]	14149	1			T1	4		T2	4		T4	8
valid_sources[0x06]	14089	1			T1	4		T13	4		T4	6
valid_sources[0x07]	12360	1			T1	7		T4	4		T5	37
valid_sources[0x08]	19291	1			T1	5		T13	2		T4	7
valid_sources[0x09]	12156	1			T1	11		T13	2		T4	1
valid_sources[0x0a]	12918	1			T1	6		T4	9		T5	28
valid_sources[0x0b]	12801	1			T1	7		T13	1		T4	2
valid_sources[0x0c]	12322	1			T1	7		T13	1		T4	1
valid_sources[0x0d]	11854	1			T1	1		T2	1		T4	12
valid_sources[0x0e]	12603	1			T2	2		T13	3		T4	7
valid_sources[0x0f]	11706	1			T1	5		T13	2		T4	9
valid_sources[0x10]	14762	1			T1	13		T4	8		T14	4
valid_sources[0x11]	12347	1			T1	4		T13	1		T4	6
valid_sources[0x12]	12746	1			T1	1		T13	4		T4	3
valid_sources[0x13]	14440	1			T1	1		T13	7		T4	17
valid_sources[0x14]	11762	1			T1	2		T4	4		T5	27
valid_sources[0x15]	16261	1			T1	6		T13	2		T4	9
valid_sources[0x16]	12404	1			T1	1		T13	2		T4	6
valid_sources[0x17]	12672	1			T1	7		T13	2		T4	7
valid_sources[0x18]	11703	1			T1	2		T13	8		T4	6
valid_sources[0x19]	12250	1			T1	3		T13	5		T4	4
valid_sources[0x1a]	12038	1			T1	2		T13	7		T4	6
valid_sources[0x1b]	14667	1			T1	4		T2	5		T13	3
valid_sources[0x1c]	22865	1			T1	6		T13	6		T4	1
valid_sources[0x1d]	13627	1			T1	1		T2	5		T4	6
valid_sources[0x1e]	14061	1			T1	3		T13	4		T4	3
valid_sources[0x1f]	13066	1			T1	3		T2	3		T13	4
valid_sources[0x20]	12660	1			T1	7		T2	11		T13	5
valid_sources[0x21]	11952	1			T1	4		T2	4		T4	1
valid_sources[0x22]	13529	1			T13	1		T4	8		T5	24
valid_sources[0x23]	84478	1			T1	2		T13	2		T4	4
valid_sources[0x24]	13960	1			T1	8		T2	26		T13	5
valid_sources[0x25]	15519	1			T1	5		T13	1		T4	5
valid_sources[0x26]	12971	1			T1	5		T13	4		T4	6
valid_sources[0x27]	12196	1			T13	2		T4	5		T5	30
valid_sources[0x28]	13427	1			T1	3		T2	6		T13	2
valid_sources[0x29]	12091	1			T1	6		T13	11		T4	4
valid_sources[0x2a]	15240	1			T1	3		T13	3		T4	6
valid_sources[0x2b]	11682	1			T1	2		T13	3		T4	9
valid_sources[0x2c]	77875	1			T1	8		T13	4		T4	9
valid_sources[0x2d]	11737	1			T1	1		T2	2		T4	2
valid_sources[0x2e]	12875	1			T1	1		T4	5		T5	28
valid_sources[0x2f]	13905	1			T13	5		T4	3		T5	26
valid_sources[0x30]	15373	1			T2	2		T13	1		T4	5
valid_sources[0x31]	16301	1			T1	3		T13	5		T4	5
valid_sources[0x32]	12805	1			T13	2		T4	5		T5	40
valid_sources[0x33]	12412	1			T1	2		T13	4		T4	9
valid_sources[0x34]	13678	1			T1	1		T13	1		T4	7
valid_sources[0x35]	12479	1			T1	2		T2	1		T13	8
valid_sources[0x36]	12266	1			T1	3		T13	5		T4	3
valid_sources[0x37]	13821	1			T1	2		T13	1		T4	5
valid_sources[0x38]	14124	1			T1	2		T13	3		T4	3
valid_sources[0x39]	14144	1			T1	2		T4	5		T14	1
valid_sources[0x3a]	37494	1			T1	6		T2	4		T13	2
valid_sources[0x3b]	21234	1			T2	28		T13	5		T4	6
valid_sources[0x3c]	12695	1			T1	2		T13	2		T4	5
valid_sources[0x3d]	12243	1			T1	2		T4	5		T14	1
valid_sources[0x3e]	11752	1			T1	4		T2	1		T13	1
valid_sources[0x3f]	16034	1			T1	1		T13	1		T5	35
valid_sources[0x40]	17790	1			T1	2		T4	7		T15	2290
valid_sources[0x41]	12757	1			T1	7		T13	1		T4	10
valid_sources[0x42]	14493	1			T1	2		T2	2		T13	1
valid_sources[0x43]	13451	1			T1	3		T2	13		T13	3
valid_sources[0x44]	12875	1			T1	2		T13	4		T4	2
valid_sources[0x45]	12899	1			T1	8		T2	1		T13	1
valid_sources[0x46]	13744	1			T1	9		T2	11		T13	1
valid_sources[0x47]	12471	1			T1	3		T4	5		T5	31
valid_sources[0x48]	13076	1			T1	5		T2	1		T13	2
valid_sources[0x49]	14275	1			T1	2		T13	2		T4	2
valid_sources[0x4a]	12020	1			T1	8		T2	7		T4	8
valid_sources[0x4b]	12355	1			T1	3		T13	4		T4	8
valid_sources[0x4c]	11953	1			T1	1		T13	1		T4	12
valid_sources[0x4d]	13186	1			T1	2		T4	6		T5	24
valid_sources[0x4e]	12350	1			T1	3		T4	10		T14	3
valid_sources[0x4f]	12174	1			T1	5		T13	5		T4	5
valid_sources[0x50]	24571	1			T1	10		T2	5		T13	3
valid_sources[0x51]	11858	1			T1	10		T13	4		T4	1
valid_sources[0x52]	12131	1			T1	1		T13	2		T4	9
valid_sources[0x53]	11909	1			T1	5		T13	2		T4	3
valid_sources[0x54]	13828	1			T2	14		T4	6		T5	26
valid_sources[0x55]	19095	1			T1	3		T13	1		T4	3
valid_sources[0x56]	13029	1			T2	6		T4	13		T14	3
valid_sources[0x57]	12316	1			T1	16		T13	5		T4	6
valid_sources[0x58]	13119	1			T1	1		T2	3		T4	4
valid_sources[0x59]	19998	1			T1	3		T13	7		T4	2
valid_sources[0x5a]	16439	1			T1	6		T2	22		T13	3
valid_sources[0x5b]	12573	1			T2	4		T13	1		T4	10
valid_sources[0x5c]	12882	1			T2	14		T13	3		T4	2
valid_sources[0x5d]	17609	1			T13	4		T4	6		T5	23
valid_sources[0x5e]	14930	1			T1	3		T13	3		T4	3
valid_sources[0x5f]	16752	1			T1	6		T2	1		T13	1
valid_sources[0x60]	12020	1			T1	3		T2	10		T4	2
valid_sources[0x61]	15497	1			T1	3		T13	1		T4	3
valid_sources[0x62]	15038	1			T1	3		T2	1		T13	1
valid_sources[0x63]	12002	1			T13	2		T4	3		T5	27
valid_sources[0x64]	26063	1			T1	1		T13	6		T4	7
valid_sources[0x65]	13881	1			T1	2		T4	5		T5	25
valid_sources[0x66]	15001	1			T1	3		T13	6		T4	12
valid_sources[0x67]	12354	1			T1	4		T2	2		T4	6
valid_sources[0x68]	12074	1			T1	8		T13	3		T4	8
valid_sources[0x69]	13779	1			T1	1		T2	1		T13	3
valid_sources[0x6a]	14711	1			T1	10		T2	2		T13	1
valid_sources[0x6b]	12764	1			T1	5		T13	1		T4	4
valid_sources[0x6c]	12348	1			T1	1		T13	6		T4	12
valid_sources[0x6d]	14301	1			T1	7		T13	6		T4	9
valid_sources[0x6e]	12234	1			T1	2		T13	1		T4	8
valid_sources[0x6f]	18518	1			T1	6		T13	2		T4	7
valid_sources[0x70]	16158	1			T1	4		T13	15		T4	2
valid_sources[0x71]	21158	1			T1	4		T4	7		T5	33
valid_sources[0x72]	19259	1			T1	9		T13	4		T4	2
valid_sources[0x73]	18284	1			T1	3		T4	2		T14	2
valid_sources[0x74]	15980	1			T1	2		T13	3		T4	9
valid_sources[0x75]	11901	1			T1	2		T13	2		T4	5
valid_sources[0x76]	46070	1			T1	1		T13	1		T4	9
valid_sources[0x77]	12536	1			T2	8		T4	8		T5	32
valid_sources[0x78]	12873	1			T1	5		T4	2		T5	25
valid_sources[0x79]	12156	1			T1	4		T2	4		T4	12
valid_sources[0x7a]	16319	1			T1	3		T2	11		T13	6
valid_sources[0x7b]	11829	1			T1	8		T13	1		T4	2
valid_sources[0x7c]	47945	1			T1	1		T13	3		T4	7
valid_sources[0x7d]	14169	1			T1	6		T13	4		T4	5
valid_sources[0x7e]	11714	1			T1	1		T13	3		T4	9
valid_sources[0x7f]	11767	1			T1	2		T2	7		T4	3
valid_sources[0x80]	15282	1			T1	4		T2	3		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

315583

1

T1

226

T2

161

T3

292

values[0x0]

all_enables

biggest_size

143076

1

T1

127

T2

36

T3

92

values[0x1]

all_enables

biggest_size

129214

1

T1

103

T2

8

T3

101