Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	26851229	14560	0	0
attest_sw_binding_0_rd_A	26851229	2030	0	0
attest_sw_binding_1_rd_A	26851229	2116	0	0
attest_sw_binding_2_rd_A	26851229	2071	0	0
attest_sw_binding_3_rd_A	26851229	2154	0	0
attest_sw_binding_4_rd_A	26851229	2233	0	0
attest_sw_binding_5_rd_A	26851229	2284	0	0
attest_sw_binding_6_rd_A	26851229	2230	0	0
attest_sw_binding_7_rd_A	26851229	2057	0	0
intr_enable_rd_A	26851229	2590	0	0
key_version_rd_A	26851229	2321	0	0
max_creator_key_ver_regwen_rd_A	26851229	2058	0	0
max_owner_int_key_ver_regwen_rd_A	26851229	2040	0	0
max_owner_key_ver_regwen_rd_A	26851229	2201	0	0
reseed_interval_regwen_rd_A	26851229	2287	0	0
salt_0_rd_A	26851229	2192	0	0
salt_1_rd_A	26851229	2200	0	0
salt_2_rd_A	26851229	2175	0	0
salt_3_rd_A	26851229	2052	0	0
salt_4_rd_A	26851229	2091	0	0
salt_5_rd_A	26851229	2108	0	0
salt_6_rd_A	26851229	2194	0	0
salt_7_rd_A	26851229	2225	0	0
sealing_sw_binding_0_rd_A	26851229	2117	0	0
sealing_sw_binding_1_rd_A	26851229	2264	0	0
sealing_sw_binding_2_rd_A	26851229	2048	0	0
sealing_sw_binding_3_rd_A	26851229	2158	0	0
sealing_sw_binding_4_rd_A	26851229	2214	0	0
sealing_sw_binding_5_rd_A	26851229	2200	0	0
sealing_sw_binding_6_rd_A	26851229	2111	0	0
sealing_sw_binding_7_rd_A	26851229	2049	0	0
sideload_clear_rd_A	26851229	2196	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	14560	0	0
T6	311338	0	0	0
T21	153205	0	0	0
T36	7704	0	0	0
T48	0	199	0	0
T62	8800	0	0	0
T64	0	1100	0	0
T65	17923	0	0	0
T73	99627	0	0	0
T74	3534	0	0	0
T75	3258	0	0	0
T99	26462	26	0	0
T100	0	128	0	0
T104	0	895	0	0
T112	0	327	0	0
T113	0	40	0	0
T114	0	146	0	0
T115	0	347	0	0
T116	0	281	0	0
T117	9097	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2030	0	0
T48	22780	0	0	0
T100	51374	57	0	0
T104	37203	0	0	0
T109	0	92	0	0
T113	0	22	0	0
T116	0	28	0	0
T136	0	31	0	0
T146	1730	0	0	0
T170	0	3	0	0
T171	0	36	0	0
T172	0	4	0	0
T173	0	211	0	0
T174	0	6	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2116	0	0
T48	22780	0	0	0
T100	51374	45	0	0
T104	37203	0	0	0
T109	0	87	0	0
T113	0	47	0	0
T116	0	42	0	0
T129	0	21	0	0
T136	0	47	0	0
T146	1730	0	0	0
T170	0	18	0	0
T171	0	41	0	0
T172	0	3	0	0
T173	0	194	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2071	0	0
T48	22780	0	0	0
T100	51374	38	0	0
T104	37203	0	0	0
T109	0	84	0	0
T113	0	14	0	0
T116	0	42	0	0
T129	0	35	0	0
T136	0	38	0	0
T146	1730	0	0	0
T170	0	30	0	0
T171	0	31	0	0
T173	0	221	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	1	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2154	0	0
T48	22780	0	0	0
T100	51374	82	0	0
T104	37203	0	0	0
T113	0	50	0	0
T116	0	43	0	0
T129	0	19	0	0
T136	0	37	0	0
T146	1730	0	0	0
T170	0	16	0	0
T171	0	34	0	0
T173	0	241	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	20	0	0
T182	0	6	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2233	0	0
T48	22780	0	0	0
T100	51374	70	0	0
T104	37203	0	0	0
T109	0	96	0	0
T113	0	27	0	0
T116	0	22	0	0
T129	0	23	0	0
T136	0	41	0	0
T146	1730	0	0	0
T170	0	9	0	0
T171	0	27	0	0
T173	0	246	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	12	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2284	0	0
T48	22780	0	0	0
T100	51374	60	0	0
T104	37203	0	0	0
T113	0	12	0	0
T116	0	5	0	0
T129	0	54	0	0
T136	0	35	0	0
T146	1730	0	0	0
T170	0	12	0	0
T171	0	24	0	0
T172	0	1	0	0
T173	0	239	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	10	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2230	0	0
T48	22780	0	0	0
T100	51374	52	0	0
T104	37203	0	0	0
T113	0	41	0	0
T116	0	27	0	0
T129	0	3	0	0
T136	0	53	0	0
T146	1730	0	0	0
T170	0	8	0	0
T171	0	26	0	0
T172	0	5	0	0
T173	0	238	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	6	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2057	0	0
T48	22780	0	0	0
T100	51374	53	0	0
T104	37203	0	0	0
T113	0	30	0	0
T116	0	27	0	0
T129	0	6	0	0
T136	0	49	0	0
T146	1730	0	0	0
T170	0	10	0	0
T171	0	36	0	0
T172	0	15	0	0
T173	0	220	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2590	0	0
T48	22780	0	0	0
T100	51374	81	0	0
T104	37203	0	0	0
T113	0	35	0	0
T116	0	35	0	0
T146	1730	0	0	0
T170	0	32	0	0
T171	0	38	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T183	0	33	0	0
T184	0	38	0	0
T185	0	7	0	0
T186	0	41	0	0
T187	0	32	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2321	0	0
T48	22780	0	0	0
T100	51374	60	0	0
T104	37203	0	0	0
T109	0	120	0	0
T113	0	37	0	0
T116	0	13	0	0
T129	0	47	0	0
T136	0	29	0	0
T146	1730	0	0	0
T170	0	23	0	0
T171	0	36	0	0
T173	0	204	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	9	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2058	0	0
T48	22780	0	0	0
T100	51374	58	0	0
T104	37203	0	0	0
T113	0	17	0	0
T116	0	64	0	0
T129	0	29	0	0
T136	0	28	0	0
T146	1730	0	0	0
T170	0	24	0	0
T171	0	26	0	0
T172	0	14	0	0
T173	0	226	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	8	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2040	0	0
T48	22780	0	0	0
T100	51374	38	0	0
T104	37203	0	0	0
T113	0	36	0	0
T116	0	30	0	0
T129	0	21	0	0
T136	0	25	0	0
T146	1730	0	0	0
T170	0	5	0	0
T171	0	45	0	0
T173	0	241	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	2	0	0
T188	0	6	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2201	0	0
T48	22780	0	0	0
T100	51374	74	0	0
T104	37203	0	0	0
T113	0	36	0	0
T116	0	42	0	0
T129	0	4	0	0
T136	0	37	0	0
T146	1730	0	0	0
T170	0	31	0	0
T171	0	43	0	0
T172	0	1	0	0
T173	0	215	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	4	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2287	0	0
T48	22780	0	0	0
T100	51374	60	0	0
T104	37203	0	0	0
T109	0	96	0	0
T113	0	27	0	0
T116	0	57	0	0
T129	0	30	0	0
T136	0	35	0	0
T146	1730	0	0	0
T170	0	16	0	0
T171	0	39	0	0
T173	0	230	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	15	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2192	0	0
T48	22780	0	0	0
T100	51374	69	0	0
T104	37203	0	0	0
T109	0	115	0	0
T113	0	57	0	0
T116	0	7	0	0
T129	0	25	0	0
T136	0	50	0	0
T146	1730	0	0	0
T170	0	21	0	0
T171	0	26	0	0
T173	0	194	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	2	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2200	0	0
T48	22780	0	0	0
T100	51374	68	0	0
T104	37203	0	0	0
T109	0	115	0	0
T113	0	31	0	0
T116	0	27	0	0
T129	0	50	0	0
T136	0	47	0	0
T146	1730	0	0	0
T170	0	10	0	0
T171	0	35	0	0
T173	0	242	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	3	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2175	0	0
T48	22780	0	0	0
T100	51374	39	0	0
T104	37203	0	0	0
T109	0	121	0	0
T113	0	26	0	0
T116	0	64	0	0
T129	0	24	0	0
T136	0	43	0	0
T146	1730	0	0	0
T170	0	6	0	0
T171	0	47	0	0
T173	0	206	0	0
T174	0	20	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2052	0	0
T48	22780	0	0	0
T100	51374	65	0	0
T104	37203	0	0	0
T113	0	26	0	0
T116	0	21	0	0
T129	0	8	0	0
T136	0	31	0	0
T146	1730	0	0	0
T170	0	13	0	0
T171	0	20	0	0
T172	0	4	0	0
T173	0	259	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	1	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2091	0	0
T48	22780	0	0	0
T100	51374	58	0	0
T104	37203	0	0	0
T113	0	29	0	0
T116	0	13	0	0
T129	0	23	0	0
T136	0	22	0	0
T146	1730	0	0	0
T170	0	22	0	0
T171	0	31	0	0
T172	0	7	0	0
T173	0	221	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	8	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2108	0	0
T48	22780	0	0	0
T100	51374	54	0	0
T104	37203	0	0	0
T113	0	27	0	0
T116	0	20	0	0
T129	0	36	0	0
T136	0	42	0	0
T146	1730	0	0	0
T170	0	15	0	0
T171	0	42	0	0
T172	0	4	0	0
T173	0	225	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	15	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2194	0	0
T48	22780	0	0	0
T100	51374	75	0	0
T104	37203	0	0	0
T113	0	37	0	0
T116	0	29	0	0
T129	0	26	0	0
T136	0	30	0	0
T146	1730	0	0	0
T170	0	14	0	0
T171	0	35	0	0
T172	0	1	0	0
T173	0	223	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	6	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2225	0	0
T48	22780	0	0	0
T100	51374	63	0	0
T104	37203	0	0	0
T113	0	23	0	0
T116	0	20	0	0
T129	0	39	0	0
T136	0	35	0	0
T146	1730	0	0	0
T170	0	13	0	0
T171	0	53	0	0
T172	0	6	0	0
T173	0	202	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	6	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2117	0	0
T48	22780	0	0	0
T100	51374	85	0	0
T104	37203	0	0	0
T109	0	72	0	0
T113	0	28	0	0
T116	0	20	0	0
T129	0	42	0	0
T136	0	35	0	0
T146	1730	0	0	0
T170	0	16	0	0
T171	0	55	0	0
T173	0	195	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	7	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2264	0	0
T48	22780	0	0	0
T100	51374	55	0	0
T104	37203	0	0	0
T109	0	98	0	0
T113	0	41	0	0
T116	0	24	0	0
T129	0	49	0	0
T136	0	31	0	0
T146	1730	0	0	0
T170	0	24	0	0
T171	0	31	0	0
T173	0	252	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	7	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2048	0	0
T48	22780	0	0	0
T100	51374	45	0	0
T104	37203	0	0	0
T109	0	97	0	0
T113	0	19	0	0
T116	0	30	0	0
T129	0	26	0	0
T136	0	29	0	0
T146	1730	0	0	0
T170	0	19	0	0
T171	0	32	0	0
T172	0	3	0	0
T173	0	217	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2158	0	0
T48	22780	0	0	0
T100	51374	50	0	0
T104	37203	0	0	0
T109	0	86	0	0
T113	0	37	0	0
T116	0	13	0	0
T129	0	21	0	0
T136	0	44	0	0
T146	1730	0	0	0
T170	0	20	0	0
T171	0	57	0	0
T173	0	240	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	8	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2214	0	0
T48	22780	0	0	0
T100	51374	53	0	0
T104	37203	0	0	0
T109	0	118	0	0
T113	0	17	0	0
T116	0	38	0	0
T136	0	49	0	0
T146	1730	0	0	0
T170	0	33	0	0
T171	0	30	0	0
T172	0	4	0	0
T173	0	186	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	8	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2200	0	0
T48	22780	0	0	0
T100	51374	62	0	0
T104	37203	0	0	0
T109	0	117	0	0
T113	0	25	0	0
T116	0	41	0	0
T129	0	22	0	0
T136	0	37	0	0
T146	1730	0	0	0
T170	0	19	0	0
T171	0	32	0	0
T173	0	197	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	2	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2111	0	0
T48	22780	0	0	0
T100	51374	58	0	0
T104	37203	0	0	0
T109	0	118	0	0
T113	0	22	0	0
T116	0	59	0	0
T129	0	27	0	0
T136	0	48	0	0
T146	1730	0	0	0
T170	0	16	0	0
T171	0	31	0	0
T173	0	192	0	0
T174	0	10	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2049	0	0
T48	22780	0	0	0
T100	51374	38	0	0
T104	37203	0	0	0
T113	0	34	0	0
T116	0	19	0	0
T129	0	8	0	0
T136	0	19	0	0
T146	1730	0	0	0
T170	0	15	0	0
T171	0	49	0	0
T172	0	8	0	0
T173	0	220	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0
T181	0	12	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26851229	2196	0	0
T48	22780	0	0	0
T100	51374	72	0	0
T104	37203	0	0	0
T109	0	110	0	0
T113	0	29	0	0
T116	0	21	0	0
T129	0	27	0	0
T136	0	49	0	0
T146	1730	0	0	0
T170	0	23	0	0
T171	0	39	0	0
T172	0	21	0	0
T173	0	242	0	0
T175	3376	0	0	0
T176	22007	0	0	0
T177	61081	0	0	0
T178	4370	0	0	0
T179	13669	0	0	0
T180	1653	0	0	0