Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3905965	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

595718

1

T1

32

T2

324

T3

164

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4097822	1			T1	194		T2	2098		T3	1087
values[0x0]	200282	1			T1	15		T2	120		T3	52
values[0x1]	203579	1			T1	20		T2	134		T3	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2660516	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1841167

1

T1

82

T2

925

T3

466

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14947	1			T4	12		T5	438		T15	4
valid_sources[0x01]	14502	1			T4	4		T5	419		T15	6
valid_sources[0x02]	15170	1			T4	7		T5	419		T15	1
valid_sources[0x03]	15222	1			T4	5		T5	399		T15	10
valid_sources[0x04]	14841	1			T4	11		T5	514		T15	1
valid_sources[0x05]	15077	1			T4	7		T5	443		T15	14
valid_sources[0x06]	14922	1			T4	9		T5	375		T15	3
valid_sources[0x07]	17807	1			T3	1173		T4	5		T5	461
valid_sources[0x08]	15648	1			T4	4		T5	418		T15	4
valid_sources[0x09]	17315	1			T4	7		T5	389		T16	13
valid_sources[0x0a]	16140	1			T4	6		T5	430		T15	11
valid_sources[0x0b]	14144	1			T4	8		T5	351		T15	5
valid_sources[0x0c]	15888	1			T4	13		T5	422		T15	4
valid_sources[0x0d]	14283	1			T4	9		T5	330		T15	6
valid_sources[0x0e]	14732	1			T4	12		T5	341		T15	2
valid_sources[0x0f]	17281	1			T4	10		T5	451		T15	3
valid_sources[0x10]	14242	1			T4	9		T5	409		T15	5
valid_sources[0x11]	17823	1			T4	5		T5	413		T15	4
valid_sources[0x12]	14599	1			T4	5		T5	398		T15	17
valid_sources[0x13]	16387	1			T4	8		T5	522		T15	10
valid_sources[0x14]	17094	1			T4	4		T5	461		T15	2
valid_sources[0x15]	25535	1			T4	9		T5	383		T15	2
valid_sources[0x16]	15061	1			T4	10		T5	375		T15	2
valid_sources[0x17]	14216	1			T4	11		T5	395		T15	10
valid_sources[0x18]	18317	1			T4	11		T5	401		T16	2
valid_sources[0x19]	14565	1			T4	9		T5	454		T15	2
valid_sources[0x1a]	24630	1			T4	9		T5	457		T16	28
valid_sources[0x1b]	16165	1			T4	8		T5	395		T15	7
valid_sources[0x1c]	15168	1			T4	8		T5	465		T15	5
valid_sources[0x1d]	18758	1			T4	6		T5	421		T15	4
valid_sources[0x1e]	14155	1			T4	9		T5	376		T15	4
valid_sources[0x1f]	15432	1			T4	10		T5	402		T15	7
valid_sources[0x20]	18151	1			T4	7		T5	382		T15	15
valid_sources[0x21]	14477	1			T4	7		T5	459		T15	14
valid_sources[0x22]	15064	1			T4	8		T5	397		T16	42
valid_sources[0x23]	14596	1			T4	7		T5	359		T15	5
valid_sources[0x24]	15835	1			T4	10		T5	427		T15	6
valid_sources[0x25]	14823	1			T4	13		T5	386		T15	5
valid_sources[0x26]	60424	1			T4	6		T13	702		T5	415
valid_sources[0x27]	16487	1			T4	8		T5	359		T15	1
valid_sources[0x28]	14361	1			T4	14		T5	344		T15	5
valid_sources[0x29]	14437	1			T4	8		T5	441		T15	9
valid_sources[0x2a]	16027	1			T4	6		T5	425		T15	2
valid_sources[0x2b]	14447	1			T4	8		T5	332		T16	9
valid_sources[0x2c]	26514	1			T4	9		T5	382		T15	4
valid_sources[0x2d]	15446	1			T4	1		T5	432		T15	4
valid_sources[0x2e]	17116	1			T4	13		T5	405		T15	17
valid_sources[0x2f]	16757	1			T4	9		T5	375		T15	2
valid_sources[0x30]	15374	1			T4	5		T5	417		T15	1
valid_sources[0x31]	15366	1			T4	11		T5	457		T15	2
valid_sources[0x32]	15896	1			T4	5		T5	459		T15	1
valid_sources[0x33]	16579	1			T4	16		T5	437		T15	8
valid_sources[0x34]	14025	1			T4	8		T5	401		T15	16
valid_sources[0x35]	16860	1			T4	11		T5	471		T15	2
valid_sources[0x36]	16035	1			T4	9		T5	424		T15	9
valid_sources[0x37]	14686	1			T4	8		T5	439		T15	1
valid_sources[0x38]	16106	1			T4	9		T5	348		T16	22
valid_sources[0x39]	14371	1			T4	8		T5	390		T15	5
valid_sources[0x3a]	20155	1			T4	10		T5	432		T15	1
valid_sources[0x3b]	14177	1			T4	3		T5	343		T15	4
valid_sources[0x3c]	17364	1			T4	6		T5	409		T16	15
valid_sources[0x3d]	14326	1			T4	13		T5	438		T15	10
valid_sources[0x3e]	13761	1			T4	7		T5	359		T16	39
valid_sources[0x3f]	13899	1			T4	8		T5	415		T15	6
valid_sources[0x40]	16764	1			T4	7		T5	368		T15	6
valid_sources[0x41]	14946	1			T4	12		T5	421		T15	6
valid_sources[0x42]	14256	1			T4	8		T5	348		T15	4
valid_sources[0x43]	14846	1			T4	6		T5	491		T16	13
valid_sources[0x44]	15855	1			T4	9		T5	379		T15	7
valid_sources[0x45]	15376	1			T4	4		T5	381		T15	2
valid_sources[0x46]	14340	1			T4	6		T5	418		T15	14
valid_sources[0x47]	13903	1			T4	6		T5	383		T15	9
valid_sources[0x48]	14817	1			T4	8		T5	500		T15	5
valid_sources[0x49]	14188	1			T4	4		T5	454		T15	8
valid_sources[0x4a]	14582	1			T4	9		T5	372		T16	7
valid_sources[0x4b]	14591	1			T4	14		T5	396		T15	2
valid_sources[0x4c]	14237	1			T4	12		T5	414		T15	1
valid_sources[0x4d]	15089	1			T4	4		T5	391		T15	5
valid_sources[0x4e]	15419	1			T4	1		T5	388		T15	2
valid_sources[0x4f]	18192	1			T4	6		T5	353		T15	2
valid_sources[0x50]	14568	1			T4	10		T5	424		T15	4
valid_sources[0x51]	15215	1			T4	9		T5	420		T15	1
valid_sources[0x52]	38199	1			T4	8		T5	358		T15	13
valid_sources[0x53]	13992	1			T4	11		T5	461		T15	2
valid_sources[0x54]	15929	1			T4	8		T5	399		T15	5
valid_sources[0x55]	14684	1			T4	11		T5	425		T15	7
valid_sources[0x56]	14429	1			T4	5		T5	355		T15	4
valid_sources[0x57]	15494	1			T4	6		T5	410		T15	3
valid_sources[0x58]	16381	1			T4	8		T5	478		T15	12
valid_sources[0x59]	13800	1			T4	8		T5	426		T16	12
valid_sources[0x5a]	35594	1			T4	13		T5	403		T15	8
valid_sources[0x5b]	14199	1			T4	17		T5	439		T15	1
valid_sources[0x5c]	16188	1			T4	8		T5	372		T15	2
valid_sources[0x5d]	14481	1			T4	2		T5	378		T15	9
valid_sources[0x5e]	19190	1			T4	10		T5	462		T15	2
valid_sources[0x5f]	18062	1			T2	2352		T4	8		T5	366
valid_sources[0x60]	14572	1			T4	9		T5	406		T16	19
valid_sources[0x61]	14209	1			T4	4		T5	449		T15	8
valid_sources[0x62]	14862	1			T4	10		T5	411		T15	1
valid_sources[0x63]	52132	1			T4	6		T5	372		T15	6
valid_sources[0x64]	14493	1			T4	9		T5	471		T16	33
valid_sources[0x65]	14548	1			T4	3		T5	471		T15	3
valid_sources[0x66]	15046	1			T4	7		T5	470		T15	8
valid_sources[0x67]	14934	1			T4	3		T5	484		T15	2
valid_sources[0x68]	18572	1			T4	9		T5	450		T15	7
valid_sources[0x69]	14192	1			T4	15		T5	440		T16	15
valid_sources[0x6a]	14017	1			T4	10		T5	338		T15	2
valid_sources[0x6b]	13809	1			T4	9		T5	424		T15	4
valid_sources[0x6c]	14309	1			T4	8		T5	423		T15	1
valid_sources[0x6d]	38383	1			T4	7		T5	401		T15	10
valid_sources[0x6e]	28829	1			T4	9		T5	379		T15	2
valid_sources[0x6f]	15003	1			T4	10		T5	409		T15	3
valid_sources[0x70]	16885	1			T4	3		T5	483		T16	34
valid_sources[0x71]	22556	1			T4	9		T5	377		T16	3
valid_sources[0x72]	13967	1			T4	15		T5	412		T15	6
valid_sources[0x73]	18165	1			T4	2		T5	353		T15	1
valid_sources[0x74]	15121	1			T4	4		T5	342		T16	6
valid_sources[0x75]	15161	1			T4	10		T5	383		T15	12
valid_sources[0x76]	19728	1			T4	4		T5	468		T15	2
valid_sources[0x77]	19038	1			T4	11		T5	443		T16	3
valid_sources[0x78]	14359	1			T4	8		T5	447		T15	1
valid_sources[0x79]	14514	1			T4	6		T5	439		T15	11
valid_sources[0x7a]	14234	1			T4	6		T5	378		T15	10
valid_sources[0x7b]	15860	1			T4	13		T5	381		T15	13
valid_sources[0x7c]	16332	1			T4	8		T5	436		T15	3
valid_sources[0x7d]	19855	1			T4	5		T5	449		T15	2
valid_sources[0x7e]	16771	1			T4	8		T5	404		T16	36
valid_sources[0x7f]	14825	1			T4	12		T5	357		T15	6
valid_sources[0x80]	15324	1			T4	13		T5	454		T15	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

321091

1

T1

18

T2

170

T3

132

values[0x0]

all_enables

biggest_size

144356

1

T1

8

T2

77

T3

23

values[0x1]

all_enables

biggest_size

130271

1

T1

6

T2

77

T3

9