Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	31024013	12770	0	0
attest_sw_binding_0_rd_A	31024013	1564	0	0
attest_sw_binding_1_rd_A	31024013	1673	0	0
attest_sw_binding_2_rd_A	31024013	1720	0	0
attest_sw_binding_3_rd_A	31024013	1677	0	0
attest_sw_binding_4_rd_A	31024013	1578	0	0
attest_sw_binding_5_rd_A	31024013	1576	0	0
attest_sw_binding_6_rd_A	31024013	1503	0	0
attest_sw_binding_7_rd_A	31024013	1579	0	0
intr_enable_rd_A	31024013	2268	0	0
key_version_rd_A	31024013	1602	0	0
max_creator_key_ver_regwen_rd_A	31024013	1569	0	0
max_owner_int_key_ver_regwen_rd_A	31024013	1729	0	0
max_owner_key_ver_regwen_rd_A	31024013	1760	0	0
reseed_interval_regwen_rd_A	31024013	1695	0	0
salt_0_rd_A	31024013	1602	0	0
salt_1_rd_A	31024013	1673	0	0
salt_2_rd_A	31024013	1791	0	0
salt_3_rd_A	31024013	1628	0	0
salt_4_rd_A	31024013	1689	0	0
salt_5_rd_A	31024013	1693	0	0
salt_6_rd_A	31024013	1544	0	0
salt_7_rd_A	31024013	1666	0	0
sealing_sw_binding_0_rd_A	31024013	1596	0	0
sealing_sw_binding_1_rd_A	31024013	1534	0	0
sealing_sw_binding_2_rd_A	31024013	1668	0	0
sealing_sw_binding_3_rd_A	31024013	1651	0	0
sealing_sw_binding_4_rd_A	31024013	1587	0	0
sealing_sw_binding_5_rd_A	31024013	1732	0	0
sealing_sw_binding_6_rd_A	31024013	1582	0	0
sealing_sw_binding_7_rd_A	31024013	1711	0	0
sideload_clear_rd_A	31024013	1620	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	12770	0	0
T6	0	123	0	0
T24	16904	0	0	0
T41	41279	0	0	0
T54	18163	47	0	0
T58	0	751	0	0
T71	10072	0	0	0
T89	10768	0	0	0
T98	753	0	0	0
T104	0	453	0	0
T114	0	119	0	0
T115	0	538	0	0
T116	0	585	0	0
T117	0	593	0	0
T119	2720	0	0	0
T121	4710	0	0	0
T122	1236	0	0	0
T123	2836	0	0	0
T124	0	385	0	0
T125	0	61	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1564	0	0
T6	74197	84	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	15	0	0
T110	0	51	0	0
T134	0	6	0	0
T149	2844	0	0	0
T159	0	51	0	0
T167	0	45	0	0
T168	0	13	0	0
T169	0	11	0	0
T170	0	10	0	0
T171	0	5	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1673	0	0
T6	74197	76	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	17	0	0
T110	0	59	0	0
T134	0	6	0	0
T149	2844	0	0	0
T159	0	36	0	0
T167	0	53	0	0
T168	0	50	0	0
T169	0	8	0	0
T170	0	10	0	0
T171	0	5	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1720	0	0
T6	74197	87	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	7	0	0
T110	0	44	0	0
T134	0	15	0	0
T149	2844	0	0	0
T150	0	30	0	0
T159	0	51	0	0
T167	0	49	0	0
T168	0	34	0	0
T169	0	8	0	0
T170	0	8	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1677	0	0
T6	74197	83	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	17	0	0
T110	0	44	0	0
T134	0	2	0	0
T149	2844	0	0	0
T150	0	23	0	0
T159	0	33	0	0
T167	0	66	0	0
T168	0	38	0	0
T169	0	19	0	0
T170	0	8	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1578	0	0
T6	74197	91	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	22	0	0
T110	0	42	0	0
T134	0	6	0	0
T149	2844	0	0	0
T159	0	61	0	0
T167	0	29	0	0
T168	0	45	0	0
T169	0	10	0	0
T170	0	2	0	0
T171	0	4	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1576	0	0
T6	74197	44	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	1	0	0
T134	0	11	0	0
T149	2844	0	0	0
T159	0	62	0	0
T167	0	51	0	0
T168	0	14	0	0
T169	0	1	0	0
T170	0	8	0	0
T171	0	1	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0
T176	0	9	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1503	0	0
T6	74197	48	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	23	0	0
T110	0	60	0	0
T134	0	7	0	0
T149	2844	0	0	0
T159	0	43	0	0
T167	0	59	0	0
T168	0	20	0	0
T169	0	7	0	0
T170	0	25	0	0
T171	0	5	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1579	0	0
T6	74197	77	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	12	0	0
T110	0	47	0	0
T134	0	4	0	0
T149	2844	0	0	0
T159	0	48	0	0
T167	0	41	0	0
T168	0	61	0	0
T169	0	11	0	0
T170	0	13	0	0
T171	0	10	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	2268	0	0
T6	74197	71	0	0
T34	3933	0	0	0
T42	0	16	0	0
T62	0	13	0	0
T77	0	36	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T130	0	18	0	0
T149	2844	0	0	0
T167	0	56	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0
T177	0	20	0	0
T178	0	26	0	0
T179	0	2	0	0
T180	0	53	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1602	0	0
T6	74197	70	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	11	0	0
T110	0	64	0	0
T134	0	5	0	0
T149	2844	0	0	0
T159	0	49	0	0
T167	0	42	0	0
T168	0	18	0	0
T169	0	1	0	0
T170	0	6	0	0
T171	0	5	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1569	0	0
T6	74197	62	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	7	0	0
T110	0	52	0	0
T134	0	12	0	0
T149	2844	0	0	0
T159	0	46	0	0
T167	0	47	0	0
T168	0	20	0	0
T169	0	5	0	0
T170	0	15	0	0
T171	0	6	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1729	0	0
T6	74197	55	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	16	0	0
T110	0	69	0	0
T134	0	12	0	0
T149	2844	0	0	0
T159	0	46	0	0
T167	0	38	0	0
T168	0	38	0	0
T169	0	17	0	0
T170	0	1	0	0
T171	0	4	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1760	0	0
T6	74197	58	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	20	0	0
T110	0	44	0	0
T134	0	10	0	0
T149	2844	0	0	0
T159	0	81	0	0
T167	0	42	0	0
T168	0	32	0	0
T169	0	12	0	0
T170	0	7	0	0
T171	0	1	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1695	0	0
T6	74197	56	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	23	0	0
T110	0	53	0	0
T134	0	8	0	0
T149	2844	0	0	0
T159	0	74	0	0
T167	0	48	0	0
T168	0	34	0	0
T169	0	10	0	0
T170	0	10	0	0
T171	0	6	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1602	0	0
T6	74197	41	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	7	0	0
T110	0	45	0	0
T134	0	1	0	0
T149	2844	0	0	0
T159	0	29	0	0
T167	0	41	0	0
T168	0	36	0	0
T169	0	9	0	0
T170	0	17	0	0
T171	0	3	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1673	0	0
T6	74197	66	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	37	0	0
T110	0	33	0	0
T134	0	6	0	0
T149	2844	0	0	0
T159	0	32	0	0
T167	0	41	0	0
T168	0	45	0	0
T169	0	6	0	0
T170	0	11	0	0
T171	0	7	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1791	0	0
T6	74197	58	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	19	0	0
T110	0	61	0	0
T134	0	9	0	0
T149	2844	0	0	0
T159	0	51	0	0
T167	0	48	0	0
T168	0	38	0	0
T169	0	6	0	0
T170	0	27	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0
T181	0	1	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1628	0	0
T6	74197	90	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	9	0	0
T110	0	70	0	0
T134	0	15	0	0
T149	2844	0	0	0
T159	0	63	0	0
T167	0	55	0	0
T168	0	40	0	0
T169	0	15	0	0
T170	0	14	0	0
T171	0	1	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1689	0	0
T6	74197	73	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	27	0	0
T110	0	60	0	0
T134	0	6	0	0
T149	2844	0	0	0
T159	0	41	0	0
T167	0	33	0	0
T168	0	34	0	0
T169	0	14	0	0
T170	0	4	0	0
T171	0	4	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1693	0	0
T6	74197	50	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	21	0	0
T110	0	53	0	0
T134	0	10	0	0
T149	2844	0	0	0
T159	0	53	0	0
T167	0	40	0	0
T168	0	37	0	0
T169	0	4	0	0
T170	0	25	0	0
T171	0	8	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1544	0	0
T6	74197	86	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	25	0	0
T110	0	50	0	0
T134	0	4	0	0
T149	2844	0	0	0
T150	0	23	0	0
T159	0	33	0	0
T167	0	40	0	0
T168	0	45	0	0
T169	0	12	0	0
T171	0	8	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1666	0	0
T6	74197	44	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	28	0	0
T110	0	59	0	0
T134	0	9	0	0
T149	2844	0	0	0
T159	0	46	0	0
T167	0	44	0	0
T168	0	39	0	0
T169	0	8	0	0
T170	0	19	0	0
T171	0	3	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1596	0	0
T6	74197	59	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	3	0	0
T110	0	55	0	0
T134	0	5	0	0
T149	2844	0	0	0
T150	0	31	0	0
T159	0	54	0	0
T167	0	42	0	0
T168	0	35	0	0
T169	0	9	0	0
T171	0	5	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1534	0	0
T6	74197	59	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	20	0	0
T110	0	62	0	0
T149	2844	0	0	0
T150	0	18	0	0
T159	0	54	0	0
T167	0	35	0	0
T168	0	20	0	0
T169	0	10	0	0
T170	0	21	0	0
T171	0	8	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1668	0	0
T6	74197	69	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	19	0	0
T110	0	46	0	0
T134	0	9	0	0
T149	2844	0	0	0
T159	0	44	0	0
T167	0	71	0	0
T168	0	31	0	0
T169	0	6	0	0
T170	0	7	0	0
T171	0	2	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1651	0	0
T6	74197	77	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	10	0	0
T110	0	50	0	0
T134	0	2	0	0
T149	2844	0	0	0
T150	0	28	0	0
T159	0	47	0	0
T167	0	35	0	0
T168	0	32	0	0
T169	0	14	0	0
T170	0	4	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1587	0	0
T6	74197	51	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	11	0	0
T110	0	36	0	0
T134	0	6	0	0
T149	2844	0	0	0
T159	0	33	0	0
T167	0	37	0	0
T168	0	22	0	0
T169	0	3	0	0
T170	0	11	0	0
T171	0	7	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1732	0	0
T6	74197	124	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	8	0	0
T134	0	15	0	0
T149	2844	0	0	0
T159	0	46	0	0
T167	0	58	0	0
T168	0	46	0	0
T169	0	5	0	0
T170	0	6	0	0
T171	0	4	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0
T182	0	4	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1582	0	0
T6	74197	74	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	5	0	0
T110	0	47	0	0
T134	0	12	0	0
T149	2844	0	0	0
T159	0	46	0	0
T167	0	49	0	0
T168	0	37	0	0
T169	0	6	0	0
T170	0	9	0	0
T171	0	3	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1711	0	0
T6	74197	53	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	11	0	0
T110	0	46	0	0
T134	0	2	0	0
T149	2844	0	0	0
T159	0	81	0	0
T167	0	93	0	0
T168	0	41	0	0
T169	0	3	0	0
T170	0	6	0	0
T171	0	6	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31024013	1620	0	0
T6	74197	71	0	0
T34	3933	0	0	0
T88	17548	0	0	0
T100	216873	0	0	0
T101	42111	0	0	0
T109	0	14	0	0
T110	0	54	0	0
T134	0	8	0	0
T149	2844	0	0	0
T159	0	42	0	0
T167	0	52	0	0
T168	0	30	0	0
T169	0	11	0	0
T170	0	23	0	0
T171	0	6	0	0
T172	1052	0	0	0
T173	5360	0	0	0
T174	13359	0	0	0
T175	6724	0	0	0