Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11167

1

T1

1

T2

21

T3

4

auto[Attestation]

8077

1

T1

7

T2

8

T3

13

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2868	1			T2	5		T3	2		T4	2
auto[Aes]	3443	1			T2	2		T3	6		T4	1
auto[Kmac]	3434	1			T1	8		T2	3		T3	3
auto[Otbn]	3441	1			T2	5		T3	2		T4	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7738	1			T1	8		T2	8		T3	8
auto[OpGenId]	6058	1			T2	14		T3	4		T4	2
auto[OpGenSwOut]	6099	1			T2	8		T3	7		T4	2
auto[OpGenHwOut]	7087	1			T1	8		T2	7		T3	6
auto[OpDisable]	124	1			T47	1		T48	1		T49	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10054

1

T1

8

T2

1

T3

11

auto[OpDoneFail]

17052

1

T1

8

T2

36

T3

14

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	5977	1			T1	1		T2	6		T3	1
auto[StInit]	4337	1			T1	2		T2	31		T3	6
auto[StCreatorRootKey]	2995	1			T1	2		T3	4		T4	4
auto[StOwnerIntKey]	2600	1			T1	2		T3	2		T14	4
auto[StOwnerKey]	2431	1			T1	2		T3	3		T14	7
auto[StDisabled]	7734	1			T1	7		T3	9		T15	9
auto[StInvalid]	1032	1			T37	29		T38	27		T25	17

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	296	1			T14	2		T16	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	127	1			T2	3		T3	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	72	1			T34	1		T47	1		T204	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	63	1			T14	1		T47	1		T123	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	67	1			T134	2		T43	1		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	208	1			T34	1		T87	1		T134	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	30	1			T37	1		T25	2		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	294	1			T14	1		T15	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	114	1			T2	1		T47	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	78	1			T16	1		T18	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	74	1			T87	1		T134	1		T149	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	55	1			T47	1		T198	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	227	1			T34	2		T89	1		T134	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	35	1			T37	3		T25	1		T206	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	302	1			T14	2		T18	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	126	1			T2	1		T134	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	85	1			T87	1		T26	1		T149	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	63	1			T207	1		T56	1		T198	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	73	1			T198	1		T52	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	198	1			T15	1		T88	1		T89	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	38	1			T25	2		T206	2		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	297	1			T2	1		T18	2		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	135	1			T2	1		T89	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	76	1			T3	1		T4	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	57	1			T5	1		T57	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	58	1			T151	2		T207	1		T140	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	200	1			T47	1		T5	1		T208	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	26	1			T38	1		T206	1		T209	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	85	1			T52	2		T80	1		T70	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	120	1			T23	1		T24	1		T210	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	70	1			T35	1		T123	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	61	1			T47	2		T134	1		T151	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	69	1			T18	1		T43	1		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	220	1			T47	1		T134	1		T149	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	38	1			T38	3		T25	1		T206	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	81	1			T52	4		T44	1		T211	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	117	1			T3	1		T87	1		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	84	1			T3	1		T16	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	77	1			T198	2		T52	1		T44	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	72	1			T3	1		T14	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	213	1			T3	1		T15	1		T87	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	32	1			T37	2		T38	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	75	1			T47	2		T52	1		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	101	1			T2	1		T34	1		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	76	1			T34	1		T47	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	67	1			T14	1		T55	1		T212	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	53	1			T88	1		T151	1		T205	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	242	1			T47	1		T134	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	25	1			T37	1		T38	1		T213	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	71	1			T47	1		T52	1		T80	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	132	1			T3	1		T23	1		T24	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	65	1			T36	1		T214	1		T8	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T48	1		T43	1		T215	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	61	1			T15	1		T89	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	215	1			T34	2		T47	3		T134	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	31	1			T37	1		T38	2		T53	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	260	1			T14	3		T16	2		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	128	1			T2	1		T15	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	64	1			T34	1		T134	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	54	1			T87	1		T205	1		T140	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	52	1			T123	1		T149	1		T215	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	187	1			T34	1		T151	1		T204	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	32	1			T37	1		T38	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	384	1			T18	2		T47	1		T133	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	147	1			T18	1		T23	1		T139	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	102	1			T4	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	77	1			T18	1		T135	1		T136	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	91	1			T14	1		T34	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	260	1			T3	1		T15	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	37	1			T25	1		T206	2		T53	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	419	1			T15	1		T16	2		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	140	1			T2	1		T90	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	113	1			T90	1		T47	1		T123	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	87	1			T15	1		T123	1		T120	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	91	1			T14	1		T87	1		T205	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	279	1			T1	1		T3	1		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	37	1			T37	2		T25	1		T206	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	414	1			T17	9		T18	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	151	1			T2	1		T15	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	117	1			T4	1		T14	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	78	1			T17	1		T140	1		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	77	1			T14	2		T17	1		T134	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	302	1			T15	1		T17	4		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	39	1			T37	4		T38	1		T206	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	61	1			T47	1		T52	4		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	113	1			T2	1		T4	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	63	1			T134	1		T48	1		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	65	1			T151	1		T216	1		T44	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	46	1			T47	1		T207	1		T217	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	182	1			T3	1		T15	1		T133	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	35	1			T38	1		T206	2		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	56	1			T47	1		T52	1		T65	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	148	1			T2	1		T14	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	103	1			T3	1		T14	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	90	1			T139	1		T36	1		T149	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	83	1			T14	1		T15	1		T136	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	281	1			T135	2		T136	2		T123	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	31	1			T37	1		T38	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	57	1			T47	1		T52	1		T70	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	128	1			T1	1		T18	1		T134	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	92	1			T1	1		T16	1		T134	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	92	1			T1	1		T3	1		T90	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	98	1			T1	1		T14	1		T90	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	251	1			T1	3		T3	1		T90	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	26	1			T38	1		T213	1		T218	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	68	1			T52	3		T80	1		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	125	1			T2	2		T14	1		T134	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	113	1			T15	1		T16	1		T134	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	87	1			T123	1		T151	1		T219	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	84	1			T151	1		T205	1		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	260	1			T47	1		T123	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	30	1			T37	2		T38	1		T53	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	179	1			T14	1		T34	1		T47	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	684	1			T2	3		T3	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	184	1			T16	1		T18	1		T87	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	693	1			T2	1		T14	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	198	1			T87	1		T26	1		T149	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	687	1			T2	1		T14	2		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	172	1			T3	1		T4	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	677	1			T2	2		T18	2		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	186	1			T18	1		T47	2		T134	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	477	1			T47	1		T134	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	211	1			T3	2		T14	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	465	1			T3	2		T15	2		T87	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	181	1			T14	1		T34	1		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	458	1			T2	1		T34	1		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	181	1			T89	1		T48	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	466	1			T3	1		T15	1		T34	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	153	1			T34	1		T87	1		T134	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	624	1			T2	1		T14	3		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	252	1			T4	1		T14	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	846	1			T3	1		T15	2		T18	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	275	1			T14	1		T15	1		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	891	1			T1	1		T2	1		T3	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	255	1			T4	1		T14	3		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	923	1			T2	1		T15	2		T17	14
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	160	1			T47	1		T134	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	405	1			T2	1		T3	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	260	1			T3	1		T14	2		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	532	1			T2	1		T14	1		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	270	1			T1	3		T3	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	474	1			T1	4		T3	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	268	1			T16	1		T134	1		T123	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	499	1			T2	2		T14	1		T15	1