---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_ctrl.SecCmCFILinear_A	0	0	26278811	0	0	4818

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AdvDataWidth_A	0	0	863	863	0	0
tb.dut.AesKeyKnownO_A	0	0	26278811	26122160	0	0
tb.dut.AlertKnownO_A	0	0	26278811	26122160	0	0
tb.dut.ErrCntMatch_A	0	0	863	863	0	0
tb.dut.FaultCntMatch_A	0	0	863	863	0	0
tb.dut.FpvSecCmCtrlCntAlertCheck_A	0	0	26278811	70	0	0
tb.dut.FpvSecCmCtrlDataFsmCheck_A	0	0	26278811	70	0	0
tb.dut.FpvSecCmCtrlMainFsmCheck_A	0	0	26278811	70	0	0
tb.dut.FpvSecCmCtrlOpFsmCheck_A	0	0	26278811	70	0	0
tb.dut.FpvSecCmKmacIfCntAlertCheck_A	0	0	26278811	70	0	0
tb.dut.FpvSecCmKmacIfFsmCheck_A	0	0	26278811	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	26278811	70	0	0
tb.dut.FpvSecCmReseedCtrlCntAlertCheck_A	0	0	26278811	70	0	0
tb.dut.FpvSecCmSideloadCtrlFsmCheck_A	0	0	26278811	70	0	0
tb.dut.GenDataWidth_A	0	0	863	863	0	0
tb.dut.IdDataWidth_A	0	0	863	863	0	0
tb.dut.IntrKnownO_A	0	0	26278811	26122160	0	0
tb.dut.KmacDataKnownO_A	0	0	25727182	25574185	0	0
tb.dut.KmacKeyKnownO_A	0	0	26278811	26122160	0	0
tb.dut.KmacMaskCheck_A	0	0	863	863	0	0
tb.dut.LfsrWidth_A	0	0	863	863	0	0
tb.dut.OtbnKeyKnownO_A	0	0	26278811	26122160	0	0
tb.dut.OutputKeyDiff_A	0	0	863	863	0	0
tb.dut.StageMatch_A	0	0	863	863	0	0
tb.dut.TlAReadyKnownO_A	0	0	26278811	26122160	0	0
tb.dut.TlDValidKnownO_A	0	0	26278811	26122160	0	0
tb.dut.gen_sw_assigns[0].u_mubi_buf.NumCopiesMustBeGreaterZero_A	0	0	863	863	0	0
tb.dut.gen_sw_assigns[0].u_mubi_buf.OutputsKnown_A	0	0	26278811	26122160	0	0
tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_no_flops.OutputDelay_A	0	0	26278811	26122160	0	0
tb.dut.gen_sw_assigns[1].u_mubi_buf.NumCopiesMustBeGreaterZero_A	0	0	863	863	0	0
tb.dut.gen_sw_assigns[1].u_mubi_buf.OutputsKnown_A	0	0	26278811	26122160	0	0
tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_no_flops.OutputDelay_A	0	0	26278811	26122160	0	0
tb.dut.gen_sw_assigns[2].u_mubi_buf.NumCopiesMustBeGreaterZero_A	0	0	863	863	0	0
tb.dut.gen_sw_assigns[2].u_mubi_buf.OutputsKnown_A	0	0	26278811	26122160	0	0
tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_no_flops.OutputDelay_A	0	0	26278811	26122160	0	0
tb.dut.gen_sw_assigns[3].u_mubi_buf.NumCopiesMustBeGreaterZero_A	0	0	863	863	0	0
tb.dut.gen_sw_assigns[3].u_mubi_buf.OutputsKnown_A	0	0	26278811	26122160	0	0
tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_no_flops.OutputDelay_A	0	0	26278811	26122160	0	0
tb.dut.gen_sw_assigns[4].u_mubi_buf.NumCopiesMustBeGreaterZero_A	0	0	863	863	0	0
tb.dut.gen_sw_assigns[4].u_mubi_buf.OutputsKnown_A	0	0	26278811	26122160	0	0
tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_no_flops.OutputDelay_A	0	0	26278811	26122160	0	0
tb.dut.gen_sw_assigns[5].u_mubi_buf.NumCopiesMustBeGreaterZero_A	0	0	863	863	0	0
tb.dut.gen_sw_assigns[5].u_mubi_buf.OutputsKnown_A	0	0	26278811	26122160	0	0
tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_no_flops.OutputDelay_A	0	0	26278811	26122160	0	0
tb.dut.gen_sw_assigns[6].u_mubi_buf.NumCopiesMustBeGreaterZero_A	0	0	863	863	0	0
tb.dut.gen_sw_assigns[6].u_mubi_buf.OutputsKnown_A	0	0	26278811	26122160	0	0
tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_no_flops.OutputDelay_A	0	0	26278811	26122160	0	0
tb.dut.gen_sw_assigns[7].u_mubi_buf.NumCopiesMustBeGreaterZero_A	0	0	863	863	0	0
tb.dut.gen_sw_assigns[7].u_mubi_buf.OutputsKnown_A	0	0	26278811	26122160	0	0
tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_no_flops.OutputDelay_A	0	0	26278811	26122160	0	0
tb.dut.keymgr_csr_assert.TlulOOBAddrErr_A	0	0	28534144	9762	0	0
tb.dut.keymgr_csr_assert.attest_sw_binding_0_rd_A	0	0	28534144	2908	0	0
tb.dut.keymgr_csr_assert.attest_sw_binding_1_rd_A	0	0	28534144	2768	0	0
tb.dut.keymgr_csr_assert.attest_sw_binding_2_rd_A	0	0	28534144	2960	0	0
tb.dut.keymgr_csr_assert.attest_sw_binding_3_rd_A	0	0	28534144	2968	0	0
tb.dut.keymgr_csr_assert.attest_sw_binding_4_rd_A	0	0	28534144	2923	0	0
tb.dut.keymgr_csr_assert.attest_sw_binding_5_rd_A	0	0	28534144	2886	0	0
tb.dut.keymgr_csr_assert.attest_sw_binding_6_rd_A	0	0	28534144	2815	0	0
tb.dut.keymgr_csr_assert.attest_sw_binding_7_rd_A	0	0	28534144	2931	0	0
tb.dut.keymgr_csr_assert.intr_enable_rd_A	0	0	28534144	3547	0	0
tb.dut.keymgr_csr_assert.key_version_rd_A	0	0	28534144	2890	0	0
tb.dut.keymgr_csr_assert.max_creator_key_ver_regwen_rd_A	0	0	28534144	2762	0	0
tb.dut.keymgr_csr_assert.max_owner_int_key_ver_regwen_rd_A	0	0	28534144	2791	0	0
tb.dut.keymgr_csr_assert.max_owner_key_ver_regwen_rd_A	0	0	28534144	2892	0	0
tb.dut.keymgr_csr_assert.reseed_interval_regwen_rd_A	0	0	28534144	3026	0	0
tb.dut.keymgr_csr_assert.salt_0_rd_A	0	0	28534144	2992	0	0
tb.dut.keymgr_csr_assert.salt_1_rd_A	0	0	28534144	2989	0	0
tb.dut.keymgr_csr_assert.salt_2_rd_A	0	0	28534144	2815	0	0
tb.dut.keymgr_csr_assert.salt_3_rd_A	0	0	28534144	2895	0	0
tb.dut.keymgr_csr_assert.salt_4_rd_A	0	0	28534144	2893	0	0
tb.dut.keymgr_csr_assert.salt_5_rd_A	0	0	28534144	2907	0	0
tb.dut.keymgr_csr_assert.salt_6_rd_A	0	0	28534144	2864	0	0
tb.dut.keymgr_csr_assert.salt_7_rd_A	0	0	28534144	2852	0	0
tb.dut.keymgr_csr_assert.sealing_sw_binding_0_rd_A	0	0	28534144	3031	0	0
tb.dut.keymgr_csr_assert.sealing_sw_binding_1_rd_A	0	0	28534144	2914	0	0
tb.dut.keymgr_csr_assert.sealing_sw_binding_2_rd_A	0	0	28534144	2857	0	0
tb.dut.keymgr_csr_assert.sealing_sw_binding_3_rd_A	0	0	28534144	2955	0	0
tb.dut.keymgr_csr_assert.sealing_sw_binding_4_rd_A	0	0	28534144	2794	0	0
tb.dut.keymgr_csr_assert.sealing_sw_binding_5_rd_A	0	0	28534144	3003	0	0
tb.dut.keymgr_csr_assert.sealing_sw_binding_6_rd_A	0	0	28534144	2876	0	0
tb.dut.keymgr_csr_assert.sealing_sw_binding_7_rd_A	0	0	28534144	2879	0	0
tb.dut.keymgr_csr_assert.sideload_clear_rd_A	0	0	28534144	2970	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	28534144	5176767	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	28534144	28304097	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	28534144	28304097	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	28534144	6835370	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	28534144	28304097	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	28534144	28304097	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
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tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
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tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
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tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1068	1068	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	28534779	522764	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	28534144	9567	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	28534779	4692236	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	28503723	5813056	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	28534144	9132	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	28534779	5176767	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	28534779	6835370	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	28534779	5176767	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	28534779	6835370	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	28534779	6835370	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	28534779	6835370	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	28534144	6946	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	28534144	7338	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1068	1068	0	0
tb.dut.u_checks.gen_key_chk[0].u_key_pad.WidthCheck_A	0	0	863	863	0	0
tb.dut.u_checks.gen_key_chk[1].u_key_pad.WidthCheck_A	0	0	863	863	0	0
tb.dut.u_checks.u_creator_seed.WidthCheck_A	0	0	863	863	0	0
tb.dut.u_checks.u_devid.WidthCheck_A	0	0	863	863	0	0
tb.dut.u_checks.u_health_state.WidthCheck_A	0	0	863	863	0	0
tb.dut.u_checks.u_owner_seed.WidthCheck_A	0	0	863	863	0	0
tb.dut.u_ctrl.CntZero_A	0	0	25727182	27969	0	0
tb.dut.u_ctrl.DataEnDis_A	0	0	25521052	27426	0	0
tb.dut.u_ctrl.DataEn_A	0	0	25521052	6609489	0	0
tb.dut.u_ctrl.GeneralLegalCommands_A	0	0	26278811	33609	0	0
tb.dut.u_ctrl.InitLegalCommands_A	0	0	26278811	1336665	0	0
tb.dut.u_ctrl.LoadKey_A	0	0	26225453	20135212	0	0
tb.dut.u_ctrl.OwnerLegalCommands_A	0	0	26278811	1569152	0	0
tb.dut.u_ctrl.SameErrCnt_A	0	0	863	863	0	0
tb.dut.u_ctrl.StageDisableSel_A	0	0	26278811	790783	0	0
tb.dut.u_ctrl.u_data_en.u_state_regs.AssertConnected_A	0	0	863	863	0	0
tb.dut.u_ctrl.u_data_en.u_state_regs_A	0	0	26278811	26122160	0	0
tb.dut.u_ctrl.u_hw_sel.OutputsKnown_A	0	0	26278811	26122160	0	0
tb.dut.u_ctrl.u_op_state.u_state_regs.AssertConnected_A	0	0	863	863	0	0
tb.dut.u_ctrl.u_op_state.u_state_regs_A	0	0	26278811	26122160	0	0
tb.dut.u_ctrl.u_state_regs.AssertConnected_A	0	0	863	863	0	0
tb.dut.u_ctrl.u_state_regs_A	0	0	26278811	26122160	0	0
tb.dut.u_intr_op_done.IntrTKind_A	0	0	863	863	0	0
tb.dut.u_kmac_if.AdvRemBytes_A	0	0	863	863	0	0
tb.dut.u_kmac_if.GenRemBytes_A	0	0	863	863	0	0
tb.dut.u_kmac_if.IdRemBytes_A	0	0	863	863	0	0
tb.dut.u_kmac_if.LastStrb_A	0	0	25727182	18550632	0	0
tb.dut.u_kmac_if.u_state_regs.AssertConnected_A	0	0	863	863	0	0
tb.dut.u_kmac_if.u_state_regs_A	0	0	26278811	26122160	0	0
tb.dut.u_lc_keymgr_en_sync.NumCopiesMustBeGreaterZero_A	0	0	863	863	0	0
tb.dut.u_lc_keymgr_en_sync.OutputsKnown_A	0	0	26278811	26122160	0	0
tb.dut.u_lc_keymgr_en_sync.gen_flops.OutputDelay_A	0	0	26278811	26115554	0	2589
tb.dut.u_reg.en2addrHit	0	0	28534144	4818693	0	0
tb.dut.u_reg.reAfterRv	0	0	28534144	4818693	0	0
tb.dut.u_reg.rePulse	0	0	28534144	4441003	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	1068	1068	0	0
tb.dut.u_reg.u_control_shadowed_cdi_sel.CheckSwAccessIsLegal_A	0	0	1068	1068	0	0
tb.dut.u_reg.u_control_shadowed_cdi_sel.MubiIsNotYetSupported_A	0	0	28534144	28304097	0	0
tb.dut.u_reg.u_control_shadowed_dest_sel.CheckSwAccessIsLegal_A	0	0	1068	1068	0	0
tb.dut.u_reg.u_control_shadowed_dest_sel.MubiIsNotYetSupported_A	0	0	28534144	28304097	0	0
tb.dut.u_reg.u_control_shadowed_operation.CheckSwAccessIsLegal_A	0	0	1068	1068	0	0
tb.dut.u_reg.u_control_shadowed_operation.MubiIsNotYetSupported_A	0	0	28534144	28304097	0	0
tb.dut.u_reg.u_max_creator_key_ver_shadowed.CheckSwAccessIsLegal_A	0	0	1068	1068	0	0
tb.dut.u_reg.u_max_creator_key_ver_shadowed.MubiIsNotYetSupported_A	0	0	28534144	28304097	0	0
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.CheckSwAccessIsLegal_A	0	0	1068	1068	0	0
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.MubiIsNotYetSupported_A	0	0	28534144	28304097	0	0
tb.dut.u_reg.u_max_owner_key_ver_shadowed.CheckSwAccessIsLegal_A	0	0	1068	1068	0	0
tb.dut.u_reg.u_max_owner_key_ver_shadowed.MubiIsNotYetSupported_A	0	0	28534144	28304097	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	1068	1068	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	1068	1068	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	1068	1068	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1068	1068	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1068	1068	0	0
tb.dut.u_reg.u_reseed_interval_shadowed.CheckSwAccessIsLegal_A	0	0	1068	1068	0	0
tb.dut.u_reg.u_reseed_interval_shadowed.MubiIsNotYetSupported_A	0	0	28534144	28304097	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	1068	1068	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1068	1068	0	0
tb.dut.u_reg.wePulse	0	0	28534144	377690	0	0
tb.dut.u_reseed_ctrl.u_edn_req.DataOutputDiffFromPrev_A	0	0	26278811	19171797	0	0
tb.dut.u_reseed_ctrl.u_edn_req.DataOutputValid_A	0	0	26278811	103131	0	0
tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	0	0	26278811	206379	0	0
tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	0	0	26278811	206360	0	0
tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq	0	0	48697566	206458	0	0
tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq	0	0	26278811	103131	0	0
tb.dut.u_sideload_ctrl.KmacKeySource_a	0	0	26225453	11651	0	0
tb.dut.u_sideload_ctrl.u_mubi_buf.NumCopiesMustBeGreaterZero_A	0	0	863	863	0	0
tb.dut.u_sideload_ctrl.u_mubi_buf.OutputsKnown_A	0	0	26278811	26122160	0	0
tb.dut.u_sideload_ctrl.u_mubi_buf.gen_no_flops.OutputDelay_A	0	0	26278811	26122160	0	0
tb.dut.u_sideload_ctrl.u_state_regs.AssertConnected_A	0	0	863	863	0	0
tb.dut.u_sideload_ctrl.u_state_regs_A	0	0	26278811	26122160	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_ctrl.SecCmCFILinear_A	0	0	26278811	0	0	4818
tb.dut.u_lc_keymgr_en_sync.gen_flops.OutputDelay_A	0	0	26278811	26115554	0	2589

Assertions Excluded:

ASSERTIONS	CATEGORY	SEVERITY	EXCLUSION	EXCLUDE ANNOTATION	SRC
tb.dut.u_reseed_ctrl.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	Excluded	[UNR] rready_i is tied to 1 from prim_edn_req module.
tb.dut.u_reseed_ctrl.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	Excluded	[UNR] rready_i is tied to 1 from prim_edn_req module.

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	28534779	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	28534779	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	28534779	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	28534779	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	28534779	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	28534779	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	28534779	12888	12888	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	28534779	6297	6297	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	28534779	141745	141745	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	28534779	2479057	2479057	1029

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	28534779	12888	12888	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	28534779	6297	6297	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	28534779	141745	141745	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	28534779	2479057	2479057	1029