Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31003

1

T1

20

T2

42

T3

28

auto[1]

315

1

T123

9

T151

3

T140

9

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31017	1			T1	20		T2	42		T3	28
auto[134217728:268435455]	3	1			T402	1		T403	1		T307	1
auto[268435456:402653183]	13	1			T123	1		T140	1		T153	1
auto[402653184:536870911]	8	1			T152	1		T404	1		T405	1
auto[536870912:671088639]	11	1			T140	1		T191	1		T280	1
auto[671088640:805306367]	14	1			T123	1		T140	1		T153	1
auto[805306368:939524095]	5	1			T123	1		T263	1		T406	1
auto[939524096:1073741823]	3	1			T387	1		T403	1		T407	1
auto[1073741824:1207959551]	11	1			T151	1		T263	1		T331	1
auto[1207959552:1342177279]	11	1			T123	1		T152	1		T191	1
auto[1342177280:1476395007]	8	1			T140	1		T357	1		T404	1
auto[1476395008:1610612735]	8	1			T151	1		T386	1		T335	1
auto[1610612736:1744830463]	9	1			T191	1		T331	1		T313	1
auto[1744830464:1879048191]	6	1			T280	1		T262	1		T406	1
auto[1879048192:2013265919]	12	1			T140	2		T153	1		T191	1
auto[2013265920:2147483647]	11	1			T331	1		T280	1		T313	1
auto[2147483648:2281701375]	14	1			T152	1		T191	1		T262	1
auto[2281701376:2415919103]	9	1			T191	1		T263	1		T385	2
auto[2415919104:2550136831]	13	1			T140	1		T152	1		T313	1
auto[2550136832:2684354559]	13	1			T152	1		T313	1		T262	1
auto[2684354560:2818572287]	9	1			T153	1		T191	2		T280	1
auto[2818572288:2952790015]	11	1			T331	1		T239	1		T408	1
auto[2952790016:3087007743]	14	1			T140	1		T191	1		T331	1
auto[3087007744:3221225471]	8	1			T262	1		T239	1		T387	1
auto[3221225472:3355443199]	9	1			T123	1		T141	2		T280	1
auto[3355443200:3489660927]	12	1			T123	1		T152	1		T153	1
auto[3489660928:3623878655]	8	1			T123	1		T140	1		T262	2
auto[3623878656:3758096383]	11	1			T123	1		T151	1		T262	1
auto[3758096384:3892314111]	11	1			T123	1		T152	1		T141	1
auto[3892314112:4026531839]	9	1			T195	1		T262	1		T408	2
auto[4026531840:4160749567]	10	1			T153	1		T191	1		T408	1
auto[4160749568:4294967295]	7	1			T152	1		T153	1		T141	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31003	1			T1	20		T2	42		T3	28
auto[0:134217727]	auto[1]	14	1			T153	1		T239	1		T408	2
auto[134217728:268435455]	auto[1]	3	1			T402	1		T403	1		T307	1
auto[268435456:402653183]	auto[1]	13	1			T123	1		T140	1		T153	1
auto[402653184:536870911]	auto[1]	8	1			T152	1		T404	1		T405	1
auto[536870912:671088639]	auto[1]	11	1			T140	1		T191	1		T280	1
auto[671088640:805306367]	auto[1]	14	1			T123	1		T140	1		T153	1
auto[805306368:939524095]	auto[1]	5	1			T123	1		T263	1		T406	1
auto[939524096:1073741823]	auto[1]	3	1			T387	1		T403	1		T407	1
auto[1073741824:1207959551]	auto[1]	11	1			T151	1		T263	1		T331	1
auto[1207959552:1342177279]	auto[1]	11	1			T123	1		T152	1		T191	1
auto[1342177280:1476395007]	auto[1]	8	1			T140	1		T357	1		T404	1
auto[1476395008:1610612735]	auto[1]	8	1			T151	1		T386	1		T335	1
auto[1610612736:1744830463]	auto[1]	9	1			T191	1		T331	1		T313	1
auto[1744830464:1879048191]	auto[1]	6	1			T280	1		T262	1		T406	1
auto[1879048192:2013265919]	auto[1]	12	1			T140	2		T153	1		T191	1
auto[2013265920:2147483647]	auto[1]	11	1			T331	1		T280	1		T313	1
auto[2147483648:2281701375]	auto[1]	14	1			T152	1		T191	1		T262	1
auto[2281701376:2415919103]	auto[1]	9	1			T191	1		T263	1		T385	2
auto[2415919104:2550136831]	auto[1]	13	1			T140	1		T152	1		T313	1
auto[2550136832:2684354559]	auto[1]	13	1			T152	1		T313	1		T262	1
auto[2684354560:2818572287]	auto[1]	9	1			T153	1		T191	2		T280	1
auto[2818572288:2952790015]	auto[1]	11	1			T331	1		T239	1		T408	1
auto[2952790016:3087007743]	auto[1]	14	1			T140	1		T191	1		T331	1
auto[3087007744:3221225471]	auto[1]	8	1			T262	1		T239	1		T387	1
auto[3221225472:3355443199]	auto[1]	9	1			T123	1		T141	2		T280	1
auto[3355443200:3489660927]	auto[1]	12	1			T123	1		T152	1		T153	1
auto[3489660928:3623878655]	auto[1]	8	1			T123	1		T140	1		T262	2
auto[3623878656:3758096383]	auto[1]	11	1			T123	1		T151	1		T262	1
auto[3758096384:3892314111]	auto[1]	11	1			T123	1		T152	1		T141	1
auto[3892314112:4026531839]	auto[1]	9	1			T195	1		T262	1		T408	2
auto[4026531840:4160749567]	auto[1]	10	1			T153	1		T191	1		T408	1
auto[4160749568:4294967295]	auto[1]	7	1			T152	1		T153	1		T141	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1582

1

T2

5

T3

2

T15

2

auto[1]

1649

1

T2

1

T3

2

T14

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	89	1			T26	1		T123	1		T5	2
auto[134217728:268435455]	97	1			T3	1		T29	1		T44	1
auto[268435456:402653183]	103	1			T3	1		T23	1		T48	1
auto[402653184:536870911]	85	1			T23	1		T5	1		T43	1
auto[536870912:671088639]	122	1			T2	1		T134	1		T123	1
auto[671088640:805306367]	102	1			T3	1		T134	3		T38	1
auto[805306368:939524095]	96	1			T2	1		T24	1		T151	1
auto[939524096:1073741823]	105	1			T15	1		T16	1		T47	1
auto[1073741824:1207959551]	102	1			T47	1		T50	1		T48	1
auto[1207959552:1342177279]	90	1			T24	1		T37	1		T204	1
auto[1342177280:1476395007]	108	1			T401	1		T198	1		T52	1
auto[1476395008:1610612735]	91	1			T3	1		T34	1		T43	1
auto[1610612736:1744830463]	114	1			T24	1		T43	1		T61	1
auto[1744830464:1879048191]	105	1			T134	1		T55	1		T52	2
auto[1879048192:2013265919]	118	1			T5	1		T43	3		T52	1
auto[2013265920:2147483647]	96	1			T47	3		T50	1		T5	1
auto[2147483648:2281701375]	100	1			T50	1		T23	1		T43	2
auto[2281701376:2415919103]	86	1			T55	1		T44	1		T81	1
auto[2415919104:2550136831]	100	1			T2	2		T34	1		T43	1
auto[2550136832:2684354559]	103	1			T24	1		T43	3		T55	1
auto[2684354560:2818572287]	117	1			T15	1		T16	1		T151	1
auto[2818572288:2952790015]	92	1			T14	1		T123	1		T5	1
auto[2952790016:3087007743]	106	1			T23	1		T5	1		T204	1
auto[3087007744:3221225471]	96	1			T16	1		T47	1		T50	1
auto[3221225472:3355443199]	89	1			T47	1		T50	1		T123	1
auto[3355443200:3489660927]	96	1			T15	1		T37	1		T210	1
auto[3489660928:3623878655]	102	1			T23	1		T151	1		T6	1
auto[3623878656:3758096383]	103	1			T2	1		T14	1		T23	1
auto[3758096384:3892314111]	106	1			T2	1		T23	1		T5	2
auto[3892314112:4026531839]	107	1			T14	1		T15	1		T47	1
auto[4026531840:4160749567]	101	1			T49	1		T43	1		T401	1
auto[4160749568:4294967295]	104	1			T16	1		T34	1		T37	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	36	1			T5	1		T25	1		T72	1
auto[0:134217727]	auto[1]	53	1			T26	1		T123	1		T5	1
auto[134217728:268435455]	auto[0]	46	1			T3	1		T44	1		T70	1
auto[134217728:268435455]	auto[1]	51	1			T29	1		T82	1		T218	1
auto[268435456:402653183]	auto[0]	55	1			T3	1		T401	1		T61	1
auto[268435456:402653183]	auto[1]	48	1			T23	1		T48	1		T52	1
auto[402653184:536870911]	auto[0]	40	1			T5	1		T43	1		T52	1
auto[402653184:536870911]	auto[1]	45	1			T23	1		T215	1		T25	1
auto[536870912:671088639]	auto[0]	56	1			T2	1		T24	1		T52	1
auto[536870912:671088639]	auto[1]	66	1			T134	1		T123	1		T5	1
auto[671088640:805306367]	auto[0]	58	1			T134	2		T38	1		T6	1
auto[671088640:805306367]	auto[1]	44	1			T3	1		T134	1		T52	1
auto[805306368:939524095]	auto[0]	47	1			T151	1		T43	1		T401	1
auto[805306368:939524095]	auto[1]	49	1			T2	1		T24	1		T43	1
auto[939524096:1073741823]	auto[0]	52	1			T16	1		T198	1		T53	1
auto[939524096:1073741823]	auto[1]	53	1			T15	1		T47	1		T134	1
auto[1073741824:1207959551]	auto[0]	44	1			T47	1		T50	1		T48	1
auto[1073741824:1207959551]	auto[1]	58	1			T37	1		T44	2		T80	1
auto[1207959552:1342177279]	auto[0]	42	1			T24	1		T52	1		T44	1
auto[1207959552:1342177279]	auto[1]	48	1			T37	1		T204	1		T43	1
auto[1342177280:1476395007]	auto[0]	42	1			T401	1		T198	1		T70	1
auto[1342177280:1476395007]	auto[1]	66	1			T52	1		T44	1		T231	1
auto[1476395008:1610612735]	auto[0]	47	1			T34	1		T52	1		T44	1
auto[1476395008:1610612735]	auto[1]	44	1			T3	1		T43	1		T206	1
auto[1610612736:1744830463]	auto[0]	51	1			T24	1		T198	1		T8	1
auto[1610612736:1744830463]	auto[1]	63	1			T43	1		T61	1		T53	1
auto[1744830464:1879048191]	auto[0]	49	1			T52	2		T209	1		T268	1
auto[1744830464:1879048191]	auto[1]	56	1			T134	1		T55	1		T44	3
auto[1879048192:2013265919]	auto[0]	53	1			T5	1		T43	1		T52	1
auto[1879048192:2013265919]	auto[1]	65	1			T43	2		T44	1		T64	1
auto[2013265920:2147483647]	auto[0]	51	1			T47	3		T50	1		T5	1
auto[2013265920:2147483647]	auto[1]	45	1			T215	1		T152	2		T195	1
auto[2147483648:2281701375]	auto[0]	59	1			T23	1		T38	1		T198	1
auto[2147483648:2281701375]	auto[1]	41	1			T50	1		T43	2		T56	1
auto[2281701376:2415919103]	auto[0]	29	1			T81	1		T116	1		T409	1
auto[2281701376:2415919103]	auto[1]	57	1			T55	1		T44	1		T70	3
auto[2415919104:2550136831]	auto[0]	50	1			T2	2		T80	1		T70	1
auto[2415919104:2550136831]	auto[1]	50	1			T34	1		T43	1		T44	1
auto[2550136832:2684354559]	auto[0]	56	1			T43	2		T52	2		T410	1
auto[2550136832:2684354559]	auto[1]	47	1			T24	1		T43	1		T55	1
auto[2684354560:2818572287]	auto[0]	57	1			T52	1		T70	2		T274	1
auto[2684354560:2818572287]	auto[1]	60	1			T15	1		T16	1		T151	1
auto[2818572288:2952790015]	auto[0]	43	1			T5	1		T151	1		T210	1
auto[2818572288:2952790015]	auto[1]	49	1			T14	1		T123	1		T210	1
auto[2952790016:3087007743]	auto[0]	64	1			T23	1		T204	1		T43	1
auto[2952790016:3087007743]	auto[1]	42	1			T5	1		T52	1		T67	1
auto[3087007744:3221225471]	auto[0]	53	1			T16	1		T50	1		T149	1
auto[3087007744:3221225471]	auto[1]	43	1			T47	1		T401	1		T28	1
auto[3221225472:3355443199]	auto[0]	40	1			T47	1		T50	1		T8	1
auto[3221225472:3355443199]	auto[1]	49	1			T123	1		T210	1		T101	1
auto[3355443200:3489660927]	auto[0]	46	1			T15	1		T210	1		T52	1
auto[3355443200:3489660927]	auto[1]	50	1			T37	1		T273	1		T411	1
auto[3489660928:3623878655]	auto[0]	47	1			T23	1		T6	1		T44	1
auto[3489660928:3623878655]	auto[1]	55	1			T151	1		T25	1		T65	1
auto[3623878656:3758096383]	auto[0]	50	1			T2	1		T23	1		T5	1
auto[3623878656:3758096383]	auto[1]	53	1			T14	1		T149	1		T70	1
auto[3758096384:3892314111]	auto[0]	58	1			T2	1		T23	1		T5	2
auto[3758096384:3892314111]	auto[1]	48	1			T150	1		T215	1		T44	2
auto[3892314112:4026531839]	auto[0]	49	1			T15	1		T47	1		T50	1
auto[3892314112:4026531839]	auto[1]	58	1			T14	1		T205	1		T44	1
auto[4026531840:4160749567]	auto[0]	56	1			T401	1		T6	1		T101	1
auto[4026531840:4160749567]	auto[1]	45	1			T49	1		T43	1		T82	1
auto[4160749568:4294967295]	auto[0]	56	1			T16	1		T43	1		T101	1
auto[4160749568:4294967295]	auto[1]	48	1			T34	1		T37	1		T52	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1588

1

T2

5

T3

2

T14

1

auto[1]

1643

1

T2

1

T3

2

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T3	1		T47	1		T134	1
auto[134217728:268435455]	110	1			T50	1		T23	1		T37	1
auto[268435456:402653183]	93	1			T134	2		T23	1		T5	1
auto[402653184:536870911]	109	1			T15	1		T134	1		T6	1
auto[536870912:671088639]	99	1			T24	1		T204	1		T43	1
auto[671088640:805306367]	92	1			T37	1		T55	1		T6	1
auto[805306368:939524095]	106	1			T2	1		T15	1		T5	1
auto[939524096:1073741823]	88	1			T23	2		T38	1		T401	1
auto[1073741824:1207959551]	109	1			T14	1		T23	1		T43	1
auto[1207959552:1342177279]	95	1			T5	1		T25	1		T56	1
auto[1342177280:1476395007]	95	1			T47	1		T50	1		T23	1
auto[1476395008:1610612735]	89	1			T16	1		T70	1		T82	1
auto[1610612736:1744830463]	94	1			T3	1		T47	1		T43	1
auto[1744830464:1879048191]	94	1			T14	1		T5	1		T55	1
auto[1879048192:2013265919]	88	1			T34	1		T43	2		T44	2
auto[2013265920:2147483647]	97	1			T2	1		T210	1		T401	1
auto[2147483648:2281701375]	94	1			T24	1		T151	1		T38	1
auto[2281701376:2415919103]	106	1			T50	1		T151	1		T204	1
auto[2415919104:2550136831]	92	1			T16	1		T48	1		T43	2
auto[2550136832:2684354559]	89	1			T2	1		T23	1		T24	1
auto[2684354560:2818572287]	107	1			T15	1		T16	1		T123	1
auto[2818572288:2952790015]	120	1			T14	1		T34	1		T5	1
auto[2952790016:3087007743]	97	1			T2	1		T3	1		T5	1
auto[3087007744:3221225471]	106	1			T34	1		T47	1		T134	1
auto[3221225472:3355443199]	98	1			T47	1		T123	1		T24	1
auto[3355443200:3489660927]	110	1			T2	1		T134	1		T26	1
auto[3489660928:3623878655]	116	1			T3	1		T16	1		T50	1
auto[3623878656:3758096383]	99	1			T47	2		T50	1		T28	1
auto[3758096384:3892314111]	111	1			T15	1		T47	1		T23	1
auto[3892314112:4026531839]	100	1			T26	1		T24	1		T37	1
auto[4026531840:4160749567]	109	1			T2	1		T198	2		T52	1
auto[4160749568:4294967295]	105	1			T5	2		T204	1		T43	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	62	1			T3	1		T47	1		T134	1
auto[0:134217727]	auto[1]	52	1			T123	1		T43	1		T53	1
auto[134217728:268435455]	auto[0]	55	1			T50	1		T210	1		T6	1
auto[134217728:268435455]	auto[1]	55	1			T23	1		T37	1		T55	1
auto[268435456:402653183]	auto[0]	41	1			T198	1		T52	1		T44	1
auto[268435456:402653183]	auto[1]	52	1			T134	2		T23	1		T5	1
auto[402653184:536870911]	auto[0]	52	1			T6	1		T25	1		T70	1
auto[402653184:536870911]	auto[1]	57	1			T15	1		T134	1		T205	1
auto[536870912:671088639]	auto[0]	48	1			T24	1		T43	1		T44	1
auto[536870912:671088639]	auto[1]	51	1			T204	1		T206	1		T198	1
auto[671088640:805306367]	auto[0]	39	1			T6	1		T52	2		T80	1
auto[671088640:805306367]	auto[1]	53	1			T37	1		T55	1		T70	1
auto[805306368:939524095]	auto[0]	54	1			T2	1		T15	1		T5	1
auto[805306368:939524095]	auto[1]	52	1			T215	1		T44	2		T82	1
auto[939524096:1073741823]	auto[0]	39	1			T23	2		T38	1		T70	1
auto[939524096:1073741823]	auto[1]	49	1			T401	1		T52	1		T44	2
auto[1073741824:1207959551]	auto[0]	45	1			T14	1		T23	1		T401	1
auto[1073741824:1207959551]	auto[1]	64	1			T43	1		T81	1		T7	1
auto[1207959552:1342177279]	auto[0]	52	1			T56	1		T52	1		T80	1
auto[1207959552:1342177279]	auto[1]	43	1			T5	1		T25	1		T52	1
auto[1342177280:1476395007]	auto[0]	53	1			T149	1		T401	1		T25	1
auto[1342177280:1476395007]	auto[1]	42	1			T47	1		T50	1		T23	1
auto[1476395008:1610612735]	auto[0]	50	1			T16	1		T70	1		T412	2
auto[1476395008:1610612735]	auto[1]	39	1			T82	1		T152	1		T231	1
auto[1610612736:1744830463]	auto[0]	41	1			T47	1		T53	1		T84	1
auto[1610612736:1744830463]	auto[1]	53	1			T3	1		T43	1		T44	1
auto[1744830464:1879048191]	auto[0]	51	1			T25	1		T52	1		T81	1
auto[1744830464:1879048191]	auto[1]	43	1			T14	1		T5	1		T55	1
auto[1879048192:2013265919]	auto[0]	37	1			T411	1		T103	1		T142	1
auto[1879048192:2013265919]	auto[1]	51	1			T34	1		T43	2		T44	2
auto[2013265920:2147483647]	auto[0]	44	1			T2	1		T401	1		T44	1
auto[2013265920:2147483647]	auto[1]	53	1			T210	1		T25	1		T44	4
auto[2147483648:2281701375]	auto[0]	50	1			T24	1		T38	1		T52	1
auto[2147483648:2281701375]	auto[1]	44	1			T151	1		T67	1		T199	2
auto[2281701376:2415919103]	auto[0]	58	1			T50	1		T204	1		T43	1
auto[2281701376:2415919103]	auto[1]	48	1			T151	1		T215	1		T52	1
auto[2415919104:2550136831]	auto[0]	37	1			T43	1		T70	1		T286	1
auto[2415919104:2550136831]	auto[1]	55	1			T16	1		T48	1		T43	1
auto[2550136832:2684354559]	auto[0]	36	1			T2	1		T23	1		T43	2
auto[2550136832:2684354559]	auto[1]	53	1			T24	1		T37	1		T210	1
auto[2684354560:2818572287]	auto[0]	56	1			T15	1		T16	1		T151	1
auto[2684354560:2818572287]	auto[1]	51	1			T123	1		T149	1		T43	2
auto[2818572288:2952790015]	auto[0]	55	1			T34	1		T5	1		T38	2
auto[2818572288:2952790015]	auto[1]	65	1			T14	1		T204	1		T61	2
auto[2952790016:3087007743]	auto[0]	49	1			T2	1		T101	1		T25	1
auto[2952790016:3087007743]	auto[1]	48	1			T3	1		T5	1		T150	1
auto[3087007744:3221225471]	auto[0]	56	1			T47	1		T50	1		T123	1
auto[3087007744:3221225471]	auto[1]	50	1			T34	1		T134	1		T52	1
auto[3221225472:3355443199]	auto[0]	56	1			T24	1		T5	1		T101	2
auto[3221225472:3355443199]	auto[1]	42	1			T47	1		T123	1		T210	1
auto[3355443200:3489660927]	auto[0]	49	1			T5	2		T83	1		T84	1
auto[3355443200:3489660927]	auto[1]	61	1			T2	1		T134	1		T26	1
auto[3489660928:3623878655]	auto[0]	62	1			T3	1		T16	1		T50	1
auto[3489660928:3623878655]	auto[1]	54	1			T215	1		T198	1		T52	1
auto[3623878656:3758096383]	auto[0]	49	1			T47	2		T50	1		T52	2
auto[3623878656:3758096383]	auto[1]	50	1			T28	1		T115	1		T44	1
auto[3758096384:3892314111]	auto[0]	54	1			T15	1		T47	1		T23	1
auto[3758096384:3892314111]	auto[1]	57	1			T151	1		T207	1		T52	1
auto[3892314112:4026531839]	auto[0]	47	1			T24	1		T38	1		T6	1
auto[3892314112:4026531839]	auto[1]	53	1			T26	1		T37	1		T49	1
auto[4026531840:4160749567]	auto[0]	60	1			T2	1		T198	2		T52	1
auto[4026531840:4160749567]	auto[1]	49	1			T152	1		T191	1		T195	1
auto[4160749568:4294967295]	auto[0]	51	1			T5	2		T43	1		T52	2
auto[4160749568:4294967295]	auto[1]	54	1			T204	1		T43	1		T401	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1598

1

T2

6

T3

2

T14

1

auto[1]

1633

1

T3

2

T14

2

T15

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T2	2		T47	1		T134	1
auto[134217728:268435455]	99	1			T47	1		T50	1		T48	1
auto[268435456:402653183]	104	1			T15	1		T5	1		T210	1
auto[402653184:536870911]	86	1			T134	1		T123	1		T5	1
auto[536870912:671088639]	103	1			T47	1		T24	1		T151	1
auto[671088640:805306367]	97	1			T50	2		T123	1		T61	1
auto[805306368:939524095]	125	1			T47	2		T23	2		T24	1
auto[939524096:1073741823]	101	1			T3	2		T15	1		T16	1
auto[1073741824:1207959551]	80	1			T34	1		T47	1		T48	1
auto[1207959552:1342177279]	101	1			T24	1		T204	1		T43	1
auto[1342177280:1476395007]	102	1			T43	1		T401	1		T44	2
auto[1476395008:1610612735]	103	1			T16	1		T23	1		T24	1
auto[1610612736:1744830463]	93	1			T123	1		T24	1		T43	1
auto[1744830464:1879048191]	88	1			T2	1		T16	1		T34	1
auto[1879048192:2013265919]	105	1			T2	1		T23	1		T123	1
auto[2013265920:2147483647]	106	1			T15	1		T24	1		T151	1
auto[2147483648:2281701375]	110	1			T23	1		T37	1		T55	1
auto[2281701376:2415919103]	89	1			T134	1		T23	1		T151	1
auto[2415919104:2550136831]	95	1			T47	1		T38	1		T207	1
auto[2550136832:2684354559]	117	1			T14	1		T210	1		T101	1
auto[2684354560:2818572287]	82	1			T43	1		T25	1		T198	1
auto[2818572288:2952790015]	113	1			T149	2		T37	1		T204	1
auto[2952790016:3087007743]	96	1			T2	2		T3	1		T34	1
auto[3087007744:3221225471]	121	1			T3	1		T134	1		T23	1
auto[3221225472:3355443199]	99	1			T47	1		T50	1		T5	2
auto[3355443200:3489660927]	97	1			T15	1		T26	1		T5	1
auto[3489660928:3623878655]	110	1			T16	1		T134	1		T5	1
auto[3623878656:3758096383]	109	1			T14	1		T23	1		T43	1
auto[3758096384:3892314111]	109	1			T43	1		T56	1		T52	4
auto[3892314112:4026531839]	110	1			T14	1		T43	1		T401	1
auto[4026531840:4160749567]	91	1			T5	1		T43	1		T38	1
auto[4160749568:4294967295]	87	1			T8	1		T52	1		T44	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	55	1			T2	2		T47	1		T134	1
auto[0:134217727]	auto[1]	48	1			T43	1		T44	1		T81	1
auto[134217728:268435455]	auto[0]	53	1			T50	1		T6	1		T101	1
auto[134217728:268435455]	auto[1]	46	1			T47	1		T48	1		T151	1
auto[268435456:402653183]	auto[0]	39	1			T5	1		T401	1		T6	1
auto[268435456:402653183]	auto[1]	65	1			T15	1		T210	1		T52	2
auto[402653184:536870911]	auto[0]	39	1			T5	1		T401	1		T44	2
auto[402653184:536870911]	auto[1]	47	1			T134	1		T123	1		T44	1
auto[536870912:671088639]	auto[0]	48	1			T47	1		T207	2		T206	1
auto[536870912:671088639]	auto[1]	55	1			T24	1		T151	1		T6	1
auto[671088640:805306367]	auto[0]	56	1			T50	2		T53	1		T52	1
auto[671088640:805306367]	auto[1]	41	1			T123	1		T61	1		T241	1
auto[805306368:939524095]	auto[0]	62	1			T47	1		T23	1		T24	1
auto[805306368:939524095]	auto[1]	63	1			T47	1		T23	1		T37	1
auto[939524096:1073741823]	auto[0]	48	1			T3	1		T198	1		T81	1
auto[939524096:1073741823]	auto[1]	53	1			T3	1		T15	1		T16	1
auto[1073741824:1207959551]	auto[0]	30	1			T34	1		T47	1		T48	1
auto[1073741824:1207959551]	auto[1]	50	1			T204	1		T215	1		T140	1
auto[1207959552:1342177279]	auto[0]	56	1			T24	1		T204	1		T43	1
auto[1207959552:1342177279]	auto[1]	45	1			T198	1		T52	1		T301	1
auto[1342177280:1476395007]	auto[0]	49	1			T44	2		T274	1		T301	1
auto[1342177280:1476395007]	auto[1]	53	1			T43	1		T401	1		T70	2
auto[1476395008:1610612735]	auto[0]	54	1			T16	1		T23	1		T24	1
auto[1476395008:1610612735]	auto[1]	49	1			T43	1		T61	1		T52	1
auto[1610612736:1744830463]	auto[0]	41	1			T24	1		T43	1		T401	1
auto[1610612736:1744830463]	auto[1]	52	1			T123	1		T70	1		T274	1
auto[1744830464:1879048191]	auto[0]	46	1			T2	1		T16	1		T50	1
auto[1744830464:1879048191]	auto[1]	42	1			T34	1		T55	1		T44	1
auto[1879048192:2013265919]	auto[0]	48	1			T2	1		T23	1		T38	1
auto[1879048192:2013265919]	auto[1]	57	1			T123	1		T37	1		T210	1
auto[2013265920:2147483647]	auto[0]	56	1			T15	1		T24	1		T151	1
auto[2013265920:2147483647]	auto[1]	50	1			T204	1		T43	1		T55	1
auto[2147483648:2281701375]	auto[0]	52	1			T23	1		T198	1		T213	1
auto[2147483648:2281701375]	auto[1]	58	1			T37	1		T55	1		T25	1
auto[2281701376:2415919103]	auto[0]	47	1			T61	1		T25	1		T8	1
auto[2281701376:2415919103]	auto[1]	42	1			T134	1		T23	1		T151	1
auto[2415919104:2550136831]	auto[0]	43	1			T38	1		T52	1		T80	1
auto[2415919104:2550136831]	auto[1]	52	1			T47	1		T207	1		T28	1
auto[2550136832:2684354559]	auto[0]	61	1			T210	1		T101	1		T52	1
auto[2550136832:2684354559]	auto[1]	56	1			T14	1		T52	2		T44	3
auto[2684354560:2818572287]	auto[0]	34	1			T70	1		T84	1		T241	2
auto[2684354560:2818572287]	auto[1]	48	1			T43	1		T25	1		T198	1
auto[2818572288:2952790015]	auto[0]	64	1			T149	1		T401	1		T198	1
auto[2818572288:2952790015]	auto[1]	49	1			T149	1		T37	1		T204	1
auto[2952790016:3087007743]	auto[0]	52	1			T2	2		T134	1		T43	2
auto[2952790016:3087007743]	auto[1]	44	1			T3	1		T34	1		T198	1
auto[3087007744:3221225471]	auto[0]	55	1			T3	1		T23	1		T5	1
auto[3087007744:3221225471]	auto[1]	66	1			T134	1		T43	1		T52	1
auto[3221225472:3355443199]	auto[0]	51	1			T47	1		T50	1		T5	1
auto[3221225472:3355443199]	auto[1]	48	1			T5	1		T43	1		T206	1
auto[3355443200:3489660927]	auto[0]	52	1			T210	1		T43	1		T52	1
auto[3355443200:3489660927]	auto[1]	45	1			T15	1		T26	1		T5	1
auto[3489660928:3623878655]	auto[0]	52	1			T16	1		T5	1		T43	1
auto[3489660928:3623878655]	auto[1]	58	1			T134	1		T205	1		T44	1
auto[3623878656:3758096383]	auto[0]	52	1			T25	2		T213	1		T52	1
auto[3623878656:3758096383]	auto[1]	57	1			T14	1		T23	1		T43	1
auto[3758096384:3892314111]	auto[0]	59	1			T56	1		T52	2		T70	1
auto[3758096384:3892314111]	auto[1]	50	1			T43	1		T52	2		T115	1
auto[3892314112:4026531839]	auto[0]	58	1			T14	1		T401	1		T215	1
auto[3892314112:4026531839]	auto[1]	52	1			T43	1		T52	2		T44	2
auto[4026531840:4160749567]	auto[0]	43	1			T43	1		T38	1		T6	1
auto[4026531840:4160749567]	auto[1]	48	1			T5	1		T44	1		T70	2
auto[4160749568:4294967295]	auto[0]	43	1			T8	1		T44	1		T67	2
auto[4160749568:4294967295]	auto[1]	44	1			T52	1		T44	1		T70	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1584

1

T2

6

T3

2

T14

1

auto[1]

1647

1

T3

2

T14

2

T15

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	68	1			T3	1		T134	1		T43	1
auto[134217728:268435455]	109	1			T26	1		T43	1		T207	1
auto[268435456:402653183]	104	1			T23	1		T401	1		T25	1
auto[402653184:536870911]	101	1			T14	1		T134	1		T48	1
auto[536870912:671088639]	100	1			T34	1		T149	1		T43	1
auto[671088640:805306367]	113	1			T16	1		T34	1		T23	1
auto[805306368:939524095]	92	1			T43	3		T25	1		T198	1
auto[939524096:1073741823]	79	1			T14	1		T47	2		T5	2
auto[1073741824:1207959551]	77	1			T16	1		T204	1		T43	2
auto[1207959552:1342177279]	92	1			T16	1		T47	1		T50	1
auto[1342177280:1476395007]	108	1			T47	1		T204	1		T210	1
auto[1476395008:1610612735]	114	1			T15	1		T123	1		T43	1
auto[1610612736:1744830463]	89	1			T2	1		T3	1		T5	1
auto[1744830464:1879048191]	94	1			T50	1		T24	1		T151	1
auto[1879048192:2013265919]	111	1			T2	1		T15	1		T47	1
auto[2013265920:2147483647]	102	1			T5	1		T38	1		T198	1
auto[2147483648:2281701375]	111	1			T14	1		T149	1		T25	1
auto[2281701376:2415919103]	96	1			T15	1		T26	1		T24	1
auto[2415919104:2550136831]	108	1			T3	1		T15	1		T123	1
auto[2550136832:2684354559]	110	1			T34	1		T50	1		T123	1
auto[2684354560:2818572287]	104	1			T50	1		T23	2		T204	1
auto[2818572288:2952790015]	107	1			T47	1		T24	1		T101	1
auto[2952790016:3087007743]	117	1			T37	1		T38	1		T44	1
auto[3087007744:3221225471]	95	1			T2	1		T23	1		T151	1
auto[3221225472:3355443199]	110	1			T5	1		T101	1		T25	1
auto[3355443200:3489660927]	111	1			T2	1		T134	1		T50	1
auto[3489660928:3623878655]	96	1			T2	1		T43	1		T401	1
auto[3623878656:3758096383]	104	1			T23	1		T401	1		T55	1
auto[3758096384:3892314111]	105	1			T3	1		T5	1		T37	1
auto[3892314112:4026531839]	102	1			T2	1		T16	1		T47	1
auto[4026531840:4160749567]	96	1			T50	1		T23	1		T48	1
auto[4160749568:4294967295]	106	1			T47	1		T23	1		T5	1