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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2820 1 T2 6 T3 4 T14 3
auto[1] 303 1 T123 6 T151 7 T140 7



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 89 1 T134 1 T5 1 T151 1
auto[134217728:268435455] 94 1 T134 1 T123 1 T55 1
auto[268435456:402653183] 73 1 T16 2 T47 1 T5 1
auto[402653184:536870911] 100 1 T123 1 T210 1 T43 1
auto[536870912:671088639] 101 1 T3 1 T15 1 T34 1
auto[671088640:805306367] 99 1 T16 1 T47 1 T26 1
auto[805306368:939524095] 100 1 T123 1 T43 2 T61 1
auto[939524096:1073741823] 97 1 T2 1 T23 1 T149 1
auto[1073741824:1207959551] 102 1 T34 1 T48 1 T24 1
auto[1207959552:1342177279] 108 1 T2 1 T43 1 T401 1
auto[1342177280:1476395007] 93 1 T14 1 T47 1 T43 1
auto[1476395008:1610612735] 96 1 T34 1 T23 1 T43 1
auto[1610612736:1744830463] 102 1 T3 2 T47 1 T24 1
auto[1744830464:1879048191] 100 1 T16 1 T123 1 T24 1
auto[1879048192:2013265919] 98 1 T134 1 T123 1 T101 1
auto[2013265920:2147483647] 98 1 T14 1 T15 1 T38 1
auto[2147483648:2281701375] 92 1 T2 1 T23 1 T5 1
auto[2281701376:2415919103] 104 1 T2 2 T50 1 T48 1
auto[2415919104:2550136831] 82 1 T151 1 T37 2 T43 1
auto[2550136832:2684354559] 99 1 T15 1 T47 2 T43 1
auto[2684354560:2818572287] 95 1 T151 1 T204 1 T25 1
auto[2818572288:2952790015] 114 1 T47 1 T134 1 T123 1
auto[2952790016:3087007743] 100 1 T134 1 T23 1 T37 1
auto[3087007744:3221225471] 85 1 T123 1 T53 1 T52 2
auto[3221225472:3355443199] 113 1 T47 1 T23 1 T61 1
auto[3355443200:3489660927] 104 1 T24 1 T5 1 T149 1
auto[3489660928:3623878655] 95 1 T14 1 T151 1 T215 1
auto[3623878656:3758096383] 87 1 T3 1 T23 1 T151 1
auto[3758096384:3892314111] 103 1 T43 1 T38 2 T25 2
auto[3892314112:4026531839] 94 1 T2 1 T123 3 T207 1
auto[4026531840:4160749567] 99 1 T23 1 T24 1 T5 1
auto[4160749568:4294967295] 107 1 T15 1 T24 1 T37 1



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 74 1 T134 1 T5 1 T140 1
auto[0:134217727] auto[1] 15 1 T151 1 T152 2 T262 1
auto[134217728:268435455] auto[0] 79 1 T134 1 T55 1 T28 1
auto[134217728:268435455] auto[1] 15 1 T123 1 T191 2 T313 1
auto[268435456:402653183] auto[0] 67 1 T16 2 T47 1 T5 1
auto[268435456:402653183] auto[1] 6 1 T151 1 T142 1 T280 1
auto[402653184:536870911] auto[0] 91 1 T123 1 T210 1 T43 1
auto[402653184:536870911] auto[1] 9 1 T140 2 T331 1 T313 1
auto[536870912:671088639] auto[0] 88 1 T3 1 T15 1 T34 1
auto[536870912:671088639] auto[1] 13 1 T140 1 T331 1 T280 1
auto[671088640:805306367] auto[0] 94 1 T16 1 T47 1 T26 1
auto[671088640:805306367] auto[1] 5 1 T153 1 T404 1 T422 1
auto[805306368:939524095] auto[0] 92 1 T43 2 T61 1 T56 1
auto[805306368:939524095] auto[1] 8 1 T123 1 T152 1 T280 1
auto[939524096:1073741823] auto[0] 86 1 T2 1 T23 1 T149 1
auto[939524096:1073741823] auto[1] 11 1 T152 1 T141 1 T262 1
auto[1073741824:1207959551] auto[0] 96 1 T34 1 T48 1 T24 1
auto[1073741824:1207959551] auto[1] 6 1 T151 1 T152 2 T386 1
auto[1207959552:1342177279] auto[0] 100 1 T2 1 T43 1 T401 1
auto[1207959552:1342177279] auto[1] 8 1 T140 1 T153 1 T313 1
auto[1342177280:1476395007] auto[0] 84 1 T14 1 T47 1 T43 1
auto[1342177280:1476395007] auto[1] 9 1 T191 1 T280 1 T408 1
auto[1476395008:1610612735] auto[0] 87 1 T34 1 T23 1 T43 1
auto[1476395008:1610612735] auto[1] 9 1 T152 1 T239 1 T408 1
auto[1610612736:1744830463] auto[0] 93 1 T3 2 T47 1 T24 1
auto[1610612736:1744830463] auto[1] 9 1 T153 1 T331 1 T385 1
auto[1744830464:1879048191] auto[0] 92 1 T16 1 T24 1 T5 1
auto[1744830464:1879048191] auto[1] 8 1 T123 1 T151 1 T280 1
auto[1879048192:2013265919] auto[0] 85 1 T134 1 T123 1 T101 1
auto[1879048192:2013265919] auto[1] 13 1 T153 1 T141 1 T262 3
auto[2013265920:2147483647] auto[0] 92 1 T14 1 T15 1 T38 1
auto[2013265920:2147483647] auto[1] 6 1 T191 2 T331 1 T408 1
auto[2147483648:2281701375] auto[0] 81 1 T2 1 T23 1 T5 1
auto[2147483648:2281701375] auto[1] 11 1 T140 1 T153 1 T331 1
auto[2281701376:2415919103] auto[0] 89 1 T2 2 T50 1 T48 1
auto[2281701376:2415919103] auto[1] 15 1 T153 2 T191 2 T280 1
auto[2415919104:2550136831] auto[0] 75 1 T37 2 T43 1 T6 1
auto[2415919104:2550136831] auto[1] 7 1 T151 1 T313 1 T415 1
auto[2550136832:2684354559] auto[0] 91 1 T15 1 T47 2 T43 1
auto[2550136832:2684354559] auto[1] 8 1 T385 1 T408 1 T415 1
auto[2684354560:2818572287] auto[0] 82 1 T151 1 T204 1 T25 1
auto[2684354560:2818572287] auto[1] 13 1 T140 1 T141 2 T331 1
auto[2818572288:2952790015] auto[0] 108 1 T47 1 T134 1 T123 1
auto[2818572288:2952790015] auto[1] 6 1 T191 1 T262 1 T402 1
auto[2952790016:3087007743] auto[0] 89 1 T134 1 T23 1 T37 1
auto[2952790016:3087007743] auto[1] 11 1 T191 1 T331 1 T262 1
auto[3087007744:3221225471] auto[0] 75 1 T123 1 T53 1 T52 2
auto[3087007744:3221225471] auto[1] 10 1 T152 1 T153 1 T313 1
auto[3221225472:3355443199] auto[0] 100 1 T47 1 T23 1 T61 1
auto[3221225472:3355443199] auto[1] 13 1 T152 2 T331 1 T385 1
auto[3355443200:3489660927] auto[0] 89 1 T24 1 T5 1 T149 1
auto[3355443200:3489660927] auto[1] 15 1 T151 1 T152 1 T280 1
auto[3489660928:3623878655] auto[0] 93 1 T14 1 T151 1 T215 1
auto[3489660928:3623878655] auto[1] 2 1 T420 1 T422 1 - -
auto[3623878656:3758096383] auto[0] 77 1 T3 1 T23 1 T44 2
auto[3623878656:3758096383] auto[1] 10 1 T151 1 T153 1 T357 1
auto[3758096384:3892314111] auto[0] 97 1 T43 1 T38 2 T25 2
auto[3758096384:3892314111] auto[1] 6 1 T262 1 T336 1 T425 1
auto[3892314112:4026531839] auto[0] 86 1 T2 1 T207 1 T80 1
auto[3892314112:4026531839] auto[1] 8 1 T123 3 T152 1 T414 1
auto[4026531840:4160749567] auto[0] 90 1 T23 1 T24 1 T5 1
auto[4026531840:4160749567] auto[1] 9 1 T152 1 T141 1 T239 1
auto[4160749568:4294967295] auto[0] 98 1 T15 1 T24 1 T37 1
auto[4160749568:4294967295] auto[1] 9 1 T140 1 T142 1 T387 1

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