dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1575 1 T2 5 T3 2 T14 2
auto[1] 1655 1 T2 1 T3 2 T14 1


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 98 1 T101 1 T198 1 T52 2
auto[134217728:268435455] 106 1 T2 1 T34 1 T5 1
auto[268435456:402653183] 119 1 T47 2 T24 1 T5 1
auto[402653184:536870911] 116 1 T15 1 T43 1 T6 1
auto[536870912:671088639] 112 1 T50 1 T24 1 T198 2
auto[671088640:805306367] 101 1 T134 1 T5 1 T210 1
auto[805306368:939524095] 82 1 T3 1 T50 2 T8 1
auto[939524096:1073741823] 121 1 T15 1 T50 1 T24 1
auto[1073741824:1207959551] 97 1 T134 1 T56 1 T206 1
auto[1207959552:1342177279] 104 1 T23 1 T5 1 T151 1
auto[1342177280:1476395007] 92 1 T3 1 T14 1 T151 1
auto[1476395008:1610612735] 107 1 T50 1 T23 1 T6 1
auto[1610612736:1744830463] 118 1 T15 1 T5 1 T43 1
auto[1744830464:1879048191] 92 1 T2 1 T401 2 T140 1
auto[1879048192:2013265919] 114 1 T14 1 T134 1 T204 1
auto[2013265920:2147483647] 97 1 T23 1 T37 2 T43 2
auto[2147483648:2281701375] 92 1 T2 2 T23 1 T48 1
auto[2281701376:2415919103] 92 1 T16 1 T34 1 T5 1
auto[2415919104:2550136831] 106 1 T401 1 T28 1 T81 1
auto[2550136832:2684354559] 82 1 T15 1 T16 1 T55 1
auto[2684354560:2818572287] 95 1 T134 2 T24 1 T5 1
auto[2818572288:2952790015] 104 1 T47 1 T149 1 T43 2
auto[2952790016:3087007743] 105 1 T2 1 T50 1 T23 2
auto[3087007744:3221225471] 100 1 T14 1 T47 2 T5 1
auto[3221225472:3355443199] 92 1 T2 1 T23 1 T5 1
auto[3355443200:3489660927] 91 1 T16 1 T24 1 T5 1
auto[3489660928:3623878655] 100 1 T3 1 T16 1 T43 1
auto[3623878656:3758096383] 90 1 T26 1 T151 1 T204 1
auto[3758096384:3892314111] 107 1 T134 1 T123 1 T151 1
auto[3892314112:4026531839] 90 1 T3 1 T34 1 T47 1
auto[4026531840:4160749567] 109 1 T26 1 T23 1 T48 1
auto[4160749568:4294967295] 99 1 T47 2 T123 1 T37 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 50 1 T101 1 T198 1 T52 1
auto[0:134217727] auto[1] 48 1 T52 1 T44 3 T70 1
auto[134217728:268435455] auto[0] 50 1 T2 1 T5 1 T401 1
auto[134217728:268435455] auto[1] 56 1 T34 1 T204 1 T43 1
auto[268435456:402653183] auto[0] 64 1 T47 2 T24 1 T215 1
auto[268435456:402653183] auto[1] 55 1 T5 1 T37 1 T25 1
auto[402653184:536870911] auto[0] 54 1 T6 1 T25 1 T198 1
auto[402653184:536870911] auto[1] 62 1 T15 1 T43 1 T70 1
auto[536870912:671088639] auto[0] 55 1 T50 1 T24 1 T198 2
auto[536870912:671088639] auto[1] 57 1 T52 1 T44 1 T218 1
auto[671088640:805306367] auto[0] 52 1 T5 1 T43 1 T38 1
auto[671088640:805306367] auto[1] 49 1 T134 1 T210 1 T205 2
auto[805306368:939524095] auto[0] 37 1 T3 1 T50 2 T52 1
auto[805306368:939524095] auto[1] 45 1 T8 1 T52 1 T65 1
auto[939524096:1073741823] auto[0] 56 1 T15 1 T50 1 T43 1
auto[939524096:1073741823] auto[1] 65 1 T24 1 T5 1 T150 1
auto[1073741824:1207959551] auto[0] 55 1 T134 1 T206 1 T8 1
auto[1073741824:1207959551] auto[1] 42 1 T56 1 T44 1 T67 1
auto[1207959552:1342177279] auto[0] 56 1 T23 1 T5 1 T53 1
auto[1207959552:1342177279] auto[1] 48 1 T151 1 T198 1 T52 1
auto[1342177280:1476395007] auto[0] 45 1 T3 1 T14 1 T151 1
auto[1342177280:1476395007] auto[1] 47 1 T52 1 T44 1 T70 1
auto[1476395008:1610612735] auto[0] 48 1 T50 1 T6 1 T101 1
auto[1476395008:1610612735] auto[1] 59 1 T23 1 T61 1 T44 2
auto[1610612736:1744830463] auto[0] 62 1 T5 1 T53 1 T70 2
auto[1610612736:1744830463] auto[1] 56 1 T15 1 T43 1 T101 1
auto[1744830464:1879048191] auto[0] 49 1 T2 1 T401 2 T52 1
auto[1744830464:1879048191] auto[1] 43 1 T140 1 T199 3 T413 1
auto[1879048192:2013265919] auto[0] 59 1 T14 1 T134 1 T25 1
auto[1879048192:2013265919] auto[1] 55 1 T204 1 T55 1 T198 1
auto[2013265920:2147483647] auto[0] 51 1 T23 1 T43 1 T53 1
auto[2013265920:2147483647] auto[1] 46 1 T37 2 T43 1 T44 1
auto[2147483648:2281701375] auto[0] 48 1 T2 1 T23 1 T48 1
auto[2147483648:2281701375] auto[1] 44 1 T2 1 T49 1 T52 1
auto[2281701376:2415919103] auto[0] 44 1 T16 1 T5 1 T210 1
auto[2281701376:2415919103] auto[1] 48 1 T34 1 T43 1 T52 1
auto[2415919104:2550136831] auto[0] 45 1 T84 1 T286 1 T190 1
auto[2415919104:2550136831] auto[1] 61 1 T401 1 T28 1 T81 1
auto[2550136832:2684354559] auto[0] 43 1 T15 1 T207 1 T52 1
auto[2550136832:2684354559] auto[1] 39 1 T16 1 T55 1 T215 1
auto[2684354560:2818572287] auto[0] 47 1 T5 1 T210 1 T25 1
auto[2684354560:2818572287] auto[1] 48 1 T134 2 T24 1 T61 1
auto[2818572288:2952790015] auto[0] 48 1 T43 2 T6 1 T101 1
auto[2818572288:2952790015] auto[1] 56 1 T47 1 T149 1 T52 1
auto[2952790016:3087007743] auto[0] 49 1 T2 1 T50 1 T23 1
auto[2952790016:3087007743] auto[1] 56 1 T23 1 T123 2 T52 1
auto[3087007744:3221225471] auto[0] 44 1 T47 1 T204 1 T43 1
auto[3087007744:3221225471] auto[1] 56 1 T14 1 T47 1 T5 1
auto[3221225472:3355443199] auto[0] 49 1 T2 1 T5 1 T38 1
auto[3221225472:3355443199] auto[1] 43 1 T23 1 T43 1 T215 1
auto[3355443200:3489660927] auto[0] 37 1 T16 1 T24 1 T43 1
auto[3355443200:3489660927] auto[1] 54 1 T5 1 T43 1 T82 1
auto[3489660928:3623878655] auto[0] 45 1 T16 1 T25 1 T30 1
auto[3489660928:3623878655] auto[1] 55 1 T3 1 T43 1 T52 2
auto[3623878656:3758096383] auto[0] 44 1 T401 1 T44 1 T82 1
auto[3623878656:3758096383] auto[1] 46 1 T26 1 T151 1 T204 1
auto[3758096384:3892314111] auto[0] 48 1 T44 1 T58 1 T199 1
auto[3758096384:3892314111] auto[1] 59 1 T134 1 T123 1 T151 1
auto[3892314112:4026531839] auto[0] 38 1 T47 1 T101 1 T52 1
auto[3892314112:4026531839] auto[1] 52 1 T3 1 T34 1 T56 1
auto[4026531840:4160749567] auto[0] 54 1 T23 1 T43 1 T38 1
auto[4026531840:4160749567] auto[1] 55 1 T26 1 T48 1 T149 1
auto[4160749568:4294967295] auto[0] 49 1 T47 2 T44 1 T274 1
auto[4160749568:4294967295] auto[1] 50 1 T123 1 T37 1 T198 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%