Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.07 97.71 98.38 100.00 99.11 98.41 91.51


Total test records in report: 1068
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
T1007 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3793679347 Mar 07 01:19:04 PM PST 24 Mar 07 01:19:06 PM PST 24 48162741 ps
T1008 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2365746311 Mar 07 01:18:53 PM PST 24 Mar 07 01:19:04 PM PST 24 158787080 ps
T1009 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2812765356 Mar 07 01:19:11 PM PST 24 Mar 07 01:19:35 PM PST 24 4067246160 ps
T1010 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1701049571 Mar 07 01:19:20 PM PST 24 Mar 07 01:19:22 PM PST 24 40894020 ps
T165 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2219941134 Mar 07 01:19:07 PM PST 24 Mar 07 01:19:17 PM PST 24 826667163 ps
T1011 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3166768038 Mar 07 01:19:24 PM PST 24 Mar 07 01:19:24 PM PST 24 38992553 ps
T1012 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3744453515 Mar 07 01:19:23 PM PST 24 Mar 07 01:19:24 PM PST 24 13298039 ps
T1013 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1389055400 Mar 07 01:19:09 PM PST 24 Mar 07 01:19:10 PM PST 24 263438227 ps
T1014 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.4155802123 Mar 07 01:18:49 PM PST 24 Mar 07 01:18:50 PM PST 24 23936486 ps
T1015 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.4179455942 Mar 07 01:19:18 PM PST 24 Mar 07 01:19:19 PM PST 24 12483424 ps
T1016 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.372635484 Mar 07 01:19:23 PM PST 24 Mar 07 01:19:23 PM PST 24 11890976 ps
T1017 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1800919816 Mar 07 01:18:49 PM PST 24 Mar 07 01:18:51 PM PST 24 49540560 ps
T1018 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.905963585 Mar 07 01:19:21 PM PST 24 Mar 07 01:19:22 PM PST 24 14912638 ps
T1019 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3598002635 Mar 07 01:18:48 PM PST 24 Mar 07 01:18:50 PM PST 24 211443005 ps
T164 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2405339724 Mar 07 01:18:55 PM PST 24 Mar 07 01:18:59 PM PST 24 192806065 ps
T1020 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3599315313 Mar 07 01:19:11 PM PST 24 Mar 07 01:19:14 PM PST 24 51015662 ps
T1021 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1167148339 Mar 07 01:19:16 PM PST 24 Mar 07 01:19:24 PM PST 24 643037544 ps
T1022 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.709673336 Mar 07 01:19:05 PM PST 24 Mar 07 01:19:18 PM PST 24 699767537 ps
T1023 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1074153572 Mar 07 01:19:04 PM PST 24 Mar 07 01:19:09 PM PST 24 167486408 ps
T1024 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3428956293 Mar 07 01:19:03 PM PST 24 Mar 07 01:19:05 PM PST 24 16133453 ps
T1025 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1001622189 Mar 07 01:19:23 PM PST 24 Mar 07 01:19:24 PM PST 24 11570764 ps
T1026 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3372672810 Mar 07 01:19:21 PM PST 24 Mar 07 01:19:23 PM PST 24 18838609 ps
T1027 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3820788172 Mar 07 01:19:05 PM PST 24 Mar 07 01:19:10 PM PST 24 284869762 ps
T1028 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4283107831 Mar 07 01:18:50 PM PST 24 Mar 07 01:18:52 PM PST 24 38376602 ps
T1029 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3394658033 Mar 07 01:19:04 PM PST 24 Mar 07 01:19:05 PM PST 24 229278726 ps
T1030 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1186362590 Mar 07 01:19:25 PM PST 24 Mar 07 01:19:25 PM PST 24 38284091 ps
T1031 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2927940617 Mar 07 01:19:03 PM PST 24 Mar 07 01:19:05 PM PST 24 40988607 ps
T1032 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.4136232407 Mar 07 01:19:06 PM PST 24 Mar 07 01:19:10 PM PST 24 291292117 ps
T1033 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2572263477 Mar 07 01:19:21 PM PST 24 Mar 07 01:19:22 PM PST 24 34324767 ps
T1034 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3873114881 Mar 07 01:19:02 PM PST 24 Mar 07 01:19:04 PM PST 24 112919219 ps
T1035 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1873196885 Mar 07 01:19:06 PM PST 24 Mar 07 01:19:12 PM PST 24 99845877 ps
T1036 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2156401095 Mar 07 01:18:49 PM PST 24 Mar 07 01:18:51 PM PST 24 43539790 ps
T1037 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1778677499 Mar 07 01:18:51 PM PST 24 Mar 07 01:18:59 PM PST 24 191074738 ps
T1038 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.826030010 Mar 07 01:19:08 PM PST 24 Mar 07 01:19:09 PM PST 24 98057266 ps
T1039 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1405427748 Mar 07 01:18:53 PM PST 24 Mar 07 01:18:58 PM PST 24 99446298 ps
T1040 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3134849746 Mar 07 01:18:39 PM PST 24 Mar 07 01:18:42 PM PST 24 199933490 ps
T1041 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.292592853 Mar 07 01:18:50 PM PST 24 Mar 07 01:19:03 PM PST 24 1929580231 ps
T1042 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2064890526 Mar 07 01:19:16 PM PST 24 Mar 07 01:19:18 PM PST 24 33301485 ps
T181 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1848916487 Mar 07 01:19:04 PM PST 24 Mar 07 01:19:08 PM PST 24 99304359 ps
T1043 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1768287895 Mar 07 01:18:51 PM PST 24 Mar 07 01:18:53 PM PST 24 296386679 ps
T1044 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3121336377 Mar 07 01:19:10 PM PST 24 Mar 07 01:19:11 PM PST 24 44874820 ps
T1045 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2446411849 Mar 07 01:18:48 PM PST 24 Mar 07 01:18:53 PM PST 24 497871708 ps
T1046 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3551498118 Mar 07 01:18:53 PM PST 24 Mar 07 01:18:57 PM PST 24 36423191 ps
T1047 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2129973491 Mar 07 01:19:21 PM PST 24 Mar 07 01:19:22 PM PST 24 45063404 ps
T1048 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1929950144 Mar 07 01:19:22 PM PST 24 Mar 07 01:19:23 PM PST 24 27648741 ps
T1049 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3738680558 Mar 07 01:19:21 PM PST 24 Mar 07 01:19:22 PM PST 24 15257817 ps
T1050 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1519549736 Mar 07 01:18:53 PM PST 24 Mar 07 01:18:56 PM PST 24 129044241 ps
T1051 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2036310067 Mar 07 01:19:04 PM PST 24 Mar 07 01:19:06 PM PST 24 52632096 ps
T1052 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3901532594 Mar 07 01:19:06 PM PST 24 Mar 07 01:19:07 PM PST 24 8075940 ps
T1053 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.4053805693 Mar 07 01:19:05 PM PST 24 Mar 07 01:19:09 PM PST 24 157313244 ps
T1054 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3251756234 Mar 07 01:18:48 PM PST 24 Mar 07 01:18:49 PM PST 24 17056306 ps
T1055 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2552613858 Mar 07 01:19:03 PM PST 24 Mar 07 01:19:06 PM PST 24 631303508 ps
T1056 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.623758617 Mar 07 01:18:55 PM PST 24 Mar 07 01:18:57 PM PST 24 12878869 ps
T1057 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3823961206 Mar 07 01:19:18 PM PST 24 Mar 07 01:19:20 PM PST 24 32542851 ps
T1058 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1371919878 Mar 07 01:19:18 PM PST 24 Mar 07 01:19:21 PM PST 24 729024657 ps
T1059 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1051648625 Mar 07 01:18:52 PM PST 24 Mar 07 01:18:58 PM PST 24 137547876 ps
T1060 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1964321688 Mar 07 01:19:08 PM PST 24 Mar 07 01:19:09 PM PST 24 93439500 ps
T167 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1999512650 Mar 07 01:19:03 PM PST 24 Mar 07 01:19:37 PM PST 24 1405350502 ps
T174 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.914426469 Mar 07 01:19:07 PM PST 24 Mar 07 01:19:15 PM PST 24 1236671768 ps
T1061 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4031832826 Mar 07 01:18:49 PM PST 24 Mar 07 01:18:54 PM PST 24 473313397 ps
T1062 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1528811052 Mar 07 01:19:11 PM PST 24 Mar 07 01:19:12 PM PST 24 34983108 ps
T1063 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3880642532 Mar 07 01:18:39 PM PST 24 Mar 07 01:18:47 PM PST 24 267966091 ps
T1064 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1482016740 Mar 07 01:19:06 PM PST 24 Mar 07 01:19:09 PM PST 24 277590558 ps
T1065 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2063872074 Mar 07 01:18:50 PM PST 24 Mar 07 01:18:52 PM PST 24 43608714 ps
T176 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2319908625 Mar 07 01:19:03 PM PST 24 Mar 07 01:19:07 PM PST 24 90707398 ps
T1066 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.121619114 Mar 07 01:18:53 PM PST 24 Mar 07 01:18:59 PM PST 24 365981483 ps
T1067 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1239509017 Mar 07 01:19:04 PM PST 24 Mar 07 01:19:09 PM PST 24 257885298 ps
T1068 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3965280875 Mar 07 01:19:07 PM PST 24 Mar 07 01:19:08 PM PST 24 18590889 ps

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.4223061834
Short name T15
Test name
Test status
Simulation time 58623422 ps
CPU time 3.83 seconds
Started Mar 07 02:51:26 PM PST 24
Finished Mar 07 02:51:30 PM PST 24
Peak memory 209348 kb
Host smart-cd168425-4792-4278-9339-7afefd3c22e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223061834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.4223061834
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2314558387
Short name T44
Test name
Test status
Simulation time 9982855553 ps
CPU time 102.76 seconds
Started Mar 07 02:48:36 PM PST 24
Finished Mar 07 02:50:19 PM PST 24
Peak memory 215400 kb
Host smart-14d39b40-2e11-4932-9107-083ca0c2abb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314558387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2314558387
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3963474648
Short name T5
Test name
Test status
Simulation time 1244994366 ps
CPU time 10.47 seconds
Started Mar 07 02:47:55 PM PST 24
Finished Mar 07 02:48:06 PM PST 24
Peak memory 220520 kb
Host smart-2fbbc053-dceb-4056-8ed7-885ec4b31970
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963474648 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3963474648
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.4227740112
Short name T47
Test name
Test status
Simulation time 370792146 ps
CPU time 15.8 seconds
Started Mar 07 02:48:59 PM PST 24
Finished Mar 07 02:49:15 PM PST 24
Peak memory 222816 kb
Host smart-8c98a844-4853-4eab-a2fc-81769a58e9a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227740112 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.4227740112
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2031026707
Short name T12
Test name
Test status
Simulation time 1285158439 ps
CPU time 19.96 seconds
Started Mar 07 02:48:04 PM PST 24
Finished Mar 07 02:48:25 PM PST 24
Peak memory 233404 kb
Host smart-98e3cdc4-0612-4469-958a-703857eb7441
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031026707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2031026707
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.1572226599
Short name T69
Test name
Test status
Simulation time 336690500 ps
CPU time 11.87 seconds
Started Mar 07 02:48:51 PM PST 24
Finished Mar 07 02:49:03 PM PST 24
Peak memory 220276 kb
Host smart-97fcf537-3f05-4320-8591-4427013bb49e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572226599 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.1572226599
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.984131300
Short name T52
Test name
Test status
Simulation time 328689362 ps
CPU time 16.94 seconds
Started Mar 07 02:52:01 PM PST 24
Finished Mar 07 02:52:18 PM PST 24
Peak memory 222684 kb
Host smart-758d5b82-253c-461a-b034-3c1c13d5fa1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984131300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.984131300
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1920173629
Short name T73
Test name
Test status
Simulation time 84778126408 ps
CPU time 883.98 seconds
Started Mar 07 02:50:27 PM PST 24
Finished Mar 07 03:05:11 PM PST 24
Peak memory 230340 kb
Host smart-7172a62d-5ea5-48b9-9d37-c4f5b0b98748
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920173629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1920173629
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1951976516
Short name T26
Test name
Test status
Simulation time 206250948 ps
CPU time 2.97 seconds
Started Mar 07 02:49:07 PM PST 24
Finished Mar 07 02:49:10 PM PST 24
Peak memory 214804 kb
Host smart-222240cf-f707-4a9d-bac6-4ad25a4c1f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951976516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1951976516
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.4142078244
Short name T152
Test name
Test status
Simulation time 4106648673 ps
CPU time 54.9 seconds
Started Mar 07 02:47:51 PM PST 24
Finished Mar 07 02:48:47 PM PST 24
Peak memory 216068 kb
Host smart-66484184-e008-4a04-94f0-567582ccf6db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4142078244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.4142078244
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3139583478
Short name T119
Test name
Test status
Simulation time 512623460 ps
CPU time 14.73 seconds
Started Mar 07 01:18:33 PM PST 24
Finished Mar 07 01:18:48 PM PST 24
Peak memory 214436 kb
Host smart-769510b0-d4fc-4876-b249-cb575aaa4233
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139583478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3139583478
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2953478541
Short name T8
Test name
Test status
Simulation time 2488773771 ps
CPU time 34.93 seconds
Started Mar 07 02:49:18 PM PST 24
Finished Mar 07 02:49:54 PM PST 24
Peak memory 214828 kb
Host smart-b0451479-a13c-451b-921e-68a48b9494d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953478541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2953478541
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1481051031
Short name T51
Test name
Test status
Simulation time 116250137 ps
CPU time 3.63 seconds
Started Mar 07 02:51:04 PM PST 24
Finished Mar 07 02:51:08 PM PST 24
Peak memory 214328 kb
Host smart-02ed1ddc-6eff-4cb6-8a51-400f96218baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481051031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1481051031
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2513720646
Short name T25
Test name
Test status
Simulation time 343420138 ps
CPU time 9.6 seconds
Started Mar 07 02:50:23 PM PST 24
Finished Mar 07 02:50:32 PM PST 24
Peak memory 214352 kb
Host smart-f1c1edb7-1af7-4858-9fe4-0aa12646d12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513720646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2513720646
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1517100517
Short name T280
Test name
Test status
Simulation time 938886251 ps
CPU time 48.45 seconds
Started Mar 07 02:52:51 PM PST 24
Finished Mar 07 02:53:39 PM PST 24
Peak memory 215680 kb
Host smart-319b2641-eeb5-40cd-be2c-fea31dc8d0ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1517100517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1517100517
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2283201535
Short name T70
Test name
Test status
Simulation time 980781527 ps
CPU time 36.71 seconds
Started Mar 07 02:48:17 PM PST 24
Finished Mar 07 02:48:54 PM PST 24
Peak memory 222468 kb
Host smart-316cc53d-f411-4a09-bd49-437c5ca6eb16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283201535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2283201535
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2840793221
Short name T24
Test name
Test status
Simulation time 537430515 ps
CPU time 6.54 seconds
Started Mar 07 02:49:12 PM PST 24
Finished Mar 07 02:49:19 PM PST 24
Peak memory 219672 kb
Host smart-935101ee-d1a4-44b6-9f97-a637c528f5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840793221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2840793221
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3984135082
Short name T153
Test name
Test status
Simulation time 308044659 ps
CPU time 8.91 seconds
Started Mar 07 02:51:01 PM PST 24
Finished Mar 07 02:51:10 PM PST 24
Peak memory 215644 kb
Host smart-f8dd379f-d323-43a3-83b4-e88cb8f0a77c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3984135082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3984135082
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.667815769
Short name T262
Test name
Test status
Simulation time 192652377 ps
CPU time 10.62 seconds
Started Mar 07 02:49:22 PM PST 24
Finished Mar 07 02:49:34 PM PST 24
Peak memory 214664 kb
Host smart-1f11a021-9954-41e6-ac5a-7d6baef85337
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=667815769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.667815769
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3659370677
Short name T18
Test name
Test status
Simulation time 342073099 ps
CPU time 4.47 seconds
Started Mar 07 02:48:01 PM PST 24
Finished Mar 07 02:48:06 PM PST 24
Peak memory 211016 kb
Host smart-a449815c-cb54-4113-b136-ff3bafcb4d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659370677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3659370677
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2707015141
Short name T58
Test name
Test status
Simulation time 1078821917 ps
CPU time 22.68 seconds
Started Mar 07 02:51:58 PM PST 24
Finished Mar 07 02:52:21 PM PST 24
Peak memory 222748 kb
Host smart-32aee33f-ff4e-4795-9585-9e85eaadebec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707015141 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2707015141
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1558096024
Short name T387
Test name
Test status
Simulation time 603312994 ps
CPU time 31.6 seconds
Started Mar 07 02:50:01 PM PST 24
Finished Mar 07 02:50:33 PM PST 24
Peak memory 214828 kb
Host smart-3911149b-e816-4aab-ba79-153117042ca6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1558096024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1558096024
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.950732063
Short name T43
Test name
Test status
Simulation time 2267243800 ps
CPU time 22.56 seconds
Started Mar 07 02:48:59 PM PST 24
Finished Mar 07 02:49:22 PM PST 24
Peak memory 221128 kb
Host smart-3cbe7eb4-b850-4890-ad1e-87dfefeec262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950732063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.950732063
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3777975951
Short name T40
Test name
Test status
Simulation time 199556564 ps
CPU time 4.76 seconds
Started Mar 07 02:49:05 PM PST 24
Finished Mar 07 02:49:10 PM PST 24
Peak memory 209616 kb
Host smart-9d7c7aa2-ad28-4003-87a2-2b622d989135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777975951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3777975951
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.820976059
Short name T425
Test name
Test status
Simulation time 1314213398 ps
CPU time 66.67 seconds
Started Mar 07 02:48:37 PM PST 24
Finished Mar 07 02:49:43 PM PST 24
Peak memory 214536 kb
Host smart-f668485a-d3cb-4567-9df8-d886778a3fdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=820976059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.820976059
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3561496405
Short name T77
Test name
Test status
Simulation time 27644715888 ps
CPU time 226.1 seconds
Started Mar 07 02:47:53 PM PST 24
Finished Mar 07 02:51:40 PM PST 24
Peak memory 222704 kb
Host smart-f3a43271-a77d-4ac5-8f9b-b02071e468d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561496405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3561496405
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.283917265
Short name T230
Test name
Test status
Simulation time 2403693073 ps
CPU time 20.79 seconds
Started Mar 07 02:48:04 PM PST 24
Finished Mar 07 02:48:25 PM PST 24
Peak memory 221352 kb
Host smart-42fa5468-6892-4fa0-9fa8-2c78812f6951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283917265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.283917265
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1032877312
Short name T227
Test name
Test status
Simulation time 5437432688 ps
CPU time 69.2 seconds
Started Mar 07 02:49:19 PM PST 24
Finished Mar 07 02:50:29 PM PST 24
Peak memory 216736 kb
Host smart-8acbd824-6ba5-42f7-8115-a1841df82424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032877312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1032877312
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2924299866
Short name T171
Test name
Test status
Simulation time 2292645089 ps
CPU time 23.13 seconds
Started Mar 07 02:47:59 PM PST 24
Finished Mar 07 02:48:22 PM PST 24
Peak memory 222812 kb
Host smart-e48c7902-60be-41e1-9767-68020cf67d41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924299866 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2924299866
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2876860712
Short name T21
Test name
Test status
Simulation time 162857618 ps
CPU time 2.56 seconds
Started Mar 07 02:48:13 PM PST 24
Finished Mar 07 02:48:16 PM PST 24
Peak memory 210064 kb
Host smart-acb11fa1-7754-45b4-b4ae-46f259aab27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876860712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2876860712
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.423239438
Short name T96
Test name
Test status
Simulation time 4032729556 ps
CPU time 31.9 seconds
Started Mar 07 02:49:09 PM PST 24
Finished Mar 07 02:49:41 PM PST 24
Peak memory 215176 kb
Host smart-48e82c5d-4df5-4ad8-9742-7fd6f2fd7f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423239438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.423239438
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1091456534
Short name T313
Test name
Test status
Simulation time 65665792 ps
CPU time 3.59 seconds
Started Mar 07 02:49:24 PM PST 24
Finished Mar 07 02:49:28 PM PST 24
Peak memory 214612 kb
Host smart-263cdfb8-512f-415d-8aa5-7b1564935bef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1091456534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1091456534
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.15428478
Short name T129
Test name
Test status
Simulation time 177893908 ps
CPU time 8.78 seconds
Started Mar 07 01:18:49 PM PST 24
Finished Mar 07 01:18:58 PM PST 24
Peak memory 220336 kb
Host smart-9f6943ec-8b57-4327-b75c-a44739781cca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15428478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.ke
ymgr_shadow_reg_errors_with_csr_rw.15428478
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.423632742
Short name T135
Test name
Test status
Simulation time 124946060 ps
CPU time 1.93 seconds
Started Mar 07 02:51:02 PM PST 24
Finished Mar 07 02:51:04 PM PST 24
Peak memory 207024 kb
Host smart-e219a48b-3e6b-432d-9e35-8afea05d841c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423632742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.423632742
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.843196869
Short name T162
Test name
Test status
Simulation time 2751743227 ps
CPU time 12.64 seconds
Started Mar 07 01:19:03 PM PST 24
Finished Mar 07 01:19:16 PM PST 24
Peak memory 209440 kb
Host smart-73f59f02-4c4f-4475-9e6c-43fb5055b098
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843196869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.843196869
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3189981146
Short name T158
Test name
Test status
Simulation time 67635081 ps
CPU time 4.36 seconds
Started Mar 07 02:49:42 PM PST 24
Finished Mar 07 02:49:46 PM PST 24
Peak memory 217916 kb
Host smart-f2ced462-2604-4a4b-a0ce-12962f65ef19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189981146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3189981146
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3353808499
Short name T53
Test name
Test status
Simulation time 193383407 ps
CPU time 3.26 seconds
Started Mar 07 02:50:06 PM PST 24
Finished Mar 07 02:50:09 PM PST 24
Peak memory 211428 kb
Host smart-4a4992f4-0417-417b-a8c4-022d7df24b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353808499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3353808499
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3819736792
Short name T220
Test name
Test status
Simulation time 710307734 ps
CPU time 37.05 seconds
Started Mar 07 02:50:17 PM PST 24
Finished Mar 07 02:50:54 PM PST 24
Peak memory 216680 kb
Host smart-31fc7140-5165-4a26-948e-9886fc0ebdf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819736792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3819736792
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1951889978
Short name T336
Test name
Test status
Simulation time 1057200103 ps
CPU time 14.94 seconds
Started Mar 07 02:48:17 PM PST 24
Finished Mar 07 02:48:32 PM PST 24
Peak memory 215672 kb
Host smart-0ac53534-f690-4192-ae6b-634bc7d64daf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951889978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1951889978
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3005024982
Short name T426
Test name
Test status
Simulation time 56372698 ps
CPU time 0.92 seconds
Started Mar 07 02:48:22 PM PST 24
Finished Mar 07 02:48:23 PM PST 24
Peak memory 206264 kb
Host smart-e789d2f3-f019-47d3-9b68-f5805e09b8eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005024982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3005024982
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3022086785
Short name T92
Test name
Test status
Simulation time 1169038308 ps
CPU time 24.08 seconds
Started Mar 07 02:48:18 PM PST 24
Finished Mar 07 02:48:42 PM PST 24
Peak memory 214488 kb
Host smart-5d7a7046-8328-471b-8370-b02242e12411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022086785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3022086785
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2219941134
Short name T165
Test name
Test status
Simulation time 826667163 ps
CPU time 9.46 seconds
Started Mar 07 01:19:07 PM PST 24
Finished Mar 07 01:19:17 PM PST 24
Peak memory 209192 kb
Host smart-9a3b3f33-b3c6-4d04-8120-7dac47fe14fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219941134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2219941134
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3066516560
Short name T361
Test name
Test status
Simulation time 407519158 ps
CPU time 22.75 seconds
Started Mar 07 02:50:48 PM PST 24
Finished Mar 07 02:51:11 PM PST 24
Peak memory 215100 kb
Host smart-239ea030-7eab-417d-9ce6-29b5f99d5471
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3066516560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3066516560
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2650236806
Short name T206
Test name
Test status
Simulation time 137783287 ps
CPU time 6.46 seconds
Started Mar 07 02:51:31 PM PST 24
Finished Mar 07 02:51:37 PM PST 24
Peak memory 210836 kb
Host smart-0d85b85c-3141-4482-bb93-1135c5a09735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650236806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2650236806
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.453099488
Short name T265
Test name
Test status
Simulation time 56168556 ps
CPU time 3.94 seconds
Started Mar 07 02:48:19 PM PST 24
Finished Mar 07 02:48:23 PM PST 24
Peak memory 215376 kb
Host smart-0fea5d66-2f9e-4efc-b929-f053ee8d3985
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=453099488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.453099488
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3942599056
Short name T278
Test name
Test status
Simulation time 2278087761 ps
CPU time 35.22 seconds
Started Mar 07 02:49:13 PM PST 24
Finished Mar 07 02:49:49 PM PST 24
Peak memory 216772 kb
Host smart-eccc356f-1807-437e-a77c-1e4a3fe10826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942599056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3942599056
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.4087351796
Short name T211
Test name
Test status
Simulation time 123002481 ps
CPU time 3.32 seconds
Started Mar 07 02:49:25 PM PST 24
Finished Mar 07 02:49:29 PM PST 24
Peak memory 222608 kb
Host smart-b8d0bc43-dcf6-4a3d-a90a-2adf643741f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087351796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.4087351796
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2525754836
Short name T1
Test name
Test status
Simulation time 114074988 ps
CPU time 1.87 seconds
Started Mar 07 02:49:18 PM PST 24
Finished Mar 07 02:49:20 PM PST 24
Peak memory 206904 kb
Host smart-b4e4cd18-f0fe-492e-85d1-e9028e6535a6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525754836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2525754836
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.3844536868
Short name T232
Test name
Test status
Simulation time 6532903252 ps
CPU time 125.75 seconds
Started Mar 07 02:50:03 PM PST 24
Finished Mar 07 02:52:08 PM PST 24
Peak memory 215740 kb
Host smart-728ed5a2-effb-4445-9298-6084cbe8adc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844536868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3844536868
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3103105525
Short name T154
Test name
Test status
Simulation time 41484731 ps
CPU time 3.26 seconds
Started Mar 07 02:49:29 PM PST 24
Finished Mar 07 02:49:32 PM PST 24
Peak memory 222848 kb
Host smart-df0d8b49-9a0a-4fc1-be27-1338cde06b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103105525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3103105525
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1074105074
Short name T422
Test name
Test status
Simulation time 184836814 ps
CPU time 9.99 seconds
Started Mar 07 02:48:47 PM PST 24
Finished Mar 07 02:48:57 PM PST 24
Peak memory 215348 kb
Host smart-ec7d4c71-0869-471b-bce9-7e9cc9d2ce5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1074105074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1074105074
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2876572853
Short name T307
Test name
Test status
Simulation time 104718402 ps
CPU time 5.93 seconds
Started Mar 07 02:48:59 PM PST 24
Finished Mar 07 02:49:06 PM PST 24
Peak memory 214372 kb
Host smart-edec25f8-eabe-4171-a82f-b2f9b5cb357f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2876572853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2876572853
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2234639598
Short name T103
Test name
Test status
Simulation time 111597198 ps
CPU time 3.64 seconds
Started Mar 07 02:49:31 PM PST 24
Finished Mar 07 02:49:36 PM PST 24
Peak memory 214452 kb
Host smart-942b4a03-4ab9-4f17-8841-6f4cd514380b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234639598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2234639598
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.560854428
Short name T76
Test name
Test status
Simulation time 6253131514 ps
CPU time 45.86 seconds
Started Mar 07 02:52:09 PM PST 24
Finished Mar 07 02:52:55 PM PST 24
Peak memory 217328 kb
Host smart-1dbfed0b-76ae-437f-a31c-00493264c9d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560854428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.560854428
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.432952648
Short name T957
Test name
Test status
Simulation time 858656505 ps
CPU time 2.27 seconds
Started Mar 07 01:18:38 PM PST 24
Finished Mar 07 01:18:41 PM PST 24
Peak memory 214460 kb
Host smart-5e32f8c8-d950-4f2b-a8c3-a47df0ee3fee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432952648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.432952648
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1340948250
Short name T172
Test name
Test status
Simulation time 818889080 ps
CPU time 9.29 seconds
Started Mar 07 01:19:16 PM PST 24
Finished Mar 07 01:19:26 PM PST 24
Peak memory 209712 kb
Host smart-fc1c2b9d-0180-46cc-aa4a-46e4a2c6416b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340948250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1340948250
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.796858062
Short name T99
Test name
Test status
Simulation time 287704275 ps
CPU time 6.59 seconds
Started Mar 07 02:48:05 PM PST 24
Finished Mar 07 02:48:12 PM PST 24
Peak memory 209504 kb
Host smart-349b107d-14e4-4825-ab29-c8d4239122df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796858062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.796858062
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2333853830
Short name T156
Test name
Test status
Simulation time 195084088 ps
CPU time 3 seconds
Started Mar 07 02:51:59 PM PST 24
Finished Mar 07 02:52:02 PM PST 24
Peak memory 217796 kb
Host smart-36d2375a-b47d-4f6e-a621-d853fc7d7114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333853830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2333853830
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.517695468
Short name T159
Test name
Test status
Simulation time 216015236 ps
CPU time 4.78 seconds
Started Mar 07 02:48:59 PM PST 24
Finished Mar 07 02:49:04 PM PST 24
Peak memory 223052 kb
Host smart-52d95599-7c71-452e-bf8c-1f6dacc6ae35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517695468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.517695468
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1423785915
Short name T157
Test name
Test status
Simulation time 86973033 ps
CPU time 4.13 seconds
Started Mar 07 02:49:47 PM PST 24
Finished Mar 07 02:49:51 PM PST 24
Peak memory 222948 kb
Host smart-5b2454ad-14ff-4b23-89f0-79847fd6f5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423785915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1423785915
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2436616518
Short name T373
Test name
Test status
Simulation time 87895485 ps
CPU time 4.62 seconds
Started Mar 07 02:48:25 PM PST 24
Finished Mar 07 02:48:31 PM PST 24
Peak memory 214468 kb
Host smart-9bf88326-2fae-421b-9e7e-64a55faa5601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436616518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2436616518
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2466041845
Short name T382
Test name
Test status
Simulation time 83396080 ps
CPU time 1.95 seconds
Started Mar 07 02:48:39 PM PST 24
Finished Mar 07 02:48:41 PM PST 24
Peak memory 209752 kb
Host smart-390a43bd-69a6-4117-ae63-7bd7151734e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466041845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2466041845
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2231652907
Short name T250
Test name
Test status
Simulation time 54115062 ps
CPU time 3.83 seconds
Started Mar 07 02:48:49 PM PST 24
Finished Mar 07 02:48:53 PM PST 24
Peak memory 209184 kb
Host smart-e78233b2-d9b5-453e-8b2d-be1412db9032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231652907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2231652907
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1406601243
Short name T385
Test name
Test status
Simulation time 73286736 ps
CPU time 4.7 seconds
Started Mar 07 02:49:20 PM PST 24
Finished Mar 07 02:49:25 PM PST 24
Peak memory 215568 kb
Host smart-6147e1d7-20ba-42cf-a881-d7fb54951840
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1406601243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1406601243
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3495685561
Short name T67
Test name
Test status
Simulation time 403551249 ps
CPU time 3.73 seconds
Started Mar 07 02:50:37 PM PST 24
Finished Mar 07 02:50:41 PM PST 24
Peak memory 210056 kb
Host smart-2111360a-f5e8-4348-b5ff-9324febd33b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495685561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3495685561
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2983374437
Short name T60
Test name
Test status
Simulation time 4752309265 ps
CPU time 43.89 seconds
Started Mar 07 02:48:19 PM PST 24
Finished Mar 07 02:49:03 PM PST 24
Peak memory 215840 kb
Host smart-10ee7852-8932-435a-9492-f3f5112b837f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983374437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2983374437
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1872883271
Short name T184
Test name
Test status
Simulation time 1225498495 ps
CPU time 10.93 seconds
Started Mar 07 01:19:11 PM PST 24
Finished Mar 07 01:19:22 PM PST 24
Peak memory 209540 kb
Host smart-93e116b5-e299-4f6c-839d-cc9be5632bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872883271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1872883271
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.4090797163
Short name T180
Test name
Test status
Simulation time 104239091 ps
CPU time 2.79 seconds
Started Mar 07 02:49:15 PM PST 24
Finished Mar 07 02:49:18 PM PST 24
Peak memory 210312 kb
Host smart-0a06fcb7-9534-4c66-83d6-24e325e52a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090797163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.4090797163
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1361828322
Short name T155
Test name
Test status
Simulation time 1238285958 ps
CPU time 9.28 seconds
Started Mar 07 02:50:12 PM PST 24
Finished Mar 07 02:50:21 PM PST 24
Peak memory 216756 kb
Host smart-c77895ad-d9a4-47c5-8b4a-2fcf4f369e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361828322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1361828322
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2112966498
Short name T416
Test name
Test status
Simulation time 271213674 ps
CPU time 14.06 seconds
Started Mar 07 02:48:24 PM PST 24
Finished Mar 07 02:48:39 PM PST 24
Peak memory 215536 kb
Host smart-81ce29a5-b305-4c92-a557-0b589958c74d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112966498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2112966498
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2743240112
Short name T240
Test name
Test status
Simulation time 34257332 ps
CPU time 2.89 seconds
Started Mar 07 02:48:34 PM PST 24
Finished Mar 07 02:48:37 PM PST 24
Peak memory 214596 kb
Host smart-2c74671c-44a6-4ba4-b162-982c159d82f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2743240112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2743240112
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3832432877
Short name T85
Test name
Test status
Simulation time 55700595 ps
CPU time 2.91 seconds
Started Mar 07 02:48:33 PM PST 24
Finished Mar 07 02:48:36 PM PST 24
Peak memory 208620 kb
Host smart-3eebe0c8-368d-4b97-a7e5-3f18857fdd67
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832432877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3832432877
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1376769648
Short name T2
Test name
Test status
Simulation time 95477772 ps
CPU time 4.44 seconds
Started Mar 07 02:48:47 PM PST 24
Finished Mar 07 02:48:52 PM PST 24
Peak memory 214476 kb
Host smart-e4d579c4-289d-409a-9731-e39f0a44c319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376769648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1376769648
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2095682301
Short name T287
Test name
Test status
Simulation time 1162453462 ps
CPU time 21.39 seconds
Started Mar 07 02:48:53 PM PST 24
Finished Mar 07 02:49:15 PM PST 24
Peak memory 208660 kb
Host smart-86f315a7-94ba-41c0-ab89-cc09f78f3276
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095682301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2095682301
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2718105993
Short name T789
Test name
Test status
Simulation time 81727140 ps
CPU time 4.4 seconds
Started Mar 07 02:50:36 PM PST 24
Finished Mar 07 02:50:40 PM PST 24
Peak memory 214476 kb
Host smart-572b3860-94f4-41d8-b3cd-2f2bc9c97bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718105993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2718105993
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.25914618
Short name T268
Test name
Test status
Simulation time 191718081 ps
CPU time 6.91 seconds
Started Mar 07 02:52:36 PM PST 24
Finished Mar 07 02:52:44 PM PST 24
Peak memory 209636 kb
Host smart-004cac46-e395-4a6d-b693-66793c8ecb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25914618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.25914618
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2005356798
Short name T163
Test name
Test status
Simulation time 1178478260 ps
CPU time 9.17 seconds
Started Mar 07 01:18:49 PM PST 24
Finished Mar 07 01:18:59 PM PST 24
Peak memory 209244 kb
Host smart-56328764-71ec-41db-83d2-536c3b760197
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005356798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2005356798
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1332673501
Short name T173
Test name
Test status
Simulation time 503812055 ps
CPU time 10.1 seconds
Started Mar 07 01:19:06 PM PST 24
Finished Mar 07 01:19:16 PM PST 24
Peak memory 209156 kb
Host smart-c02ec73b-349a-47aa-b171-8a6b15a66183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332673501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1332673501
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3578372002
Short name T160
Test name
Test status
Simulation time 316446072 ps
CPU time 9.92 seconds
Started Mar 07 02:47:52 PM PST 24
Finished Mar 07 02:48:03 PM PST 24
Peak memory 215956 kb
Host smart-88722cbc-595a-4cd1-88b0-68c0686ede33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578372002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3578372002
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.366932271
Short name T161
Test name
Test status
Simulation time 145974085 ps
CPU time 6.28 seconds
Started Mar 07 02:48:04 PM PST 24
Finished Mar 07 02:48:11 PM PST 24
Peak memory 218168 kb
Host smart-4329b415-f2b7-471b-aaae-de90f86b3c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366932271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.366932271
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2376293896
Short name T805
Test name
Test status
Simulation time 59831270 ps
CPU time 3.71 seconds
Started Mar 07 02:47:52 PM PST 24
Finished Mar 07 02:47:56 PM PST 24
Peak memory 214512 kb
Host smart-11d4aa33-5bba-4632-b995-6c83db8d9e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376293896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2376293896
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2044789968
Short name T341
Test name
Test status
Simulation time 1429687160 ps
CPU time 58.76 seconds
Started Mar 07 02:48:25 PM PST 24
Finished Mar 07 02:49:25 PM PST 24
Peak memory 221004 kb
Host smart-d22363cd-2f9e-412f-adb8-05bbb8937c46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044789968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2044789968
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3912150669
Short name T379
Test name
Test status
Simulation time 61960662 ps
CPU time 3.92 seconds
Started Mar 07 02:48:26 PM PST 24
Finished Mar 07 02:48:31 PM PST 24
Peak memory 209156 kb
Host smart-65860202-b5f6-4b52-9027-2a98ef1f3a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912150669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3912150669
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3453019009
Short name T223
Test name
Test status
Simulation time 76232217 ps
CPU time 3.84 seconds
Started Mar 07 02:48:40 PM PST 24
Finished Mar 07 02:48:44 PM PST 24
Peak memory 209936 kb
Host smart-d109054d-9977-4e8d-9812-a2cfe2e46651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453019009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3453019009
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.2792555219
Short name T168
Test name
Test status
Simulation time 456738054 ps
CPU time 19.35 seconds
Started Mar 07 02:48:31 PM PST 24
Finished Mar 07 02:48:50 PM PST 24
Peak memory 222836 kb
Host smart-b5b2e7e9-7555-409a-b199-05c03068190c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792555219 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.2792555219
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2831805812
Short name T7
Test name
Test status
Simulation time 1092251541 ps
CPU time 6.79 seconds
Started Mar 07 02:48:37 PM PST 24
Finished Mar 07 02:48:44 PM PST 24
Peak memory 210128 kb
Host smart-896f1007-3633-43b2-b27a-7abf3acfe211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831805812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2831805812
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.2599211371
Short name T166
Test name
Test status
Simulation time 849092502 ps
CPU time 14.71 seconds
Started Mar 07 02:48:44 PM PST 24
Finished Mar 07 02:48:59 PM PST 24
Peak memory 221064 kb
Host smart-a22b5a9c-4ac2-47cd-a521-25eea3c0f7de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599211371 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.2599211371
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.983679264
Short name T237
Test name
Test status
Simulation time 181143149 ps
CPU time 3.25 seconds
Started Mar 07 02:48:46 PM PST 24
Finished Mar 07 02:48:50 PM PST 24
Peak memory 210108 kb
Host smart-299c1daa-b92b-42ef-81e1-130c7776fd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983679264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.983679264
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2667553645
Short name T284
Test name
Test status
Simulation time 524689183 ps
CPU time 14.62 seconds
Started Mar 07 02:48:44 PM PST 24
Finished Mar 07 02:48:59 PM PST 24
Peak memory 214508 kb
Host smart-4b1ada29-95bd-41a1-bc2c-ef7717db9133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667553645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2667553645
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_sideload.553629373
Short name T347
Test name
Test status
Simulation time 617237726 ps
CPU time 8.91 seconds
Started Mar 07 02:48:49 PM PST 24
Finished Mar 07 02:48:59 PM PST 24
Peak memory 208596 kb
Host smart-8e570b33-fbe8-47ef-9f0c-d01b8565adb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553629373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.553629373
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.367489173
Short name T271
Test name
Test status
Simulation time 925475221 ps
CPU time 5.14 seconds
Started Mar 07 02:48:55 PM PST 24
Finished Mar 07 02:49:00 PM PST 24
Peak memory 214520 kb
Host smart-c1dc21a6-a4ee-4280-adb3-ceda224ebde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367489173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.367489173
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2312740089
Short name T327
Test name
Test status
Simulation time 772354644 ps
CPU time 5.98 seconds
Started Mar 07 02:48:00 PM PST 24
Finished Mar 07 02:48:06 PM PST 24
Peak memory 209052 kb
Host smart-c4a9ccd1-4617-4de7-88f0-44a66f8dfa29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312740089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2312740089
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2470846054
Short name T443
Test name
Test status
Simulation time 417190981 ps
CPU time 11.6 seconds
Started Mar 07 02:47:56 PM PST 24
Finished Mar 07 02:48:09 PM PST 24
Peak memory 208532 kb
Host smart-23f0994b-be3b-4924-99e5-339089d1f950
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470846054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2470846054
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.372002744
Short name T238
Test name
Test status
Simulation time 561383562 ps
CPU time 10.99 seconds
Started Mar 07 02:49:18 PM PST 24
Finished Mar 07 02:49:29 PM PST 24
Peak memory 222644 kb
Host smart-05f9e4ec-e02d-44ef-ae7f-3783a59e7a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372002744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.372002744
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3401189851
Short name T323
Test name
Test status
Simulation time 129102252 ps
CPU time 4.44 seconds
Started Mar 07 02:50:22 PM PST 24
Finished Mar 07 02:50:26 PM PST 24
Peak memory 218560 kb
Host smart-b8d0d0e3-334c-43ac-bb28-f62017e8ddeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401189851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3401189851
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.40749500
Short name T123
Test name
Test status
Simulation time 81211010 ps
CPU time 4.77 seconds
Started Mar 07 02:50:24 PM PST 24
Finished Mar 07 02:50:29 PM PST 24
Peak memory 222680 kb
Host smart-6e58d0f4-337c-4ebf-bad2-6f6ca5baed32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=40749500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.40749500
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3801062234
Short name T371
Test name
Test status
Simulation time 193865738 ps
CPU time 2.73 seconds
Started Mar 07 02:50:35 PM PST 24
Finished Mar 07 02:50:38 PM PST 24
Peak memory 208180 kb
Host smart-f5b6c509-6a2e-448a-a08a-80132f8f7c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801062234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3801062234
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1604075654
Short name T283
Test name
Test status
Simulation time 235347593 ps
CPU time 5.36 seconds
Started Mar 07 02:51:48 PM PST 24
Finished Mar 07 02:51:53 PM PST 24
Peak memory 222660 kb
Host smart-ff95e2fa-ed1f-4a24-ba90-d33374d4b808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604075654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1604075654
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3934547281
Short name T205
Test name
Test status
Simulation time 218928885 ps
CPU time 5.29 seconds
Started Mar 07 02:48:00 PM PST 24
Finished Mar 07 02:48:05 PM PST 24
Peak memory 208340 kb
Host smart-eefb81f3-4c9c-490a-8f2f-c31766cb94a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934547281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3934547281
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.945578208
Short name T71
Test name
Test status
Simulation time 121972197 ps
CPU time 2.73 seconds
Started Mar 07 02:48:27 PM PST 24
Finished Mar 07 02:48:29 PM PST 24
Peak memory 214756 kb
Host smart-69d2dbd3-09f6-4856-a049-e3e44fa7d061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945578208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.945578208
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1805698271
Short name T973
Test name
Test status
Simulation time 923510749 ps
CPU time 9.46 seconds
Started Mar 07 01:18:39 PM PST 24
Finished Mar 07 01:18:49 PM PST 24
Peak memory 206036 kb
Host smart-c43765b7-6280-4153-8982-843598b49fe2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805698271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
805698271
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3880642532
Short name T1063
Test name
Test status
Simulation time 267966091 ps
CPU time 7.57 seconds
Started Mar 07 01:18:39 PM PST 24
Finished Mar 07 01:18:47 PM PST 24
Peak memory 205968 kb
Host smart-de70efc6-e7cd-4cdf-8773-983fb4c1dc17
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880642532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
880642532
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2769791846
Short name T914
Test name
Test status
Simulation time 132602765 ps
CPU time 1.52 seconds
Started Mar 07 01:18:35 PM PST 24
Finished Mar 07 01:18:37 PM PST 24
Peak memory 205968 kb
Host smart-1b1f0bd2-17e0-48d0-b8de-68a2b669de05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769791846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
769791846
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3134849746
Short name T1040
Test name
Test status
Simulation time 199933490 ps
CPU time 2.43 seconds
Started Mar 07 01:18:39 PM PST 24
Finished Mar 07 01:18:42 PM PST 24
Peak memory 218684 kb
Host smart-f347eb30-3e5a-4443-8f9a-229bc0ef315d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134849746 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3134849746
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.318853364
Short name T936
Test name
Test status
Simulation time 80385220 ps
CPU time 1.13 seconds
Started Mar 07 01:18:39 PM PST 24
Finished Mar 07 01:18:41 PM PST 24
Peak memory 206044 kb
Host smart-6f89eb64-fb55-4286-b528-74928a87ff32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318853364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.318853364
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1958062426
Short name T965
Test name
Test status
Simulation time 48231336 ps
CPU time 0.76 seconds
Started Mar 07 01:18:39 PM PST 24
Finished Mar 07 01:18:40 PM PST 24
Peak memory 205672 kb
Host smart-b4cd1399-6a50-4a1b-a07c-3b1414eab680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958062426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1958062426
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1421221366
Short name T939
Test name
Test status
Simulation time 185072617 ps
CPU time 1.82 seconds
Started Mar 07 01:18:39 PM PST 24
Finished Mar 07 01:18:42 PM PST 24
Peak memory 206032 kb
Host smart-3be62bab-0215-4ca9-8ed9-64e59794c8f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421221366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1421221366
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3172428829
Short name T903
Test name
Test status
Simulation time 441191459 ps
CPU time 2.9 seconds
Started Mar 07 01:18:36 PM PST 24
Finished Mar 07 01:18:39 PM PST 24
Peak memory 214200 kb
Host smart-0ad5c2fa-9d8e-48c6-95f1-31c8e9fae1b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172428829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3172428829
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.742734815
Short name T187
Test name
Test status
Simulation time 390076523 ps
CPU time 6.47 seconds
Started Mar 07 01:18:30 PM PST 24
Finished Mar 07 01:18:37 PM PST 24
Peak memory 209380 kb
Host smart-04d3ef92-0754-41a8-9eba-15a429d20138
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742734815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
742734815
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2446411849
Short name T1045
Test name
Test status
Simulation time 497871708 ps
CPU time 5.41 seconds
Started Mar 07 01:18:48 PM PST 24
Finished Mar 07 01:18:53 PM PST 24
Peak memory 206040 kb
Host smart-2bbed426-308a-4231-866c-fd953eaf0f8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446411849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
446411849
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2144495911
Short name T980
Test name
Test status
Simulation time 139045560 ps
CPU time 6.15 seconds
Started Mar 07 01:18:47 PM PST 24
Finished Mar 07 01:18:53 PM PST 24
Peak memory 206028 kb
Host smart-f47ca788-321e-4cdd-b67a-f683790ede09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144495911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
144495911
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1519549736
Short name T1050
Test name
Test status
Simulation time 129044241 ps
CPU time 1.27 seconds
Started Mar 07 01:18:53 PM PST 24
Finished Mar 07 01:18:56 PM PST 24
Peak memory 206068 kb
Host smart-8cc1724b-9609-4fce-a357-8c93f110efd9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519549736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
519549736
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1843317853
Short name T900
Test name
Test status
Simulation time 70304745 ps
CPU time 1.71 seconds
Started Mar 07 01:18:50 PM PST 24
Finished Mar 07 01:18:52 PM PST 24
Peak memory 214220 kb
Host smart-181c2f55-8d2e-4eaf-bd91-e178fa85714a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843317853 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1843317853
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.623758617
Short name T1056
Test name
Test status
Simulation time 12878869 ps
CPU time 1.2 seconds
Started Mar 07 01:18:55 PM PST 24
Finished Mar 07 01:18:57 PM PST 24
Peak memory 206108 kb
Host smart-efa7abc2-e7ee-48be-881c-65646a81f883
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623758617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.623758617
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3251756234
Short name T1054
Test name
Test status
Simulation time 17056306 ps
CPU time 0.7 seconds
Started Mar 07 01:18:48 PM PST 24
Finished Mar 07 01:18:49 PM PST 24
Peak memory 205752 kb
Host smart-36c9b70e-7d61-4b6c-a89c-7c7552b4a0f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251756234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3251756234
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.121619114
Short name T1066
Test name
Test status
Simulation time 365981483 ps
CPU time 3.95 seconds
Started Mar 07 01:18:53 PM PST 24
Finished Mar 07 01:18:59 PM PST 24
Peak memory 206036 kb
Host smart-20fda009-6254-4cfc-8a1f-06fff2dc151f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121619114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.121619114
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3088683019
Short name T947
Test name
Test status
Simulation time 531266696 ps
CPU time 2.29 seconds
Started Mar 07 01:18:51 PM PST 24
Finished Mar 07 01:18:53 PM PST 24
Peak memory 214468 kb
Host smart-a9b16eb9-ea92-4072-abd4-d34285e365eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088683019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3088683019
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1778677499
Short name T1037
Test name
Test status
Simulation time 191074738 ps
CPU time 8.17 seconds
Started Mar 07 01:18:51 PM PST 24
Finished Mar 07 01:18:59 PM PST 24
Peak memory 214524 kb
Host smart-74c2aade-cef0-42a2-b901-8caf6644efa1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778677499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1778677499
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4031832826
Short name T1061
Test name
Test status
Simulation time 473313397 ps
CPU time 4.32 seconds
Started Mar 07 01:18:49 PM PST 24
Finished Mar 07 01:18:54 PM PST 24
Peak memory 214244 kb
Host smart-e429d997-5a3f-4475-b911-94565a2c7e8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031832826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.4031832826
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.826030010
Short name T1038
Test name
Test status
Simulation time 98057266 ps
CPU time 1.61 seconds
Started Mar 07 01:19:08 PM PST 24
Finished Mar 07 01:19:09 PM PST 24
Peak memory 214236 kb
Host smart-a4c2df52-5988-4590-8789-13a2802fae9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826030010 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.826030010
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3799112675
Short name T145
Test name
Test status
Simulation time 62070463 ps
CPU time 1.24 seconds
Started Mar 07 01:19:11 PM PST 24
Finished Mar 07 01:19:13 PM PST 24
Peak memory 206116 kb
Host smart-505a8f87-2555-4a8b-8124-b1a0e670efb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799112675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3799112675
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3965280875
Short name T1068
Test name
Test status
Simulation time 18590889 ps
CPU time 0.74 seconds
Started Mar 07 01:19:07 PM PST 24
Finished Mar 07 01:19:08 PM PST 24
Peak memory 205732 kb
Host smart-ed5ee50e-e998-466b-86a4-d8d90e11d124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965280875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3965280875
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3010965054
Short name T902
Test name
Test status
Simulation time 39539542 ps
CPU time 1.95 seconds
Started Mar 07 01:19:06 PM PST 24
Finished Mar 07 01:19:09 PM PST 24
Peak memory 205964 kb
Host smart-d1e0fe6c-cc56-4d7f-86af-96bac7372a5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010965054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3010965054
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4109644385
Short name T963
Test name
Test status
Simulation time 175310057 ps
CPU time 3.02 seconds
Started Mar 07 01:19:06 PM PST 24
Finished Mar 07 01:19:09 PM PST 24
Peak memory 214612 kb
Host smart-ef560266-bb15-4953-9e10-26676d815f00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109644385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.4109644385
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.758233163
Short name T124
Test name
Test status
Simulation time 402786324 ps
CPU time 5.14 seconds
Started Mar 07 01:19:11 PM PST 24
Finished Mar 07 01:19:17 PM PST 24
Peak memory 214464 kb
Host smart-44bff744-fb3e-42de-ba54-650c8b6ae0c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758233163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.758233163
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1380792394
Short name T918
Test name
Test status
Simulation time 28918789 ps
CPU time 2.09 seconds
Started Mar 07 01:19:10 PM PST 24
Finished Mar 07 01:19:12 PM PST 24
Peak memory 214236 kb
Host smart-8a51d8ec-4550-4ad9-b4f7-827d8df536a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380792394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1380792394
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.4158263068
Short name T956
Test name
Test status
Simulation time 140079812 ps
CPU time 1.59 seconds
Started Mar 07 01:19:11 PM PST 24
Finished Mar 07 01:19:13 PM PST 24
Peak memory 206092 kb
Host smart-067d3ff1-41c6-4d60-8906-6a2f6df0b3bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158263068 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.4158263068
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2200879246
Short name T148
Test name
Test status
Simulation time 61263477 ps
CPU time 0.95 seconds
Started Mar 07 01:19:08 PM PST 24
Finished Mar 07 01:19:09 PM PST 24
Peak memory 205900 kb
Host smart-faa210fa-2c17-4477-8cf9-a4b9578255aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200879246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2200879246
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3489818138
Short name T1006
Test name
Test status
Simulation time 44876238 ps
CPU time 0.93 seconds
Started Mar 07 01:19:06 PM PST 24
Finished Mar 07 01:19:08 PM PST 24
Peak memory 205732 kb
Host smart-8bd7d23c-fe2b-4ae7-a430-72ceb105f415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489818138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3489818138
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3873114881
Short name T1034
Test name
Test status
Simulation time 112919219 ps
CPU time 1.63 seconds
Started Mar 07 01:19:02 PM PST 24
Finished Mar 07 01:19:04 PM PST 24
Peak memory 206076 kb
Host smart-5311979c-3c08-4767-8fbb-946a79e49ed7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873114881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3873114881
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1569136015
Short name T1005
Test name
Test status
Simulation time 223543022 ps
CPU time 2.77 seconds
Started Mar 07 01:19:09 PM PST 24
Finished Mar 07 01:19:12 PM PST 24
Peak memory 222764 kb
Host smart-642a5038-9215-4835-a38a-2eef43981862
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569136015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1569136015
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2131863466
Short name T118
Test name
Test status
Simulation time 799257715 ps
CPU time 4.99 seconds
Started Mar 07 01:19:05 PM PST 24
Finished Mar 07 01:19:10 PM PST 24
Peak memory 214504 kb
Host smart-55d50f57-ae66-48f0-92dd-f305c6fae2e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131863466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2131863466
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3959048196
Short name T908
Test name
Test status
Simulation time 56695769 ps
CPU time 2.11 seconds
Started Mar 07 01:19:06 PM PST 24
Finished Mar 07 01:19:08 PM PST 24
Peak memory 214144 kb
Host smart-d0551055-47b2-4267-893a-65ec5518b31d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959048196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3959048196
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1723234307
Short name T178
Test name
Test status
Simulation time 3633704483 ps
CPU time 21.97 seconds
Started Mar 07 01:19:07 PM PST 24
Finished Mar 07 01:19:29 PM PST 24
Peak memory 209508 kb
Host smart-7ac9492c-f57a-4c21-805f-db6f5d605fd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723234307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1723234307
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2545741122
Short name T988
Test name
Test status
Simulation time 150143034 ps
CPU time 1.21 seconds
Started Mar 07 01:19:11 PM PST 24
Finished Mar 07 01:19:13 PM PST 24
Peak memory 206048 kb
Host smart-8b39ca47-5a23-4182-b482-4957410202f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545741122 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2545741122
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1468451200
Short name T912
Test name
Test status
Simulation time 116367147 ps
CPU time 1.2 seconds
Started Mar 07 01:19:07 PM PST 24
Finished Mar 07 01:19:08 PM PST 24
Peak memory 206032 kb
Host smart-a6d8b7c7-750d-4b28-abb6-e7ba0c1c4548
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468451200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1468451200
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3121336377
Short name T1044
Test name
Test status
Simulation time 44874820 ps
CPU time 0.72 seconds
Started Mar 07 01:19:10 PM PST 24
Finished Mar 07 01:19:11 PM PST 24
Peak memory 205700 kb
Host smart-e29e92d4-0a60-4f16-8928-9083bbbdd1db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121336377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3121336377
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1964321688
Short name T1060
Test name
Test status
Simulation time 93439500 ps
CPU time 1.71 seconds
Started Mar 07 01:19:08 PM PST 24
Finished Mar 07 01:19:09 PM PST 24
Peak memory 206036 kb
Host smart-0bc72814-4c46-4883-bf94-27926d3fcc70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964321688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1964321688
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2978459051
Short name T970
Test name
Test status
Simulation time 2566032939 ps
CPU time 6.65 seconds
Started Mar 07 01:19:06 PM PST 24
Finished Mar 07 01:19:13 PM PST 24
Peak memory 214560 kb
Host smart-2518355e-52a0-4256-ba98-f2763f9fbecb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978459051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2978459051
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2909761672
Short name T126
Test name
Test status
Simulation time 751305531 ps
CPU time 7.42 seconds
Started Mar 07 01:19:06 PM PST 24
Finished Mar 07 01:19:13 PM PST 24
Peak memory 214540 kb
Host smart-f971f577-6381-4d76-8096-16e22ecb1afe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909761672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2909761672
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.4053805693
Short name T1053
Test name
Test status
Simulation time 157313244 ps
CPU time 3.76 seconds
Started Mar 07 01:19:05 PM PST 24
Finished Mar 07 01:19:09 PM PST 24
Peak memory 214196 kb
Host smart-81bfb835-94da-471a-b61b-31b515484f0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053805693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.4053805693
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.838366633
Short name T933
Test name
Test status
Simulation time 30819215 ps
CPU time 1.26 seconds
Started Mar 07 01:19:11 PM PST 24
Finished Mar 07 01:19:13 PM PST 24
Peak memory 205912 kb
Host smart-fea89ee3-d436-4659-a60d-33384e2e0761
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838366633 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.838366633
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.4012464530
Short name T907
Test name
Test status
Simulation time 72385836 ps
CPU time 1.19 seconds
Started Mar 07 01:19:08 PM PST 24
Finished Mar 07 01:19:10 PM PST 24
Peak memory 206016 kb
Host smart-31a9d150-6f66-43d5-8675-0f21cbe1951c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012464530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.4012464530
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1419397575
Short name T910
Test name
Test status
Simulation time 95284850 ps
CPU time 0.71 seconds
Started Mar 07 01:19:10 PM PST 24
Finished Mar 07 01:19:11 PM PST 24
Peak memory 205728 kb
Host smart-092540dd-a157-4e22-b9df-b0a350ef43ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419397575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1419397575
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2925481030
Short name T953
Test name
Test status
Simulation time 107394296 ps
CPU time 3.82 seconds
Started Mar 07 01:19:10 PM PST 24
Finished Mar 07 01:19:14 PM PST 24
Peak memory 206108 kb
Host smart-41bd747b-031d-4acd-958c-ce129d9ccd79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925481030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2925481030
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.179638592
Short name T946
Test name
Test status
Simulation time 340418324 ps
CPU time 11.65 seconds
Started Mar 07 01:19:08 PM PST 24
Finished Mar 07 01:19:19 PM PST 24
Peak memory 214460 kb
Host smart-bfbaebd0-3587-41b0-b608-486a60f3eab7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179638592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.179638592
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.512742490
Short name T972
Test name
Test status
Simulation time 377156085 ps
CPU time 7.04 seconds
Started Mar 07 01:19:06 PM PST 24
Finished Mar 07 01:19:13 PM PST 24
Peak memory 214552 kb
Host smart-400904ec-4040-4805-9f61-7e886b303e04
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512742490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_shadow_reg_errors_with_csr_rw.512742490
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.968643062
Short name T960
Test name
Test status
Simulation time 105101216 ps
CPU time 4.07 seconds
Started Mar 07 01:19:10 PM PST 24
Finished Mar 07 01:19:14 PM PST 24
Peak memory 216208 kb
Host smart-418ee811-9ce3-4bfd-8b26-1f71f9399b9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968643062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.968643062
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3685268127
Short name T179
Test name
Test status
Simulation time 535977098 ps
CPU time 4.99 seconds
Started Mar 07 01:19:09 PM PST 24
Finished Mar 07 01:19:14 PM PST 24
Peak memory 209548 kb
Host smart-385a8599-6b01-474b-b7ff-48ac3b1863d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685268127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3685268127
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2064890526
Short name T1042
Test name
Test status
Simulation time 33301485 ps
CPU time 1.48 seconds
Started Mar 07 01:19:16 PM PST 24
Finished Mar 07 01:19:18 PM PST 24
Peak memory 214192 kb
Host smart-b4f9a5df-48b2-4eec-aa9f-f332aa431842
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064890526 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2064890526
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2126129497
Short name T928
Test name
Test status
Simulation time 33541921 ps
CPU time 1.15 seconds
Started Mar 07 01:19:09 PM PST 24
Finished Mar 07 01:19:11 PM PST 24
Peak memory 206004 kb
Host smart-1a98c46f-671a-4e85-9319-404c2e95a609
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126129497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2126129497
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1628182602
Short name T977
Test name
Test status
Simulation time 19023690 ps
CPU time 1.01 seconds
Started Mar 07 01:19:07 PM PST 24
Finished Mar 07 01:19:08 PM PST 24
Peak memory 205740 kb
Host smart-aca01790-6f64-4a53-9cf6-2277ad221e9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628182602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1628182602
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.4002686194
Short name T990
Test name
Test status
Simulation time 225426298 ps
CPU time 1.65 seconds
Started Mar 07 01:19:16 PM PST 24
Finished Mar 07 01:19:18 PM PST 24
Peak memory 206004 kb
Host smart-c9cdae01-c16f-4775-ad31-a2ef785388df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002686194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.4002686194
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.4117805063
Short name T945
Test name
Test status
Simulation time 321171601 ps
CPU time 7.12 seconds
Started Mar 07 01:19:11 PM PST 24
Finished Mar 07 01:19:18 PM PST 24
Peak memory 214328 kb
Host smart-f9eec3da-fed2-4629-9ec7-4d3983c55cd1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117805063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.4117805063
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.4107433071
Short name T985
Test name
Test status
Simulation time 595467162 ps
CPU time 10.75 seconds
Started Mar 07 01:19:10 PM PST 24
Finished Mar 07 01:19:21 PM PST 24
Peak memory 214592 kb
Host smart-65763d6b-aec2-431b-a47b-e48eb367e516
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107433071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.4107433071
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2965720640
Short name T997
Test name
Test status
Simulation time 30384868 ps
CPU time 2.33 seconds
Started Mar 07 01:19:07 PM PST 24
Finished Mar 07 01:19:09 PM PST 24
Peak memory 214120 kb
Host smart-f05b5dac-369a-4fd8-a645-66d2c3d89695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965720640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2965720640
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3599315313
Short name T1020
Test name
Test status
Simulation time 51015662 ps
CPU time 2.54 seconds
Started Mar 07 01:19:11 PM PST 24
Finished Mar 07 01:19:14 PM PST 24
Peak memory 214428 kb
Host smart-073727f2-c96f-49e8-a340-2eeee1d82d57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599315313 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3599315313
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.458469658
Short name T958
Test name
Test status
Simulation time 26505142 ps
CPU time 1.48 seconds
Started Mar 07 01:19:10 PM PST 24
Finished Mar 07 01:19:12 PM PST 24
Peak memory 206108 kb
Host smart-ed371caa-7974-4d63-a5c9-5feb03638c4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458469658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.458469658
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1528811052
Short name T1062
Test name
Test status
Simulation time 34983108 ps
CPU time 0.7 seconds
Started Mar 07 01:19:11 PM PST 24
Finished Mar 07 01:19:12 PM PST 24
Peak memory 205740 kb
Host smart-ca93a68a-97af-4bf5-8aa3-9d7f3367d2d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528811052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1528811052
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2043324520
Short name T1004
Test name
Test status
Simulation time 46184974 ps
CPU time 2.13 seconds
Started Mar 07 01:19:07 PM PST 24
Finished Mar 07 01:19:10 PM PST 24
Peak memory 205996 kb
Host smart-c3632fa8-d4d7-4a04-b4f9-149e6d86ab71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043324520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2043324520
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3637616319
Short name T122
Test name
Test status
Simulation time 525469205 ps
CPU time 5.91 seconds
Started Mar 07 01:19:16 PM PST 24
Finished Mar 07 01:19:22 PM PST 24
Peak memory 214508 kb
Host smart-73ecd906-5b1f-4cfb-a269-d84e89ed7669
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637616319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3637616319
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1167148339
Short name T1021
Test name
Test status
Simulation time 643037544 ps
CPU time 7.87 seconds
Started Mar 07 01:19:16 PM PST 24
Finished Mar 07 01:19:24 PM PST 24
Peak memory 214564 kb
Host smart-28f2bf66-d1f0-44ca-805c-795c6099008f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167148339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1167148339
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.350496593
Short name T934
Test name
Test status
Simulation time 77864066 ps
CPU time 1.99 seconds
Started Mar 07 01:19:07 PM PST 24
Finished Mar 07 01:19:10 PM PST 24
Peak memory 222320 kb
Host smart-4699a0a1-1330-4f1d-a7d1-ff4030aec1a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350496593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.350496593
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1752398928
Short name T962
Test name
Test status
Simulation time 31865044 ps
CPU time 1.66 seconds
Started Mar 07 01:19:05 PM PST 24
Finished Mar 07 01:19:07 PM PST 24
Peak memory 206144 kb
Host smart-26e2af0e-175a-4176-9ef2-4e881b101f32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752398928 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1752398928
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2681497830
Short name T976
Test name
Test status
Simulation time 142973486 ps
CPU time 1.2 seconds
Started Mar 07 01:19:08 PM PST 24
Finished Mar 07 01:19:09 PM PST 24
Peak memory 206076 kb
Host smart-d5f3e4e3-e4bc-436e-b4a9-3b3449d83678
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681497830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2681497830
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1035183243
Short name T974
Test name
Test status
Simulation time 78313150 ps
CPU time 0.78 seconds
Started Mar 07 01:19:11 PM PST 24
Finished Mar 07 01:19:11 PM PST 24
Peak memory 205784 kb
Host smart-6d2ea490-ee86-4be3-8c86-17a6addec03f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035183243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1035183243
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.41967454
Short name T950
Test name
Test status
Simulation time 199044676 ps
CPU time 2.11 seconds
Started Mar 07 01:19:16 PM PST 24
Finished Mar 07 01:19:18 PM PST 24
Peak memory 205928 kb
Host smart-c36c060e-4052-4b4e-8a70-51cd7f6bc48a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41967454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sam
e_csr_outstanding.41967454
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3553631990
Short name T935
Test name
Test status
Simulation time 363726464 ps
CPU time 2.08 seconds
Started Mar 07 01:19:13 PM PST 24
Finished Mar 07 01:19:15 PM PST 24
Peak memory 214564 kb
Host smart-8f376733-c4dc-4d79-a8de-8205e10fa562
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553631990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3553631990
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1775644902
Short name T117
Test name
Test status
Simulation time 283119683 ps
CPU time 3.69 seconds
Started Mar 07 01:19:11 PM PST 24
Finished Mar 07 01:19:15 PM PST 24
Peak memory 214708 kb
Host smart-4163e0f9-e86c-4f44-961b-7f3c2abc8d3f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775644902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1775644902
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2892309336
Short name T905
Test name
Test status
Simulation time 103004425 ps
CPU time 1.86 seconds
Started Mar 07 01:19:13 PM PST 24
Finished Mar 07 01:19:15 PM PST 24
Peak memory 214240 kb
Host smart-eeac0326-a3dd-46e4-a394-2576470326ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892309336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2892309336
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1701049571
Short name T1010
Test name
Test status
Simulation time 40894020 ps
CPU time 1.73 seconds
Started Mar 07 01:19:20 PM PST 24
Finished Mar 07 01:19:22 PM PST 24
Peak memory 214312 kb
Host smart-46714145-ed13-4884-8b0a-c34d1a24f3eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701049571 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1701049571
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1929950144
Short name T1048
Test name
Test status
Simulation time 27648741 ps
CPU time 1.09 seconds
Started Mar 07 01:19:22 PM PST 24
Finished Mar 07 01:19:23 PM PST 24
Peak memory 205952 kb
Host smart-321ceb14-343d-496d-af0d-469e108de547
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929950144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1929950144
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.637436706
Short name T904
Test name
Test status
Simulation time 18108245 ps
CPU time 0.81 seconds
Started Mar 07 01:19:08 PM PST 24
Finished Mar 07 01:19:09 PM PST 24
Peak memory 205720 kb
Host smart-556bb311-52e8-4d5d-9353-fdbfc91d042d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637436706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.637436706
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3534038590
Short name T915
Test name
Test status
Simulation time 48487795 ps
CPU time 1.53 seconds
Started Mar 07 01:19:19 PM PST 24
Finished Mar 07 01:19:21 PM PST 24
Peak memory 205964 kb
Host smart-2e61eccd-1d57-4c97-af76-9dcb9dcb2e9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534038590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3534038590
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3361182621
Short name T948
Test name
Test status
Simulation time 105339848 ps
CPU time 2.64 seconds
Started Mar 07 01:19:13 PM PST 24
Finished Mar 07 01:19:16 PM PST 24
Peak memory 214568 kb
Host smart-903f3709-595c-46bd-a28e-dd780336bc4f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361182621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3361182621
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1873196885
Short name T1035
Test name
Test status
Simulation time 99845877 ps
CPU time 4.88 seconds
Started Mar 07 01:19:06 PM PST 24
Finished Mar 07 01:19:12 PM PST 24
Peak memory 214552 kb
Host smart-94ab26e9-0af6-48c8-b3cb-20f1deb91ffb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873196885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1873196885
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.4207973472
Short name T896
Test name
Test status
Simulation time 93676490 ps
CPU time 2.01 seconds
Started Mar 07 01:19:13 PM PST 24
Finished Mar 07 01:19:15 PM PST 24
Peak memory 214280 kb
Host smart-e053e735-c0fd-4072-8a2c-6855ab8697dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207973472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.4207973472
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.914426469
Short name T174
Test name
Test status
Simulation time 1236671768 ps
CPU time 7.12 seconds
Started Mar 07 01:19:07 PM PST 24
Finished Mar 07 01:19:15 PM PST 24
Peak memory 209296 kb
Host smart-ed3a7d73-1f89-4089-bf0f-8e261ea28268
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914426469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.914426469
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3372672810
Short name T1026
Test name
Test status
Simulation time 18838609 ps
CPU time 1.5 seconds
Started Mar 07 01:19:21 PM PST 24
Finished Mar 07 01:19:23 PM PST 24
Peak memory 214196 kb
Host smart-57b647fb-9d23-430e-a0e4-d8aea20c2ce7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372672810 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3372672810
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.410806091
Short name T919
Test name
Test status
Simulation time 16976777 ps
CPU time 1.05 seconds
Started Mar 07 01:19:18 PM PST 24
Finished Mar 07 01:19:19 PM PST 24
Peak memory 206032 kb
Host smart-1732f150-69ee-4513-a5ca-f92bc38e54e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410806091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.410806091
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.324210762
Short name T986
Test name
Test status
Simulation time 9497017 ps
CPU time 0.73 seconds
Started Mar 07 01:19:17 PM PST 24
Finished Mar 07 01:19:18 PM PST 24
Peak memory 205672 kb
Host smart-7e053088-5511-4b93-907a-e43316cc0e44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324210762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.324210762
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1057786555
Short name T1002
Test name
Test status
Simulation time 470939068 ps
CPU time 2.57 seconds
Started Mar 07 01:19:18 PM PST 24
Finished Mar 07 01:19:21 PM PST 24
Peak memory 205948 kb
Host smart-55721d67-70a8-416e-ba6e-3239a214640a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057786555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1057786555
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.4195045099
Short name T128
Test name
Test status
Simulation time 159410098 ps
CPU time 2.74 seconds
Started Mar 07 01:19:19 PM PST 24
Finished Mar 07 01:19:22 PM PST 24
Peak memory 214396 kb
Host smart-759965d1-d9a3-4333-9706-96e4db51e1b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195045099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.4195045099
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2070559917
Short name T944
Test name
Test status
Simulation time 184439639 ps
CPU time 6.79 seconds
Started Mar 07 01:19:19 PM PST 24
Finished Mar 07 01:19:26 PM PST 24
Peak memory 214556 kb
Host smart-d7b104b9-d73e-4311-84ee-44c2d2a660ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070559917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2070559917
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1752647441
Short name T1003
Test name
Test status
Simulation time 91605901 ps
CPU time 1.67 seconds
Started Mar 07 01:19:20 PM PST 24
Finished Mar 07 01:19:22 PM PST 24
Peak memory 214136 kb
Host smart-fc99d8a5-6922-440f-86ad-01a5d8daf15d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752647441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1752647441
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2727512899
Short name T183
Test name
Test status
Simulation time 497029616 ps
CPU time 5.59 seconds
Started Mar 07 01:19:23 PM PST 24
Finished Mar 07 01:19:29 PM PST 24
Peak memory 209008 kb
Host smart-840645de-d590-4bf1-bff8-25b3c88b1d06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727512899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2727512899
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.739237769
Short name T987
Test name
Test status
Simulation time 317264571 ps
CPU time 2.05 seconds
Started Mar 07 01:19:20 PM PST 24
Finished Mar 07 01:19:22 PM PST 24
Peak memory 214292 kb
Host smart-31e2763c-df54-4a20-bc2c-eb6fe00c1e2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739237769 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.739237769
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1882432706
Short name T144
Test name
Test status
Simulation time 343360906 ps
CPU time 1.53 seconds
Started Mar 07 01:19:23 PM PST 24
Finished Mar 07 01:19:25 PM PST 24
Peak memory 206116 kb
Host smart-0c5789f8-3e80-444b-a154-59df0b998395
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882432706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1882432706
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3873733587
Short name T995
Test name
Test status
Simulation time 101505293 ps
CPU time 0.71 seconds
Started Mar 07 01:19:18 PM PST 24
Finished Mar 07 01:19:20 PM PST 24
Peak memory 205796 kb
Host smart-5af487a4-6648-44c6-9729-02f4145acfaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873733587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3873733587
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1371919878
Short name T1058
Test name
Test status
Simulation time 729024657 ps
CPU time 3.38 seconds
Started Mar 07 01:19:18 PM PST 24
Finished Mar 07 01:19:21 PM PST 24
Peak memory 206044 kb
Host smart-d0e19e9d-58a7-4a18-84f8-e8e9653e9997
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371919878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1371919878
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.426652837
Short name T959
Test name
Test status
Simulation time 144459769 ps
CPU time 1.77 seconds
Started Mar 07 01:19:20 PM PST 24
Finished Mar 07 01:19:22 PM PST 24
Peak memory 222280 kb
Host smart-f25fed78-5911-4add-9f1e-4c484c78f649
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426652837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.426652837
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2544226594
Short name T127
Test name
Test status
Simulation time 1418199426 ps
CPU time 12.22 seconds
Started Mar 07 01:19:21 PM PST 24
Finished Mar 07 01:19:34 PM PST 24
Peak memory 214544 kb
Host smart-f9af6ea1-f87e-4f8c-92d6-2441de31257e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544226594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2544226594
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1736549932
Short name T978
Test name
Test status
Simulation time 297211165 ps
CPU time 2.95 seconds
Started Mar 07 01:19:18 PM PST 24
Finished Mar 07 01:19:21 PM PST 24
Peak memory 215200 kb
Host smart-e59f1c55-56c6-4b10-8b99-5a1e127f0e73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736549932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1736549932
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2179381091
Short name T175
Test name
Test status
Simulation time 383525126 ps
CPU time 4.91 seconds
Started Mar 07 01:19:22 PM PST 24
Finished Mar 07 01:19:27 PM PST 24
Peak memory 209732 kb
Host smart-0461fa95-df6f-4882-a3f2-f1b870ae05f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179381091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2179381091
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.4271567816
Short name T983
Test name
Test status
Simulation time 1908855317 ps
CPU time 9.85 seconds
Started Mar 07 01:18:49 PM PST 24
Finished Mar 07 01:18:59 PM PST 24
Peak memory 206080 kb
Host smart-5c095573-0c90-497a-b86c-13e487c3de19
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271567816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.4
271567816
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.590345087
Short name T979
Test name
Test status
Simulation time 1042914876 ps
CPU time 15.37 seconds
Started Mar 07 01:18:49 PM PST 24
Finished Mar 07 01:19:05 PM PST 24
Peak memory 205976 kb
Host smart-d3715121-f9d6-4a2e-8a50-5c16b604b7f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590345087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.590345087
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1123047326
Short name T917
Test name
Test status
Simulation time 48177437 ps
CPU time 1.11 seconds
Started Mar 07 01:18:49 PM PST 24
Finished Mar 07 01:18:51 PM PST 24
Peak memory 206004 kb
Host smart-eb22e786-313a-4966-a98c-99d88be5c1b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123047326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
123047326
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.612773807
Short name T931
Test name
Test status
Simulation time 285196520 ps
CPU time 1.58 seconds
Started Mar 07 01:18:56 PM PST 24
Finished Mar 07 01:18:59 PM PST 24
Peak memory 214448 kb
Host smart-e1326997-6ade-47c5-b436-a0e56e5c867f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612773807 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.612773807
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2063872074
Short name T1065
Test name
Test status
Simulation time 43608714 ps
CPU time 1.53 seconds
Started Mar 07 01:18:50 PM PST 24
Finished Mar 07 01:18:52 PM PST 24
Peak memory 205984 kb
Host smart-d6ccb96c-eeaf-4893-93d4-721a571bcc24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063872074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2063872074
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1436516416
Short name T969
Test name
Test status
Simulation time 27054607 ps
CPU time 0.8 seconds
Started Mar 07 01:18:54 PM PST 24
Finished Mar 07 01:18:56 PM PST 24
Peak memory 205744 kb
Host smart-06615667-f5db-412f-a2d9-ab3a4137cb32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436516416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1436516416
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1320989509
Short name T923
Test name
Test status
Simulation time 263693605 ps
CPU time 1.58 seconds
Started Mar 07 01:18:49 PM PST 24
Finished Mar 07 01:18:51 PM PST 24
Peak memory 206012 kb
Host smart-21446370-0d8f-456b-b248-4c4c6a96d771
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320989509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1320989509
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3249047595
Short name T981
Test name
Test status
Simulation time 2401401726 ps
CPU time 3.88 seconds
Started Mar 07 01:18:48 PM PST 24
Finished Mar 07 01:18:52 PM PST 24
Peak memory 214492 kb
Host smart-66999855-907b-40a2-b3ea-e4b362fec070
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249047595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3249047595
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3867842989
Short name T941
Test name
Test status
Simulation time 294313038 ps
CPU time 3.59 seconds
Started Mar 07 01:18:49 PM PST 24
Finished Mar 07 01:18:53 PM PST 24
Peak memory 214640 kb
Host smart-4d6a8b38-07a7-42e4-aecb-965d9c157676
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867842989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3867842989
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2951349264
Short name T951
Test name
Test status
Simulation time 515188661 ps
CPU time 5.25 seconds
Started Mar 07 01:18:49 PM PST 24
Finished Mar 07 01:18:54 PM PST 24
Peak memory 214268 kb
Host smart-517d3383-eaa3-4dab-b317-ea36a8ec8d40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951349264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2951349264
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2405339724
Short name T164
Test name
Test status
Simulation time 192806065 ps
CPU time 3.17 seconds
Started Mar 07 01:18:55 PM PST 24
Finished Mar 07 01:18:59 PM PST 24
Peak memory 214420 kb
Host smart-0bbcaec7-348f-4108-afb0-de0d1dc49ea9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405339724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2405339724
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3964173507
Short name T994
Test name
Test status
Simulation time 31633066 ps
CPU time 0.68 seconds
Started Mar 07 01:19:22 PM PST 24
Finished Mar 07 01:19:23 PM PST 24
Peak memory 205652 kb
Host smart-2db1bce8-27e0-49dd-95b3-2dfec92388cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964173507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3964173507
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3593753001
Short name T924
Test name
Test status
Simulation time 20786867 ps
CPU time 0.85 seconds
Started Mar 07 01:19:18 PM PST 24
Finished Mar 07 01:19:19 PM PST 24
Peak memory 205604 kb
Host smart-427dee81-b0c2-4b7a-b489-2f33cd4bf6bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593753001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3593753001
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.430370799
Short name T899
Test name
Test status
Simulation time 127264604 ps
CPU time 0.87 seconds
Started Mar 07 01:19:20 PM PST 24
Finished Mar 07 01:19:21 PM PST 24
Peak memory 205652 kb
Host smart-5afbffa6-fed4-45d8-838a-d3d1a1318708
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430370799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.430370799
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2282841540
Short name T943
Test name
Test status
Simulation time 25273295 ps
CPU time 0.72 seconds
Started Mar 07 01:19:16 PM PST 24
Finished Mar 07 01:19:17 PM PST 24
Peak memory 205804 kb
Host smart-af56d67e-7f67-4b50-b972-190b7d10ece0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282841540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2282841540
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3744453515
Short name T1012
Test name
Test status
Simulation time 13298039 ps
CPU time 0.69 seconds
Started Mar 07 01:19:23 PM PST 24
Finished Mar 07 01:19:24 PM PST 24
Peak memory 205688 kb
Host smart-3a5d3ace-53f4-4e69-b225-1c982486b9d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744453515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3744453515
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.4179455942
Short name T1015
Test name
Test status
Simulation time 12483424 ps
CPU time 0.72 seconds
Started Mar 07 01:19:18 PM PST 24
Finished Mar 07 01:19:19 PM PST 24
Peak memory 205724 kb
Host smart-8d3a66b0-6138-4ad6-b042-0af49426716b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179455942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.4179455942
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3990120805
Short name T927
Test name
Test status
Simulation time 13830256 ps
CPU time 0.77 seconds
Started Mar 07 01:19:19 PM PST 24
Finished Mar 07 01:19:20 PM PST 24
Peak memory 205580 kb
Host smart-a72883a1-8ec9-4faf-a25f-809fc0dfeba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990120805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3990120805
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3207048890
Short name T964
Test name
Test status
Simulation time 8171300 ps
CPU time 0.72 seconds
Started Mar 07 01:19:22 PM PST 24
Finished Mar 07 01:19:22 PM PST 24
Peak memory 205772 kb
Host smart-fd919d98-7fd5-40fc-a51f-17e182eef95f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207048890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3207048890
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3478196264
Short name T906
Test name
Test status
Simulation time 23924700 ps
CPU time 0.84 seconds
Started Mar 07 01:19:22 PM PST 24
Finished Mar 07 01:19:22 PM PST 24
Peak memory 205772 kb
Host smart-2a0db170-e2d9-4fc9-84bd-a9fcfc9fc8e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478196264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3478196264
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2646235406
Short name T982
Test name
Test status
Simulation time 19866340 ps
CPU time 0.74 seconds
Started Mar 07 01:19:25 PM PST 24
Finished Mar 07 01:19:26 PM PST 24
Peak memory 205768 kb
Host smart-2159d601-282b-4331-b7ed-4c42c1a530eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646235406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2646235406
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1622607713
Short name T954
Test name
Test status
Simulation time 380845333 ps
CPU time 9.2 seconds
Started Mar 07 01:18:53 PM PST 24
Finished Mar 07 01:19:04 PM PST 24
Peak memory 206064 kb
Host smart-66d8d1e5-a620-4785-ae65-61ef8b089b7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622607713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
622607713
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.292592853
Short name T1041
Test name
Test status
Simulation time 1929580231 ps
CPU time 12.23 seconds
Started Mar 07 01:18:50 PM PST 24
Finished Mar 07 01:19:03 PM PST 24
Peak memory 205988 kb
Host smart-bd87b0e4-1caa-4589-bb54-de7f7e4ec1c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292592853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.292592853
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4283107831
Short name T1028
Test name
Test status
Simulation time 38376602 ps
CPU time 1.09 seconds
Started Mar 07 01:18:50 PM PST 24
Finished Mar 07 01:18:52 PM PST 24
Peak memory 205908 kb
Host smart-148f72d9-840c-404d-a5ce-e7eaae320053
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283107831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.4
283107831
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2156401095
Short name T1036
Test name
Test status
Simulation time 43539790 ps
CPU time 1.43 seconds
Started Mar 07 01:18:49 PM PST 24
Finished Mar 07 01:18:51 PM PST 24
Peak memory 214288 kb
Host smart-2ca3b6fc-746f-474d-b096-68828006fa38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156401095 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2156401095
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1800919816
Short name T1017
Test name
Test status
Simulation time 49540560 ps
CPU time 1.03 seconds
Started Mar 07 01:18:49 PM PST 24
Finished Mar 07 01:18:51 PM PST 24
Peak memory 205748 kb
Host smart-b3321258-5ebc-4f91-8fea-f44d6a33051c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800919816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1800919816
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.4155802123
Short name T1014
Test name
Test status
Simulation time 23936486 ps
CPU time 0.88 seconds
Started Mar 07 01:18:49 PM PST 24
Finished Mar 07 01:18:50 PM PST 24
Peak memory 205724 kb
Host smart-c3145f1d-3c21-4246-ae7b-96413f11cfa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155802123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.4155802123
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.404303873
Short name T1000
Test name
Test status
Simulation time 346661473 ps
CPU time 2.47 seconds
Started Mar 07 01:18:51 PM PST 24
Finished Mar 07 01:18:54 PM PST 24
Peak memory 205988 kb
Host smart-aabc3250-c938-4c81-9d57-75953efccf31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404303873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.404303873
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1405427748
Short name T1039
Test name
Test status
Simulation time 99446298 ps
CPU time 3.18 seconds
Started Mar 07 01:18:53 PM PST 24
Finished Mar 07 01:18:58 PM PST 24
Peak memory 222488 kb
Host smart-7993fd78-c82a-413b-983e-1712444895e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405427748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1405427748
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1472986210
Short name T989
Test name
Test status
Simulation time 1589877647 ps
CPU time 10.79 seconds
Started Mar 07 01:18:50 PM PST 24
Finished Mar 07 01:19:01 PM PST 24
Peak memory 214524 kb
Host smart-9f7ca824-f41f-4697-8f4b-dba55c7f888d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472986210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1472986210
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.430890555
Short name T992
Test name
Test status
Simulation time 30153248 ps
CPU time 1.86 seconds
Started Mar 07 01:18:49 PM PST 24
Finished Mar 07 01:18:51 PM PST 24
Peak memory 214216 kb
Host smart-f9bf0144-6486-4a2f-97a4-8ca0e09325f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430890555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.430890555
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1051648625
Short name T1059
Test name
Test status
Simulation time 137547876 ps
CPU time 5.27 seconds
Started Mar 07 01:18:52 PM PST 24
Finished Mar 07 01:18:58 PM PST 24
Peak memory 209628 kb
Host smart-08063f4e-0e10-419a-95d9-a24f5a39a5d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051648625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1051648625
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2748040136
Short name T966
Test name
Test status
Simulation time 35808381 ps
CPU time 0.83 seconds
Started Mar 07 01:19:19 PM PST 24
Finished Mar 07 01:19:20 PM PST 24
Peak memory 205700 kb
Host smart-8ba081f2-e098-4def-9179-a81ba6721617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748040136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2748040136
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3823961206
Short name T1057
Test name
Test status
Simulation time 32542851 ps
CPU time 0.73 seconds
Started Mar 07 01:19:18 PM PST 24
Finished Mar 07 01:19:20 PM PST 24
Peak memory 205680 kb
Host smart-dbb348c1-101b-4cf1-a2f8-d23a4f584ad7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823961206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3823961206
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.905963585
Short name T1018
Test name
Test status
Simulation time 14912638 ps
CPU time 0.71 seconds
Started Mar 07 01:19:21 PM PST 24
Finished Mar 07 01:19:22 PM PST 24
Peak memory 205820 kb
Host smart-610a8337-8ada-4dfe-a7d6-c2e3dc043a8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905963585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.905963585
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.220397879
Short name T922
Test name
Test status
Simulation time 73559454 ps
CPU time 0.77 seconds
Started Mar 07 01:19:21 PM PST 24
Finished Mar 07 01:19:22 PM PST 24
Peak memory 205744 kb
Host smart-d7973205-829e-41e0-a40f-262e54d1f09f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220397879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.220397879
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1001622189
Short name T1025
Test name
Test status
Simulation time 11570764 ps
CPU time 0.77 seconds
Started Mar 07 01:19:23 PM PST 24
Finished Mar 07 01:19:24 PM PST 24
Peak memory 205648 kb
Host smart-3fbeb109-b51c-4547-b13e-ade7eb49baec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001622189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1001622189
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.4035542823
Short name T911
Test name
Test status
Simulation time 27921067 ps
CPU time 0.75 seconds
Started Mar 07 01:19:23 PM PST 24
Finished Mar 07 01:19:24 PM PST 24
Peak memory 205672 kb
Host smart-f28060f3-3eac-4bb5-a22a-c9597f091517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035542823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.4035542823
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3738680558
Short name T1049
Test name
Test status
Simulation time 15257817 ps
CPU time 0.79 seconds
Started Mar 07 01:19:21 PM PST 24
Finished Mar 07 01:19:22 PM PST 24
Peak memory 205656 kb
Host smart-db315a9e-b955-4aa6-a723-def1b2804cf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738680558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3738680558
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2129973491
Short name T1047
Test name
Test status
Simulation time 45063404 ps
CPU time 0.7 seconds
Started Mar 07 01:19:21 PM PST 24
Finished Mar 07 01:19:22 PM PST 24
Peak memory 205732 kb
Host smart-3d6c068b-893d-47b7-acf3-51b3b6d52cfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129973491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2129973491
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.444054697
Short name T920
Test name
Test status
Simulation time 20229890 ps
CPU time 0.72 seconds
Started Mar 07 01:19:22 PM PST 24
Finished Mar 07 01:19:23 PM PST 24
Peak memory 205744 kb
Host smart-a5ab85e7-9ce9-436a-ac7c-88bf7ebc1da1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444054697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.444054697
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.372635484
Short name T1016
Test name
Test status
Simulation time 11890976 ps
CPU time 0.75 seconds
Started Mar 07 01:19:23 PM PST 24
Finished Mar 07 01:19:23 PM PST 24
Peak memory 205728 kb
Host smart-f4986832-5c1f-4821-a920-9b6121255569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372635484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.372635484
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.4023350722
Short name T991
Test name
Test status
Simulation time 468335040 ps
CPU time 11.83 seconds
Started Mar 07 01:18:48 PM PST 24
Finished Mar 07 01:19:00 PM PST 24
Peak memory 206084 kb
Host smart-8593320d-c527-4f6d-9409-67f3ca69debc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023350722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.4
023350722
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2548781943
Short name T916
Test name
Test status
Simulation time 876986634 ps
CPU time 17.18 seconds
Started Mar 07 01:18:55 PM PST 24
Finished Mar 07 01:19:14 PM PST 24
Peak memory 206020 kb
Host smart-e0e80332-7f7b-4d56-84c8-b8b5362301d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548781943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
548781943
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.50452805
Short name T940
Test name
Test status
Simulation time 21259336 ps
CPU time 0.98 seconds
Started Mar 07 01:18:48 PM PST 24
Finished Mar 07 01:18:49 PM PST 24
Peak memory 205832 kb
Host smart-d9423c19-7963-4091-a703-f1bb1723b210
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50452805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.50452805
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3551498118
Short name T1046
Test name
Test status
Simulation time 36423191 ps
CPU time 1.7 seconds
Started Mar 07 01:18:53 PM PST 24
Finished Mar 07 01:18:57 PM PST 24
Peak memory 217048 kb
Host smart-050cb787-9011-44c5-a27d-79ab4e2adb1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551498118 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3551498118
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1381466305
Short name T925
Test name
Test status
Simulation time 184349802 ps
CPU time 1.03 seconds
Started Mar 07 01:18:54 PM PST 24
Finished Mar 07 01:18:56 PM PST 24
Peak memory 205672 kb
Host smart-a49114de-9960-4a90-99f2-0579020ffd3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381466305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1381466305
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1390677897
Short name T938
Test name
Test status
Simulation time 32248170 ps
CPU time 0.8 seconds
Started Mar 07 01:18:56 PM PST 24
Finished Mar 07 01:18:59 PM PST 24
Peak memory 205744 kb
Host smart-1282b7f2-686a-4ecf-a892-e5a30af263b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390677897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1390677897
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.468481990
Short name T909
Test name
Test status
Simulation time 103569130 ps
CPU time 4.31 seconds
Started Mar 07 01:18:52 PM PST 24
Finished Mar 07 01:18:57 PM PST 24
Peak memory 206096 kb
Host smart-a41877ab-5fc2-4cb2-9030-3a0eefbd6ee0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468481990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam
e_csr_outstanding.468481990
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3598002635
Short name T1019
Test name
Test status
Simulation time 211443005 ps
CPU time 2.57 seconds
Started Mar 07 01:18:48 PM PST 24
Finished Mar 07 01:18:50 PM PST 24
Peak memory 214548 kb
Host smart-72eb3ee3-c01d-4a58-9245-f63b2225667d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598002635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3598002635
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2365746311
Short name T1008
Test name
Test status
Simulation time 158787080 ps
CPU time 8.81 seconds
Started Mar 07 01:18:53 PM PST 24
Finished Mar 07 01:19:04 PM PST 24
Peak memory 214592 kb
Host smart-478cf8c5-c8e2-4c51-a0f3-34747ef13e95
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365746311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2365746311
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1447863987
Short name T921
Test name
Test status
Simulation time 537761170 ps
CPU time 3.53 seconds
Started Mar 07 01:18:48 PM PST 24
Finished Mar 07 01:18:51 PM PST 24
Peak memory 214228 kb
Host smart-fd423a7d-8d36-438d-8b8a-eaa0803d3321
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447863987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1447863987
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2368369315
Short name T967
Test name
Test status
Simulation time 2406773584 ps
CPU time 28.19 seconds
Started Mar 07 01:18:48 PM PST 24
Finished Mar 07 01:19:16 PM PST 24
Peak memory 210284 kb
Host smart-322ef965-d06b-45f0-9de6-3aa0821acfc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368369315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2368369315
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2287199215
Short name T937
Test name
Test status
Simulation time 45558823 ps
CPU time 0.86 seconds
Started Mar 07 01:19:23 PM PST 24
Finished Mar 07 01:19:24 PM PST 24
Peak memory 205744 kb
Host smart-cd0cb2bf-db2b-42c7-bec3-d01fa09cad95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287199215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2287199215
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3928034847
Short name T996
Test name
Test status
Simulation time 31492417 ps
CPU time 0.76 seconds
Started Mar 07 01:19:21 PM PST 24
Finished Mar 07 01:19:21 PM PST 24
Peak memory 205744 kb
Host smart-fed245ff-a9cd-411b-837d-a1aeba81a7e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928034847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3928034847
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.888004083
Short name T926
Test name
Test status
Simulation time 66832185 ps
CPU time 0.81 seconds
Started Mar 07 01:19:21 PM PST 24
Finished Mar 07 01:19:22 PM PST 24
Peak memory 205668 kb
Host smart-2a0e13e3-2d56-43e2-b52c-77a50541fad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888004083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.888004083
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1263239402
Short name T1001
Test name
Test status
Simulation time 29409398 ps
CPU time 0.79 seconds
Started Mar 07 01:19:26 PM PST 24
Finished Mar 07 01:19:27 PM PST 24
Peak memory 205764 kb
Host smart-42e323c6-6e7e-46d3-9006-3a35484e73cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263239402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1263239402
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2714138253
Short name T901
Test name
Test status
Simulation time 14555107 ps
CPU time 0.89 seconds
Started Mar 07 01:19:21 PM PST 24
Finished Mar 07 01:19:22 PM PST 24
Peak memory 205872 kb
Host smart-b37212d7-3f62-4353-b938-21f1413e83da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714138253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2714138253
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1186362590
Short name T1030
Test name
Test status
Simulation time 38284091 ps
CPU time 0.72 seconds
Started Mar 07 01:19:25 PM PST 24
Finished Mar 07 01:19:25 PM PST 24
Peak memory 205692 kb
Host smart-c0d550fd-8353-4805-9daa-2e3ed73ef518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186362590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1186362590
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.87889975
Short name T897
Test name
Test status
Simulation time 16035570 ps
CPU time 0.96 seconds
Started Mar 07 01:19:25 PM PST 24
Finished Mar 07 01:19:26 PM PST 24
Peak memory 205836 kb
Host smart-96d1680a-9333-4e60-9210-aa8d4b15cea4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87889975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.87889975
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3166768038
Short name T1011
Test name
Test status
Simulation time 38992553 ps
CPU time 0.82 seconds
Started Mar 07 01:19:24 PM PST 24
Finished Mar 07 01:19:24 PM PST 24
Peak memory 205676 kb
Host smart-3a70dfd0-6d41-4f89-9f6a-3feada16f507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166768038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3166768038
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2572263477
Short name T1033
Test name
Test status
Simulation time 34324767 ps
CPU time 0.71 seconds
Started Mar 07 01:19:21 PM PST 24
Finished Mar 07 01:19:22 PM PST 24
Peak memory 205676 kb
Host smart-d9d5bfc6-e0db-475e-b33b-a45c762cf53d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572263477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2572263477
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1108372182
Short name T913
Test name
Test status
Simulation time 10495898 ps
CPU time 0.81 seconds
Started Mar 07 01:19:29 PM PST 24
Finished Mar 07 01:19:30 PM PST 24
Peak memory 205696 kb
Host smart-14999b74-e8ac-4113-9aa1-75eb77ad3d55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108372182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1108372182
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3114270299
Short name T929
Test name
Test status
Simulation time 25219821 ps
CPU time 1.22 seconds
Started Mar 07 01:19:08 PM PST 24
Finished Mar 07 01:19:09 PM PST 24
Peak memory 206012 kb
Host smart-e36c8234-83c8-4387-80f4-6755f36ed6bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114270299 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3114270299
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1795997914
Short name T993
Test name
Test status
Simulation time 21291809 ps
CPU time 0.89 seconds
Started Mar 07 01:19:04 PM PST 24
Finished Mar 07 01:19:05 PM PST 24
Peak memory 205784 kb
Host smart-654595d2-eeab-43c6-b916-cffd4e5383fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795997914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1795997914
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.4266417938
Short name T942
Test name
Test status
Simulation time 25463691 ps
CPU time 0.92 seconds
Started Mar 07 01:19:04 PM PST 24
Finished Mar 07 01:19:05 PM PST 24
Peak memory 205772 kb
Host smart-ea91f963-f516-40ff-a636-932d0f8dd3da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266417938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.4266417938
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3394658033
Short name T1029
Test name
Test status
Simulation time 229278726 ps
CPU time 1.74 seconds
Started Mar 07 01:19:04 PM PST 24
Finished Mar 07 01:19:05 PM PST 24
Peak memory 205972 kb
Host smart-d9cd0b49-94d7-4417-ac28-f59821109bbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394658033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3394658033
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1768287895
Short name T1043
Test name
Test status
Simulation time 296386679 ps
CPU time 2.43 seconds
Started Mar 07 01:18:51 PM PST 24
Finished Mar 07 01:18:53 PM PST 24
Peak memory 222624 kb
Host smart-aa66b5df-f53c-4f1a-b167-3a7f9f228e6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768287895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1768287895
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.298886104
Short name T898
Test name
Test status
Simulation time 351345734 ps
CPU time 3.27 seconds
Started Mar 07 01:18:50 PM PST 24
Finished Mar 07 01:18:54 PM PST 24
Peak memory 214164 kb
Host smart-b2f372d9-6c81-4d0a-81fc-252bc84b60d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298886104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.298886104
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3820788172
Short name T1027
Test name
Test status
Simulation time 284869762 ps
CPU time 5.3 seconds
Started Mar 07 01:19:05 PM PST 24
Finished Mar 07 01:19:10 PM PST 24
Peak memory 209164 kb
Host smart-1a108c48-850c-4a44-885f-3f4c3f0734fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820788172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3820788172
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3772650176
Short name T984
Test name
Test status
Simulation time 52602122 ps
CPU time 1.41 seconds
Started Mar 07 01:19:09 PM PST 24
Finished Mar 07 01:19:11 PM PST 24
Peak memory 214276 kb
Host smart-a57cbafb-befe-4188-b1f3-01224a00f504
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772650176 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3772650176
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3428956293
Short name T1024
Test name
Test status
Simulation time 16133453 ps
CPU time 1.22 seconds
Started Mar 07 01:19:03 PM PST 24
Finished Mar 07 01:19:05 PM PST 24
Peak memory 206044 kb
Host smart-701231ec-8978-4a18-9b20-d37055c45c8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428956293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3428956293
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3901532594
Short name T1052
Test name
Test status
Simulation time 8075940 ps
CPU time 0.7 seconds
Started Mar 07 01:19:06 PM PST 24
Finished Mar 07 01:19:07 PM PST 24
Peak memory 205668 kb
Host smart-88def4ba-f683-4d0f-9c47-cfa91767a892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901532594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3901532594
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.804615543
Short name T930
Test name
Test status
Simulation time 393555341 ps
CPU time 2.78 seconds
Started Mar 07 01:19:06 PM PST 24
Finished Mar 07 01:19:09 PM PST 24
Peak memory 206028 kb
Host smart-ed764ffd-f489-4823-9010-9054cfd50fb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804615543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.804615543
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2036310067
Short name T1051
Test name
Test status
Simulation time 52632096 ps
CPU time 1.9 seconds
Started Mar 07 01:19:04 PM PST 24
Finished Mar 07 01:19:06 PM PST 24
Peak memory 214492 kb
Host smart-d0edec3e-ac4a-4c17-bc0c-66154e1fc39b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036310067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2036310067
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.297892396
Short name T125
Test name
Test status
Simulation time 579066023 ps
CPU time 8.73 seconds
Started Mar 07 01:19:02 PM PST 24
Finished Mar 07 01:19:11 PM PST 24
Peak memory 214420 kb
Host smart-cc991894-2a25-4a05-9e35-31c8a5c87daf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297892396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.297892396
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3980917710
Short name T999
Test name
Test status
Simulation time 148706353 ps
CPU time 2.15 seconds
Started Mar 07 01:19:03 PM PST 24
Finished Mar 07 01:19:05 PM PST 24
Peak memory 217300 kb
Host smart-3ea7865a-940b-44fb-a101-88ece0798868
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980917710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3980917710
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1848916487
Short name T181
Test name
Test status
Simulation time 99304359 ps
CPU time 3.67 seconds
Started Mar 07 01:19:04 PM PST 24
Finished Mar 07 01:19:08 PM PST 24
Peak memory 214296 kb
Host smart-16d25035-3e2e-4100-a4fa-81ba7541e570
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848916487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1848916487
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2927940617
Short name T1031
Test name
Test status
Simulation time 40988607 ps
CPU time 1.52 seconds
Started Mar 07 01:19:03 PM PST 24
Finished Mar 07 01:19:05 PM PST 24
Peak memory 214300 kb
Host smart-303af813-b356-4709-a80d-f1c819fd3715
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927940617 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2927940617
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1389055400
Short name T1013
Test name
Test status
Simulation time 263438227 ps
CPU time 1.12 seconds
Started Mar 07 01:19:09 PM PST 24
Finished Mar 07 01:19:10 PM PST 24
Peak memory 205944 kb
Host smart-2abb6032-dd3a-4a13-9625-bf0fc3a1f605
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389055400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1389055400
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1187413063
Short name T955
Test name
Test status
Simulation time 139569458 ps
CPU time 0.84 seconds
Started Mar 07 01:19:06 PM PST 24
Finished Mar 07 01:19:07 PM PST 24
Peak memory 205768 kb
Host smart-88512f08-015c-48b8-aa4a-a1f69f822380
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187413063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1187413063
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2552613858
Short name T1055
Test name
Test status
Simulation time 631303508 ps
CPU time 2.81 seconds
Started Mar 07 01:19:03 PM PST 24
Finished Mar 07 01:19:06 PM PST 24
Peak memory 206020 kb
Host smart-7c9fd0db-40bc-4dec-b406-a43355b1997a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552613858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2552613858
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2766284045
Short name T971
Test name
Test status
Simulation time 818810323 ps
CPU time 5.68 seconds
Started Mar 07 01:19:03 PM PST 24
Finished Mar 07 01:19:09 PM PST 24
Peak memory 214520 kb
Host smart-966be816-b4c0-44f8-b9fc-eb7f4c2e245e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766284045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2766284045
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1239509017
Short name T1067
Test name
Test status
Simulation time 257885298 ps
CPU time 4.22 seconds
Started Mar 07 01:19:04 PM PST 24
Finished Mar 07 01:19:09 PM PST 24
Peak memory 214524 kb
Host smart-ae38d7a6-b7a6-424d-8ace-3cc54205dc26
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239509017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1239509017
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1228043890
Short name T968
Test name
Test status
Simulation time 187319632 ps
CPU time 3.37 seconds
Started Mar 07 01:19:06 PM PST 24
Finished Mar 07 01:19:10 PM PST 24
Peak memory 214088 kb
Host smart-83d62d4a-ae20-4056-a307-a34ba3fe409b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228043890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1228043890
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.709673336
Short name T1022
Test name
Test status
Simulation time 699767537 ps
CPU time 12.75 seconds
Started Mar 07 01:19:05 PM PST 24
Finished Mar 07 01:19:18 PM PST 24
Peak memory 209052 kb
Host smart-6e34468a-d89d-4045-b0a8-eb09e06ab4d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709673336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
709673336
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3793679347
Short name T1007
Test name
Test status
Simulation time 48162741 ps
CPU time 1.67 seconds
Started Mar 07 01:19:04 PM PST 24
Finished Mar 07 01:19:06 PM PST 24
Peak memory 214336 kb
Host smart-c6f37467-193b-471a-92e1-060a966d6786
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793679347 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3793679347
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.762388792
Short name T998
Test name
Test status
Simulation time 52879798 ps
CPU time 1.25 seconds
Started Mar 07 01:19:05 PM PST 24
Finished Mar 07 01:19:06 PM PST 24
Peak memory 206080 kb
Host smart-8f06c47f-453f-4d5e-825e-d1fabd275114
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762388792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.762388792
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2130572589
Short name T975
Test name
Test status
Simulation time 10181441 ps
CPU time 0.78 seconds
Started Mar 07 01:19:07 PM PST 24
Finished Mar 07 01:19:08 PM PST 24
Peak memory 205652 kb
Host smart-dde07481-d7b7-4df1-acea-36ab2d741074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130572589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2130572589
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1218652608
Short name T949
Test name
Test status
Simulation time 36203612 ps
CPU time 1.58 seconds
Started Mar 07 01:19:07 PM PST 24
Finished Mar 07 01:19:09 PM PST 24
Peak memory 206068 kb
Host smart-7e102fa9-bf4c-4a8e-b14e-ba7d36d3908d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218652608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1218652608
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2812765356
Short name T1009
Test name
Test status
Simulation time 4067246160 ps
CPU time 23.25 seconds
Started Mar 07 01:19:11 PM PST 24
Finished Mar 07 01:19:35 PM PST 24
Peak memory 217952 kb
Host smart-c10b1f31-7ae4-4d35-aaf9-0e208b3e5576
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812765356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2812765356
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1968670143
Short name T961
Test name
Test status
Simulation time 267312957 ps
CPU time 9.12 seconds
Started Mar 07 01:19:05 PM PST 24
Finished Mar 07 01:19:14 PM PST 24
Peak memory 214564 kb
Host smart-9e210f6f-46ad-4456-9f24-36d08eaafe11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968670143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1968670143
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1482016740
Short name T1064
Test name
Test status
Simulation time 277590558 ps
CPU time 2.2 seconds
Started Mar 07 01:19:06 PM PST 24
Finished Mar 07 01:19:09 PM PST 24
Peak memory 214256 kb
Host smart-28aadf4f-d43c-4773-8c38-3834ada3e380
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482016740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1482016740
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2319908625
Short name T176
Test name
Test status
Simulation time 90707398 ps
CPU time 3.91 seconds
Started Mar 07 01:19:03 PM PST 24
Finished Mar 07 01:19:07 PM PST 24
Peak memory 209252 kb
Host smart-78dd812b-a6d8-4635-bd71-f25cd176780c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319908625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2319908625
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.258547169
Short name T952
Test name
Test status
Simulation time 43176931 ps
CPU time 1.97 seconds
Started Mar 07 01:19:04 PM PST 24
Finished Mar 07 01:19:06 PM PST 24
Peak memory 217492 kb
Host smart-a034db8a-2d14-428f-9982-eac92d9361df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258547169 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.258547169
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3035269618
Short name T146
Test name
Test status
Simulation time 26071193 ps
CPU time 1.55 seconds
Started Mar 07 01:19:04 PM PST 24
Finished Mar 07 01:19:06 PM PST 24
Peak memory 206036 kb
Host smart-1d487395-9641-45e7-9c97-ca1695a61dda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035269618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3035269618
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.807499258
Short name T932
Test name
Test status
Simulation time 13427821 ps
CPU time 0.74 seconds
Started Mar 07 01:19:05 PM PST 24
Finished Mar 07 01:19:05 PM PST 24
Peak memory 205672 kb
Host smart-7f29639d-0f0e-483a-b1a3-eaa823ad1fb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807499258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.807499258
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1613424824
Short name T147
Test name
Test status
Simulation time 51226188 ps
CPU time 1.49 seconds
Started Mar 07 01:19:08 PM PST 24
Finished Mar 07 01:19:10 PM PST 24
Peak memory 206016 kb
Host smart-5b95aa16-7b8d-4490-82b2-a70969e1180a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613424824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1613424824
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1074153572
Short name T1023
Test name
Test status
Simulation time 167486408 ps
CPU time 4.97 seconds
Started Mar 07 01:19:04 PM PST 24
Finished Mar 07 01:19:09 PM PST 24
Peak memory 214528 kb
Host smart-039fe168-b2ac-4e3f-9b09-4dc01f21636a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074153572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1074153572
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2104202874
Short name T121
Test name
Test status
Simulation time 761555247 ps
CPU time 7.19 seconds
Started Mar 07 01:19:05 PM PST 24
Finished Mar 07 01:19:12 PM PST 24
Peak memory 214492 kb
Host smart-8cf0a4af-e204-4e25-89b9-a9cc209a0f10
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104202874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2104202874
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.4136232407
Short name T1032
Test name
Test status
Simulation time 291292117 ps
CPU time 3.56 seconds
Started Mar 07 01:19:06 PM PST 24
Finished Mar 07 01:19:10 PM PST 24
Peak memory 214184 kb
Host smart-8772a67f-947e-4eff-8535-e3064f899370
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136232407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.4136232407
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1999512650
Short name T167
Test name
Test status
Simulation time 1405350502 ps
CPU time 33.16 seconds
Started Mar 07 01:19:03 PM PST 24
Finished Mar 07 01:19:37 PM PST 24
Peak memory 209484 kb
Host smart-f0622a48-9281-4b3c-8873-548c6d9e2987
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999512650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1999512650
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2857894050
Short name T713
Test name
Test status
Simulation time 42721530 ps
CPU time 0.73 seconds
Started Mar 07 02:47:54 PM PST 24
Finished Mar 07 02:47:56 PM PST 24
Peak memory 206220 kb
Host smart-18a1771d-b64e-4bfb-ab4d-73d0bca7be7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857894050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2857894050
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1154336634
Short name T407
Test name
Test status
Simulation time 502535403 ps
CPU time 13.38 seconds
Started Mar 07 02:47:45 PM PST 24
Finished Mar 07 02:47:58 PM PST 24
Peak memory 215912 kb
Host smart-2b8b4cd8-87b9-44f9-968c-7078349a2da7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1154336634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1154336634
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.4148123768
Short name T28
Test name
Test status
Simulation time 74823838 ps
CPU time 3.28 seconds
Started Mar 07 02:47:44 PM PST 24
Finished Mar 07 02:47:48 PM PST 24
Peak memory 209992 kb
Host smart-5532dbed-33d9-4403-a91c-4692447ec028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148123768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.4148123768
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3229344036
Short name T826
Test name
Test status
Simulation time 512407695 ps
CPU time 2.56 seconds
Started Mar 07 02:47:44 PM PST 24
Finished Mar 07 02:47:46 PM PST 24
Peak memory 207756 kb
Host smart-4673bb34-0699-4cdb-8254-b3c66c3c3410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229344036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3229344036
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1370600477
Short name T102
Test name
Test status
Simulation time 311341529 ps
CPU time 4.01 seconds
Started Mar 07 02:47:48 PM PST 24
Finished Mar 07 02:47:52 PM PST 24
Peak memory 220152 kb
Host smart-3a40d8a5-089e-4a50-929e-730408050ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370600477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1370600477
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3795262463
Short name T785
Test name
Test status
Simulation time 1563429129 ps
CPU time 11.4 seconds
Started Mar 07 02:47:44 PM PST 24
Finished Mar 07 02:47:55 PM PST 24
Peak memory 214464 kb
Host smart-a707cfc4-8e6c-4650-ad2f-f3b2e63c5885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795262463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3795262463
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.428675961
Short name T895
Test name
Test status
Simulation time 47402573 ps
CPU time 2.6 seconds
Started Mar 07 02:47:45 PM PST 24
Finished Mar 07 02:47:47 PM PST 24
Peak memory 220032 kb
Host smart-e7da71d9-85ac-4f36-bc4e-719dc20ed3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428675961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.428675961
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2909206873
Short name T522
Test name
Test status
Simulation time 63672601 ps
CPU time 2.75 seconds
Started Mar 07 02:47:45 PM PST 24
Finished Mar 07 02:47:47 PM PST 24
Peak memory 208096 kb
Host smart-995e4d98-4aa0-47c1-b9ea-b5eaef1000f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909206873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2909206873
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1575256395
Short name T42
Test name
Test status
Simulation time 833723647 ps
CPU time 20.42 seconds
Started Mar 07 02:47:51 PM PST 24
Finished Mar 07 02:48:12 PM PST 24
Peak memory 230444 kb
Host smart-0d51ff37-7ade-45c9-b42f-57eaa8e3448e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575256395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1575256395
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3557967565
Short name T194
Test name
Test status
Simulation time 109277305 ps
CPU time 2.77 seconds
Started Mar 07 02:47:45 PM PST 24
Finished Mar 07 02:47:48 PM PST 24
Peak memory 206700 kb
Host smart-15fddc0f-cb2b-4a3e-bd42-bd552402b7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557967565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3557967565
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1643161671
Short name T728
Test name
Test status
Simulation time 413390060 ps
CPU time 14.79 seconds
Started Mar 07 02:47:46 PM PST 24
Finished Mar 07 02:48:01 PM PST 24
Peak memory 208276 kb
Host smart-8d7c77fa-fd96-42df-a3cf-633b66af8905
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643161671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1643161671
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.528331700
Short name T799
Test name
Test status
Simulation time 61288568 ps
CPU time 3.32 seconds
Started Mar 07 02:47:47 PM PST 24
Finished Mar 07 02:47:50 PM PST 24
Peak memory 208528 kb
Host smart-5d8fa188-f688-4b9f-a553-1a8276967469
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528331700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.528331700
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2586495694
Short name T600
Test name
Test status
Simulation time 33151921 ps
CPU time 2.34 seconds
Started Mar 07 02:47:45 PM PST 24
Finished Mar 07 02:47:47 PM PST 24
Peak memory 206920 kb
Host smart-dae20cc3-853c-4478-afa7-c5ebfa2e3db3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586495694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2586495694
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2913053355
Short name T322
Test name
Test status
Simulation time 61742390 ps
CPU time 1.66 seconds
Started Mar 07 02:47:55 PM PST 24
Finished Mar 07 02:47:57 PM PST 24
Peak memory 209936 kb
Host smart-77c73b1c-1436-468d-93e6-d05b7555660c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913053355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2913053355
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2041594083
Short name T580
Test name
Test status
Simulation time 38476043 ps
CPU time 1.67 seconds
Started Mar 07 02:47:45 PM PST 24
Finished Mar 07 02:47:47 PM PST 24
Peak memory 206724 kb
Host smart-cf2cf460-845d-4d9d-ba63-24b47b4cab07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041594083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2041594083
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.448572705
Short name T703
Test name
Test status
Simulation time 480295045 ps
CPU time 11.94 seconds
Started Mar 07 02:47:46 PM PST 24
Finished Mar 07 02:47:58 PM PST 24
Peak memory 209912 kb
Host smart-d3c248ad-a31b-4fb6-8c9e-3da466b94488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448572705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.448572705
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1119574412
Short name T182
Test name
Test status
Simulation time 52163796 ps
CPU time 2.7 seconds
Started Mar 07 02:47:53 PM PST 24
Finished Mar 07 02:47:56 PM PST 24
Peak memory 209972 kb
Host smart-bcb1b2b9-c002-40f4-8da2-97109ef5431c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119574412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1119574412
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1837983536
Short name T480
Test name
Test status
Simulation time 86864635 ps
CPU time 0.76 seconds
Started Mar 07 02:48:01 PM PST 24
Finished Mar 07 02:48:02 PM PST 24
Peak memory 206168 kb
Host smart-174c1974-42b1-4ab2-98f7-0959bf2e2160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837983536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1837983536
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.34458735
Short name T318
Test name
Test status
Simulation time 74821802 ps
CPU time 2.38 seconds
Started Mar 07 02:47:52 PM PST 24
Finished Mar 07 02:47:54 PM PST 24
Peak memory 214552 kb
Host smart-40db09f0-1d07-41f5-a549-aee6687bd1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34458735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.34458735
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1408890291
Short name T269
Test name
Test status
Simulation time 696789407 ps
CPU time 7.73 seconds
Started Mar 07 02:47:52 PM PST 24
Finished Mar 07 02:48:00 PM PST 24
Peak memory 222744 kb
Host smart-94610091-16dd-4b3b-b17a-2a1ba05ab82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408890291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1408890291
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1736421726
Short name T64
Test name
Test status
Simulation time 297238226 ps
CPU time 3.72 seconds
Started Mar 07 02:47:52 PM PST 24
Finished Mar 07 02:47:57 PM PST 24
Peak memory 209976 kb
Host smart-f02850eb-7bf7-44a4-9471-bb8bfcba2c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736421726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1736421726
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1626528223
Short name T744
Test name
Test status
Simulation time 132152064 ps
CPU time 3.73 seconds
Started Mar 07 02:47:57 PM PST 24
Finished Mar 07 02:48:01 PM PST 24
Peak memory 207224 kb
Host smart-50699b3a-3d70-4883-b801-12c47c3bc549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626528223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1626528223
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.184000255
Short name T106
Test name
Test status
Simulation time 1006964207 ps
CPU time 9.21 seconds
Started Mar 07 02:47:56 PM PST 24
Finished Mar 07 02:48:05 PM PST 24
Peak memory 230880 kb
Host smart-b02759e7-90dc-4621-b588-39b79d7103e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184000255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.184000255
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.4035452319
Short name T830
Test name
Test status
Simulation time 2765626713 ps
CPU time 49.62 seconds
Started Mar 07 02:47:51 PM PST 24
Finished Mar 07 02:48:41 PM PST 24
Peak memory 208256 kb
Host smart-7ed664e7-f202-4b06-b96e-01fc5e4e411b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035452319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.4035452319
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.4125674820
Short name T643
Test name
Test status
Simulation time 142499615 ps
CPU time 3.61 seconds
Started Mar 07 02:47:49 PM PST 24
Finished Mar 07 02:47:53 PM PST 24
Peak memory 206816 kb
Host smart-1a1723e3-bd54-4a7d-85e9-dda5a386b3ed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125674820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.4125674820
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2218594777
Short name T526
Test name
Test status
Simulation time 24337307041 ps
CPU time 57.62 seconds
Started Mar 07 02:47:57 PM PST 24
Finished Mar 07 02:48:55 PM PST 24
Peak memory 208588 kb
Host smart-86fc5df8-d836-4873-b9e6-5ac4b3864866
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218594777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2218594777
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1885838602
Short name T569
Test name
Test status
Simulation time 108021080 ps
CPU time 3.78 seconds
Started Mar 07 02:47:52 PM PST 24
Finished Mar 07 02:47:56 PM PST 24
Peak memory 208740 kb
Host smart-1d7a5e21-6854-443a-a4e5-d87baff49f64
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885838602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1885838602
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.491924256
Short name T595
Test name
Test status
Simulation time 2436377043 ps
CPU time 8.17 seconds
Started Mar 07 02:47:53 PM PST 24
Finished Mar 07 02:48:02 PM PST 24
Peak memory 209084 kb
Host smart-10348905-54a6-4864-a098-b89db74dc2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491924256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.491924256
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3645078529
Short name T636
Test name
Test status
Simulation time 173620372 ps
CPU time 2.4 seconds
Started Mar 07 02:47:52 PM PST 24
Finished Mar 07 02:47:56 PM PST 24
Peak memory 206848 kb
Host smart-0e0f7f32-10ce-429e-96d5-750841ca3b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645078529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3645078529
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3581799150
Short name T757
Test name
Test status
Simulation time 52182504803 ps
CPU time 342.11 seconds
Started Mar 07 02:47:52 PM PST 24
Finished Mar 07 02:53:35 PM PST 24
Peak memory 222744 kb
Host smart-77738a63-c9dd-4e9b-b8f0-4a39321243bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581799150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3581799150
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3661526679
Short name T683
Test name
Test status
Simulation time 629751002 ps
CPU time 5.02 seconds
Started Mar 07 02:48:02 PM PST 24
Finished Mar 07 02:48:07 PM PST 24
Peak memory 208132 kb
Host smart-7af76d53-2b9f-404a-9c4f-5a773fcbac14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661526679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3661526679
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2941491092
Short name T27
Test name
Test status
Simulation time 317118586 ps
CPU time 2.87 seconds
Started Mar 07 02:48:23 PM PST 24
Finished Mar 07 02:48:26 PM PST 24
Peak memory 221860 kb
Host smart-93c605b2-0181-4c81-9d79-95c65182c7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941491092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2941491092
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.431399170
Short name T56
Test name
Test status
Simulation time 82208989 ps
CPU time 1.89 seconds
Started Mar 07 02:48:27 PM PST 24
Finished Mar 07 02:48:30 PM PST 24
Peak memory 207056 kb
Host smart-262e8306-c58f-430c-9d81-6c27244e6b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431399170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.431399170
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2341653857
Short name T734
Test name
Test status
Simulation time 195565530 ps
CPU time 3.37 seconds
Started Mar 07 02:48:25 PM PST 24
Finished Mar 07 02:48:29 PM PST 24
Peak memory 209768 kb
Host smart-82f0da92-bd07-4dcc-92b8-e6d5e1cc19f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341653857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2341653857
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3172327369
Short name T561
Test name
Test status
Simulation time 141283960 ps
CPU time 3.91 seconds
Started Mar 07 02:48:25 PM PST 24
Finished Mar 07 02:48:29 PM PST 24
Peak memory 220140 kb
Host smart-b70dcb39-32bb-47db-8d24-630b17a4a0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172327369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3172327369
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3068407125
Short name T190
Test name
Test status
Simulation time 322311629 ps
CPU time 7.2 seconds
Started Mar 07 02:48:23 PM PST 24
Finished Mar 07 02:48:30 PM PST 24
Peak memory 209240 kb
Host smart-6a46c75c-6289-4c78-8b13-0100c218cdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068407125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3068407125
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1180801426
Short name T516
Test name
Test status
Simulation time 649731893 ps
CPU time 3.86 seconds
Started Mar 07 02:48:23 PM PST 24
Finished Mar 07 02:48:28 PM PST 24
Peak memory 206308 kb
Host smart-c81afa59-e292-4e52-99d7-1dbda163db7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180801426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1180801426
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3589867093
Short name T399
Test name
Test status
Simulation time 45625941 ps
CPU time 2.58 seconds
Started Mar 07 02:48:22 PM PST 24
Finished Mar 07 02:48:25 PM PST 24
Peak memory 206872 kb
Host smart-85acca37-cbf3-4b85-87fa-19b00ea00038
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589867093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3589867093
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.39249646
Short name T567
Test name
Test status
Simulation time 817938052 ps
CPU time 6.09 seconds
Started Mar 07 02:48:25 PM PST 24
Finished Mar 07 02:48:31 PM PST 24
Peak memory 208932 kb
Host smart-25e8a5d7-5d39-4017-830f-d1d5e5b52acd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39249646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.39249646
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.4141534893
Short name T627
Test name
Test status
Simulation time 116467149 ps
CPU time 2.7 seconds
Started Mar 07 02:48:27 PM PST 24
Finished Mar 07 02:48:30 PM PST 24
Peak memory 208492 kb
Host smart-58b02309-5725-4e34-868e-350ee2f5c90a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141534893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.4141534893
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3798694894
Short name T802
Test name
Test status
Simulation time 145470164 ps
CPU time 2.76 seconds
Started Mar 07 02:48:22 PM PST 24
Finished Mar 07 02:48:25 PM PST 24
Peak memory 218492 kb
Host smart-4a73c97e-3091-43f3-bf7c-b7f3b4406535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798694894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3798694894
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1562882290
Short name T754
Test name
Test status
Simulation time 142942365 ps
CPU time 3.53 seconds
Started Mar 07 02:48:24 PM PST 24
Finished Mar 07 02:48:28 PM PST 24
Peak memory 208804 kb
Host smart-3d76b4c6-2d78-40c7-b5a5-51c85a12afda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562882290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1562882290
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2720836418
Short name T613
Test name
Test status
Simulation time 56134501 ps
CPU time 2.82 seconds
Started Mar 07 02:48:25 PM PST 24
Finished Mar 07 02:48:28 PM PST 24
Peak memory 208044 kb
Host smart-e0a008e5-1029-4bd1-914a-e72f87aa25b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720836418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2720836418
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.701804911
Short name T880
Test name
Test status
Simulation time 106760800 ps
CPU time 3.54 seconds
Started Mar 07 02:48:24 PM PST 24
Finished Mar 07 02:48:27 PM PST 24
Peak memory 210932 kb
Host smart-a0ef9418-de56-426c-9496-1f0d3f6052f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701804911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.701804911
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3822026203
Short name T448
Test name
Test status
Simulation time 21597062 ps
CPU time 0.84 seconds
Started Mar 07 02:48:34 PM PST 24
Finished Mar 07 02:48:35 PM PST 24
Peak memory 206132 kb
Host smart-541a5b30-dc3b-41fb-b99b-2499cc786ab8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822026203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3822026203
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1712855423
Short name T151
Test name
Test status
Simulation time 470013153 ps
CPU time 6.61 seconds
Started Mar 07 02:48:24 PM PST 24
Finished Mar 07 02:48:31 PM PST 24
Peak memory 215232 kb
Host smart-4d3bc0bd-5cb2-4b2f-9861-156ca99878fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1712855423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1712855423
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.4124106055
Short name T606
Test name
Test status
Simulation time 113112111 ps
CPU time 4.54 seconds
Started Mar 07 02:48:27 PM PST 24
Finished Mar 07 02:48:31 PM PST 24
Peak memory 209164 kb
Host smart-85880af5-b85e-4859-b2da-d2b16de43ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124106055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.4124106055
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1789362774
Short name T429
Test name
Test status
Simulation time 78007106 ps
CPU time 1.79 seconds
Started Mar 07 02:48:26 PM PST 24
Finished Mar 07 02:48:28 PM PST 24
Peak memory 207096 kb
Host smart-20456a46-fa1b-4b61-a36d-06bed8cc131d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789362774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1789362774
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.327683355
Short name T100
Test name
Test status
Simulation time 103537096 ps
CPU time 4.66 seconds
Started Mar 07 02:48:28 PM PST 24
Finished Mar 07 02:48:33 PM PST 24
Peak memory 210260 kb
Host smart-bd3a4442-f610-42ea-bd61-b21d0ff3cea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327683355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.327683355
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.61102373
Short name T221
Test name
Test status
Simulation time 1598318216 ps
CPU time 13.43 seconds
Started Mar 07 02:48:25 PM PST 24
Finished Mar 07 02:48:39 PM PST 24
Peak memory 222692 kb
Host smart-5a52c6a4-f920-4e64-8af9-5330acbe4a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61102373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.61102373
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.485746444
Short name T584
Test name
Test status
Simulation time 828465364 ps
CPU time 9.01 seconds
Started Mar 07 02:48:22 PM PST 24
Finished Mar 07 02:48:31 PM PST 24
Peak memory 214532 kb
Host smart-aa012b54-d0fa-4e53-98aa-2adb55308862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485746444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.485746444
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1438687579
Short name T464
Test name
Test status
Simulation time 21057342 ps
CPU time 1.9 seconds
Started Mar 07 02:48:23 PM PST 24
Finished Mar 07 02:48:26 PM PST 24
Peak memory 206732 kb
Host smart-10651efd-93d5-4136-a45e-6a2796761974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438687579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1438687579
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2250436390
Short name T507
Test name
Test status
Simulation time 60290496 ps
CPU time 3.05 seconds
Started Mar 07 02:48:26 PM PST 24
Finished Mar 07 02:48:30 PM PST 24
Peak memory 208740 kb
Host smart-400cfbda-cf08-425d-a049-4a680ee3e819
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250436390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2250436390
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1017766071
Short name T457
Test name
Test status
Simulation time 575141746 ps
CPU time 4.04 seconds
Started Mar 07 02:48:32 PM PST 24
Finished Mar 07 02:48:36 PM PST 24
Peak memory 206668 kb
Host smart-43fb3093-f235-4909-8a09-fcc05e3d1370
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017766071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1017766071
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2131664738
Short name T694
Test name
Test status
Simulation time 13041203984 ps
CPU time 22.66 seconds
Started Mar 07 02:48:23 PM PST 24
Finished Mar 07 02:48:45 PM PST 24
Peak memory 208224 kb
Host smart-d957d516-5b4c-4065-b667-a331135efb58
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131664738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2131664738
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1888423751
Short name T831
Test name
Test status
Simulation time 1006622229 ps
CPU time 3.83 seconds
Started Mar 07 02:48:33 PM PST 24
Finished Mar 07 02:48:37 PM PST 24
Peak memory 214448 kb
Host smart-a20e8c25-c569-42b8-9943-bdf8e851724f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888423751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1888423751
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3381382949
Short name T493
Test name
Test status
Simulation time 36772087 ps
CPU time 2.31 seconds
Started Mar 07 02:48:32 PM PST 24
Finished Mar 07 02:48:34 PM PST 24
Peak memory 207200 kb
Host smart-21ab1e86-b7da-40e7-a018-78278f19dc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381382949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3381382949
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2113470525
Short name T738
Test name
Test status
Simulation time 1566595247 ps
CPU time 7.97 seconds
Started Mar 07 02:48:27 PM PST 24
Finished Mar 07 02:48:36 PM PST 24
Peak memory 209356 kb
Host smart-a44cc93e-934c-488c-9ef9-6f47f5919d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113470525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2113470525
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1321603159
Short name T729
Test name
Test status
Simulation time 357006024 ps
CPU time 4.28 seconds
Started Mar 07 02:48:31 PM PST 24
Finished Mar 07 02:48:35 PM PST 24
Peak memory 210244 kb
Host smart-a23b7ce4-ad57-4d07-b4ff-d023f1f0f62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321603159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1321603159
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.498393255
Short name T680
Test name
Test status
Simulation time 68269626 ps
CPU time 0.77 seconds
Started Mar 07 02:48:40 PM PST 24
Finished Mar 07 02:48:41 PM PST 24
Peak memory 206180 kb
Host smart-455d9af6-6d0c-4600-8808-871c71a2509c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498393255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.498393255
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1838563079
Short name T228
Test name
Test status
Simulation time 378101758 ps
CPU time 4.12 seconds
Started Mar 07 02:48:33 PM PST 24
Finished Mar 07 02:48:37 PM PST 24
Peak memory 210048 kb
Host smart-d35eb541-52a7-4da7-bbb7-1775a5ee1d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838563079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1838563079
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1251471481
Short name T488
Test name
Test status
Simulation time 98254909 ps
CPU time 2.26 seconds
Started Mar 07 02:48:30 PM PST 24
Finished Mar 07 02:48:32 PM PST 24
Peak memory 206864 kb
Host smart-f7fd0fb5-c34c-42be-95da-5289a93b5705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251471481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1251471481
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3674095
Short name T376
Test name
Test status
Simulation time 123058899 ps
CPU time 4.93 seconds
Started Mar 07 02:48:32 PM PST 24
Finished Mar 07 02:48:37 PM PST 24
Peak memory 222576 kb
Host smart-64f5739e-5d7f-483e-9044-9edef0e2b586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3674095
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1596383994
Short name T319
Test name
Test status
Simulation time 643708845 ps
CPU time 9.43 seconds
Started Mar 07 02:48:36 PM PST 24
Finished Mar 07 02:48:46 PM PST 24
Peak memory 211620 kb
Host smart-d2d545c0-6229-47f7-ac52-bab4150e4b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596383994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1596383994
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.608002043
Short name T723
Test name
Test status
Simulation time 5478497901 ps
CPU time 49.73 seconds
Started Mar 07 02:48:32 PM PST 24
Finished Mar 07 02:49:21 PM PST 24
Peak memory 209164 kb
Host smart-b80456c1-9448-4ed8-9670-c1e203295ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608002043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.608002043
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2773424989
Short name T851
Test name
Test status
Simulation time 1473364330 ps
CPU time 3.81 seconds
Started Mar 07 02:48:33 PM PST 24
Finished Mar 07 02:48:37 PM PST 24
Peak memory 206588 kb
Host smart-ecd235c7-7d4a-466d-a891-cf9278ff5af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773424989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2773424989
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.604128502
Short name T762
Test name
Test status
Simulation time 276742942 ps
CPU time 3.4 seconds
Started Mar 07 02:48:32 PM PST 24
Finished Mar 07 02:48:35 PM PST 24
Peak memory 208708 kb
Host smart-fb1261a0-7182-4807-a1da-43f54546b1d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604128502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.604128502
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3285730782
Short name T879
Test name
Test status
Simulation time 98127393 ps
CPU time 2.93 seconds
Started Mar 07 02:48:40 PM PST 24
Finished Mar 07 02:48:43 PM PST 24
Peak memory 206904 kb
Host smart-8b524519-938e-479d-aefc-17914b0726b0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285730782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3285730782
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1624661993
Short name T758
Test name
Test status
Simulation time 98247921 ps
CPU time 2.86 seconds
Started Mar 07 02:48:32 PM PST 24
Finished Mar 07 02:48:35 PM PST 24
Peak memory 206828 kb
Host smart-3e4568d7-a17b-4e22-b3ff-cbf16f266571
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624661993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1624661993
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.4010985839
Short name T82
Test name
Test status
Simulation time 382216127 ps
CPU time 2.75 seconds
Started Mar 07 02:48:29 PM PST 24
Finished Mar 07 02:48:32 PM PST 24
Peak memory 222656 kb
Host smart-cb74dffe-6b2c-485f-a6ae-ca0671b50609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010985839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.4010985839
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1127836507
Short name T489
Test name
Test status
Simulation time 23646367 ps
CPU time 1.83 seconds
Started Mar 07 02:48:31 PM PST 24
Finished Mar 07 02:48:33 PM PST 24
Peak memory 206900 kb
Host smart-46dbc56a-f756-4fd1-ba93-2209c40edcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127836507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1127836507
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.396140673
Short name T229
Test name
Test status
Simulation time 5808957989 ps
CPU time 37.38 seconds
Started Mar 07 02:48:31 PM PST 24
Finished Mar 07 02:49:09 PM PST 24
Peak memory 222784 kb
Host smart-33f5780d-8846-44f9-9f2f-9c46b7f8d2cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396140673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.396140673
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2176281773
Short name T84
Test name
Test status
Simulation time 192260751 ps
CPU time 7.65 seconds
Started Mar 07 02:48:36 PM PST 24
Finished Mar 07 02:48:44 PM PST 24
Peak memory 214520 kb
Host smart-d335b282-d588-437c-b2c6-1e619471e75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176281773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2176281773
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1579217506
Short name T62
Test name
Test status
Simulation time 158911002 ps
CPU time 3.32 seconds
Started Mar 07 02:48:32 PM PST 24
Finished Mar 07 02:48:35 PM PST 24
Peak memory 209996 kb
Host smart-fe9f0d63-9232-4c4c-ae6d-0ce4e0efa4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579217506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1579217506
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.98674402
Short name T105
Test name
Test status
Simulation time 15967046 ps
CPU time 0.79 seconds
Started Mar 07 02:48:37 PM PST 24
Finished Mar 07 02:48:38 PM PST 24
Peak memory 206236 kb
Host smart-2ab87c6b-3f9b-4c77-a314-56798148a5ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98674402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.98674402
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2249790363
Short name T419
Test name
Test status
Simulation time 210713333 ps
CPU time 11.04 seconds
Started Mar 07 02:48:37 PM PST 24
Finished Mar 07 02:48:48 PM PST 24
Peak memory 215520 kb
Host smart-4ede758d-4dad-45b4-b618-39500e0356ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2249790363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2249790363
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1414828318
Short name T533
Test name
Test status
Simulation time 162706817 ps
CPU time 2.48 seconds
Started Mar 07 02:48:39 PM PST 24
Finished Mar 07 02:48:41 PM PST 24
Peak memory 207628 kb
Host smart-d6da0979-d00c-4fc8-aade-72a8a7c71682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414828318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1414828318
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3800012463
Short name T355
Test name
Test status
Simulation time 213544300 ps
CPU time 6.6 seconds
Started Mar 07 02:48:36 PM PST 24
Finished Mar 07 02:48:43 PM PST 24
Peak memory 214480 kb
Host smart-5b416095-c00d-41b3-a48b-e74ef561e45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800012463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3800012463
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3423273473
Short name T342
Test name
Test status
Simulation time 203161627 ps
CPU time 7.89 seconds
Started Mar 07 02:48:40 PM PST 24
Finished Mar 07 02:48:48 PM PST 24
Peak memory 221508 kb
Host smart-d7dbfee5-9c1e-4d7d-a25d-7533506f4fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423273473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3423273473
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.4205537347
Short name T733
Test name
Test status
Simulation time 457801549 ps
CPU time 4.98 seconds
Started Mar 07 02:48:37 PM PST 24
Finished Mar 07 02:48:42 PM PST 24
Peak memory 208020 kb
Host smart-5bb8d20f-72bd-4730-81c8-8144d36a4062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205537347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.4205537347
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.806951583
Short name T264
Test name
Test status
Simulation time 11625903145 ps
CPU time 42.35 seconds
Started Mar 07 02:48:31 PM PST 24
Finished Mar 07 02:49:13 PM PST 24
Peak memory 209424 kb
Host smart-e0d14008-ec7f-407a-8cda-b1bdf026c276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806951583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.806951583
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3329159867
Short name T590
Test name
Test status
Simulation time 610050569 ps
CPU time 2.58 seconds
Started Mar 07 02:48:40 PM PST 24
Finished Mar 07 02:48:42 PM PST 24
Peak memory 206884 kb
Host smart-c5e7a241-35ab-4978-a8cc-379e20af68c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329159867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3329159867
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.485528033
Short name T781
Test name
Test status
Simulation time 102734612 ps
CPU time 4.42 seconds
Started Mar 07 02:48:31 PM PST 24
Finished Mar 07 02:48:35 PM PST 24
Peak memory 208572 kb
Host smart-0eb2a245-c8bd-46b5-93d4-9355d36677a7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485528033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.485528033
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2511840247
Short name T850
Test name
Test status
Simulation time 61404560 ps
CPU time 3.11 seconds
Started Mar 07 02:48:33 PM PST 24
Finished Mar 07 02:48:36 PM PST 24
Peak memory 208852 kb
Host smart-82988ed2-6060-4596-82ae-aeb7f6dec218
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511840247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2511840247
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.135128172
Short name T534
Test name
Test status
Simulation time 1168617280 ps
CPU time 26.35 seconds
Started Mar 07 02:48:38 PM PST 24
Finished Mar 07 02:49:05 PM PST 24
Peak memory 218108 kb
Host smart-ecdc547a-944c-4039-9914-4973d801faee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135128172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.135128172
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3572979383
Short name T864
Test name
Test status
Simulation time 55371840 ps
CPU time 2.96 seconds
Started Mar 07 02:48:33 PM PST 24
Finished Mar 07 02:48:36 PM PST 24
Peak memory 206848 kb
Host smart-3dde0c18-6f39-4652-be4e-df0b06c51778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572979383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3572979383
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2694756143
Short name T233
Test name
Test status
Simulation time 2950802464 ps
CPU time 20.24 seconds
Started Mar 07 02:48:40 PM PST 24
Finished Mar 07 02:49:01 PM PST 24
Peak memory 220108 kb
Host smart-3c7ff9d7-6254-4a5b-8b34-972bda8d6448
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694756143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2694756143
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2983129109
Short name T409
Test name
Test status
Simulation time 90506414 ps
CPU time 4.2 seconds
Started Mar 07 02:48:37 PM PST 24
Finished Mar 07 02:48:42 PM PST 24
Peak memory 208180 kb
Host smart-70041755-0fde-4410-9cb2-62b38ed2ed8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983129109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2983129109
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2503552844
Short name T739
Test name
Test status
Simulation time 18656386 ps
CPU time 0.77 seconds
Started Mar 07 02:48:46 PM PST 24
Finished Mar 07 02:48:47 PM PST 24
Peak memory 206084 kb
Host smart-4183ca94-e97f-4d7d-9308-ca89772097bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503552844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2503552844
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2651120509
Short name T885
Test name
Test status
Simulation time 49460520 ps
CPU time 2.19 seconds
Started Mar 07 02:48:47 PM PST 24
Finished Mar 07 02:48:49 PM PST 24
Peak memory 218428 kb
Host smart-e7188916-6712-4c71-8253-3018d64e895d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651120509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2651120509
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3111029303
Short name T72
Test name
Test status
Simulation time 88004200 ps
CPU time 3.59 seconds
Started Mar 07 02:48:38 PM PST 24
Finished Mar 07 02:48:41 PM PST 24
Peak memory 218252 kb
Host smart-c752ffea-86d8-4d83-be92-6935e931e720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111029303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3111029303
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2358466289
Short name T761
Test name
Test status
Simulation time 321012168 ps
CPU time 4.15 seconds
Started Mar 07 02:48:35 PM PST 24
Finished Mar 07 02:48:39 PM PST 24
Peak memory 214560 kb
Host smart-300b3d7c-aa67-4162-a5c8-21db49b68e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358466289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2358466289
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.97333062
Short name T689
Test name
Test status
Simulation time 44859366 ps
CPU time 3.18 seconds
Started Mar 07 02:48:38 PM PST 24
Finished Mar 07 02:48:41 PM PST 24
Peak memory 214380 kb
Host smart-c2fef3b7-64dd-4cd8-b640-1c2fd99dc3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97333062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.97333062
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1301228091
Short name T469
Test name
Test status
Simulation time 285906628 ps
CPU time 3.85 seconds
Started Mar 07 02:48:40 PM PST 24
Finished Mar 07 02:48:44 PM PST 24
Peak memory 220516 kb
Host smart-e4b2f356-2105-4a78-bd08-981c370d6128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301228091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1301228091
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2281815853
Short name T839
Test name
Test status
Simulation time 501933538 ps
CPU time 5.12 seconds
Started Mar 07 02:48:36 PM PST 24
Finished Mar 07 02:48:42 PM PST 24
Peak memory 208104 kb
Host smart-2bb909f4-95d1-4c2a-a3a6-2ae46796674f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281815853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2281815853
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.97547780
Short name T679
Test name
Test status
Simulation time 461941521 ps
CPU time 3.12 seconds
Started Mar 07 02:48:38 PM PST 24
Finished Mar 07 02:48:41 PM PST 24
Peak memory 208624 kb
Host smart-a30b1e7a-dffc-4a17-9360-c507b91ebba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97547780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.97547780
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.193800284
Short name T840
Test name
Test status
Simulation time 82058103 ps
CPU time 2.85 seconds
Started Mar 07 02:48:38 PM PST 24
Finished Mar 07 02:48:41 PM PST 24
Peak memory 206872 kb
Host smart-8a422c48-ec9d-41d6-b759-6d7fbeff6647
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193800284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.193800284
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.4173235597
Short name T500
Test name
Test status
Simulation time 66265995 ps
CPU time 2.6 seconds
Started Mar 07 02:48:40 PM PST 24
Finished Mar 07 02:48:43 PM PST 24
Peak memory 208784 kb
Host smart-564a5035-ad69-4aec-b7e9-31b11e75566e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173235597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.4173235597
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2395386172
Short name T743
Test name
Test status
Simulation time 100443335 ps
CPU time 2.79 seconds
Started Mar 07 02:48:41 PM PST 24
Finished Mar 07 02:48:44 PM PST 24
Peak memory 208924 kb
Host smart-275139d3-ad58-46fc-acfa-2249a3d057ab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395386172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2395386172
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2755619725
Short name T108
Test name
Test status
Simulation time 42357218 ps
CPU time 2.76 seconds
Started Mar 07 02:48:46 PM PST 24
Finished Mar 07 02:48:49 PM PST 24
Peak memory 209184 kb
Host smart-43754189-df2f-4246-ad08-684eda84ce39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755619725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2755619725
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1339438454
Short name T89
Test name
Test status
Simulation time 73341928 ps
CPU time 2.36 seconds
Started Mar 07 02:48:38 PM PST 24
Finished Mar 07 02:48:41 PM PST 24
Peak memory 207116 kb
Host smart-fbd9f350-5252-4854-bb93-61abc60f9f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339438454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1339438454
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.125406482
Short name T309
Test name
Test status
Simulation time 885494561 ps
CPU time 12.78 seconds
Started Mar 07 02:48:48 PM PST 24
Finished Mar 07 02:49:01 PM PST 24
Peak memory 216032 kb
Host smart-32220621-3759-4048-bc67-babbcf7217ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125406482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.125406482
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.783584333
Short name T487
Test name
Test status
Simulation time 180417760 ps
CPU time 3.47 seconds
Started Mar 07 02:48:39 PM PST 24
Finished Mar 07 02:48:42 PM PST 24
Peak memory 207468 kb
Host smart-6dd266b2-f2a3-460f-89d8-8dbd69f08465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783584333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.783584333
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2717330999
Short name T806
Test name
Test status
Simulation time 46422482 ps
CPU time 2.07 seconds
Started Mar 07 02:48:46 PM PST 24
Finished Mar 07 02:48:48 PM PST 24
Peak memory 209700 kb
Host smart-785dd249-dc72-4381-baa4-926202b18971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717330999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2717330999
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.4208792453
Short name T755
Test name
Test status
Simulation time 9688249 ps
CPU time 0.85 seconds
Started Mar 07 02:48:49 PM PST 24
Finished Mar 07 02:48:50 PM PST 24
Peak memory 206120 kb
Host smart-3b518eb0-9b39-4ca4-8e0b-aaf191a7aeff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208792453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.4208792453
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3564020886
Short name T303
Test name
Test status
Simulation time 56370703 ps
CPU time 4.5 seconds
Started Mar 07 02:48:45 PM PST 24
Finished Mar 07 02:48:49 PM PST 24
Peak memory 215620 kb
Host smart-d27d1fa9-c2d5-467c-9728-5c335b9becc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3564020886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3564020886
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.4100615775
Short name T776
Test name
Test status
Simulation time 602722480 ps
CPU time 3.63 seconds
Started Mar 07 02:48:46 PM PST 24
Finished Mar 07 02:48:50 PM PST 24
Peak memory 208468 kb
Host smart-1c22aa4d-115b-4edc-bd23-7c1adf033a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100615775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.4100615775
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.635769223
Short name T301
Test name
Test status
Simulation time 334023739 ps
CPU time 4.25 seconds
Started Mar 07 02:48:46 PM PST 24
Finished Mar 07 02:48:50 PM PST 24
Peak memory 209564 kb
Host smart-442ffbd4-150e-4677-8aa9-91450fb67cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635769223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.635769223
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2112742562
Short name T741
Test name
Test status
Simulation time 82361170 ps
CPU time 2.61 seconds
Started Mar 07 02:48:46 PM PST 24
Finished Mar 07 02:48:49 PM PST 24
Peak memory 219008 kb
Host smart-c501437c-6074-4241-a34d-48782edf56b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112742562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2112742562
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3949423052
Short name T675
Test name
Test status
Simulation time 789539744 ps
CPU time 8.75 seconds
Started Mar 07 02:48:46 PM PST 24
Finished Mar 07 02:48:55 PM PST 24
Peak memory 207588 kb
Host smart-0339aaa7-aef5-4cc3-aa61-75e0329620e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949423052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3949423052
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3394204059
Short name T433
Test name
Test status
Simulation time 317882180 ps
CPU time 2.89 seconds
Started Mar 07 02:48:46 PM PST 24
Finished Mar 07 02:48:49 PM PST 24
Peak memory 206780 kb
Host smart-6a5eb847-df3b-4c27-98c9-4963c38e3b9a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394204059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3394204059
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.762333482
Short name T503
Test name
Test status
Simulation time 233564385 ps
CPU time 3.02 seconds
Started Mar 07 02:48:48 PM PST 24
Finished Mar 07 02:48:51 PM PST 24
Peak memory 207932 kb
Host smart-14e6f107-7b42-4b63-8b79-da94124f67fe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762333482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.762333482
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2453475174
Short name T345
Test name
Test status
Simulation time 65301517 ps
CPU time 1.63 seconds
Started Mar 07 02:48:46 PM PST 24
Finished Mar 07 02:48:48 PM PST 24
Peak memory 214520 kb
Host smart-e3a2cd99-361d-48bf-8afd-d08752cf3f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453475174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2453475174
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.144729524
Short name T394
Test name
Test status
Simulation time 627381313 ps
CPU time 18.07 seconds
Started Mar 07 02:48:49 PM PST 24
Finished Mar 07 02:49:07 PM PST 24
Peak memory 207912 kb
Host smart-87ea9323-4541-4b11-a272-33c64e7e2c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144729524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.144729524
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1286521826
Short name T736
Test name
Test status
Simulation time 2817187227 ps
CPU time 28.52 seconds
Started Mar 07 02:48:45 PM PST 24
Finished Mar 07 02:49:14 PM PST 24
Peak memory 220780 kb
Host smart-0a857f83-f426-41e5-b90f-9c9704ca9d2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286521826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1286521826
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2917402558
Short name T875
Test name
Test status
Simulation time 263625080 ps
CPU time 6.28 seconds
Started Mar 07 02:48:46 PM PST 24
Finished Mar 07 02:48:52 PM PST 24
Peak memory 219564 kb
Host smart-1d5c5289-a7e4-4d34-9896-03003ba8ca83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917402558 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2917402558
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2291993765
Short name T324
Test name
Test status
Simulation time 258873743 ps
CPU time 6.41 seconds
Started Mar 07 02:48:47 PM PST 24
Finished Mar 07 02:48:53 PM PST 24
Peak memory 210072 kb
Host smart-6a3875f1-5d49-4eef-8d42-da02f5be7574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291993765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2291993765
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2953688629
Short name T188
Test name
Test status
Simulation time 573280418 ps
CPU time 3.56 seconds
Started Mar 07 02:48:47 PM PST 24
Finished Mar 07 02:48:51 PM PST 24
Peak memory 210308 kb
Host smart-33bd0854-8c05-4cb0-bb85-817f96cb312f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953688629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2953688629
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2005901208
Short name T104
Test name
Test status
Simulation time 36047386 ps
CPU time 0.86 seconds
Started Mar 07 02:48:51 PM PST 24
Finished Mar 07 02:48:53 PM PST 24
Peak memory 206204 kb
Host smart-42799b97-4e2f-4529-8fce-8a44a313646d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005901208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2005901208
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1116512243
Short name T639
Test name
Test status
Simulation time 508520793 ps
CPU time 12.75 seconds
Started Mar 07 02:48:48 PM PST 24
Finished Mar 07 02:49:01 PM PST 24
Peak memory 222160 kb
Host smart-0ac8f0dd-6ccc-4379-a392-039d6968497b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116512243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1116512243
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.858878641
Short name T49
Test name
Test status
Simulation time 1924134686 ps
CPU time 11.11 seconds
Started Mar 07 02:48:52 PM PST 24
Finished Mar 07 02:49:03 PM PST 24
Peak memory 208588 kb
Host smart-f567eacf-3b36-4382-b241-6c1ebd04d5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858878641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.858878641
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_random.1427080308
Short name T677
Test name
Test status
Simulation time 28008593 ps
CPU time 2.13 seconds
Started Mar 07 02:48:46 PM PST 24
Finished Mar 07 02:48:49 PM PST 24
Peak memory 207340 kb
Host smart-c24556e8-37ac-4461-90bb-4f9b9bbd6a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427080308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1427080308
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.828630708
Short name T248
Test name
Test status
Simulation time 233295859 ps
CPU time 6.4 seconds
Started Mar 07 02:48:47 PM PST 24
Finished Mar 07 02:48:54 PM PST 24
Peak memory 208816 kb
Host smart-d348caf5-200e-4d76-80d6-bbd932e11bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828630708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.828630708
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3329672769
Short name T859
Test name
Test status
Simulation time 411160041 ps
CPU time 5.08 seconds
Started Mar 07 02:48:49 PM PST 24
Finished Mar 07 02:48:55 PM PST 24
Peak memory 208572 kb
Host smart-4165309b-3bfa-4846-b4e5-e26ba1aada85
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329672769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3329672769
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3109527564
Short name T111
Test name
Test status
Simulation time 232640945 ps
CPU time 3.16 seconds
Started Mar 07 02:48:45 PM PST 24
Finished Mar 07 02:48:48 PM PST 24
Peak memory 206800 kb
Host smart-64451b1d-3b7c-4b87-afdd-f6650a2ac95e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109527564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3109527564
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.810921749
Short name T275
Test name
Test status
Simulation time 36792958 ps
CPU time 2.57 seconds
Started Mar 07 02:48:47 PM PST 24
Finished Mar 07 02:48:50 PM PST 24
Peak memory 208624 kb
Host smart-98800d58-f9b9-4370-8aa1-3fea27993f46
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810921749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.810921749
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2726869685
Short name T291
Test name
Test status
Simulation time 367350535 ps
CPU time 5.09 seconds
Started Mar 07 02:48:48 PM PST 24
Finished Mar 07 02:48:53 PM PST 24
Peak memory 208544 kb
Host smart-20356a0d-f60a-43c4-a5e8-f6d9a0a9bada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726869685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2726869685
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2393171362
Short name T866
Test name
Test status
Simulation time 8502456391 ps
CPU time 35.22 seconds
Started Mar 07 02:48:45 PM PST 24
Finished Mar 07 02:49:20 PM PST 24
Peak memory 208612 kb
Host smart-96c21ab3-d6bb-48f0-9dda-da025e973849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393171362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2393171362
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3720265277
Short name T565
Test name
Test status
Simulation time 283958077 ps
CPU time 2.36 seconds
Started Mar 07 02:48:46 PM PST 24
Finished Mar 07 02:48:49 PM PST 24
Peak memory 207556 kb
Host smart-d827d963-96ab-4b91-b249-7b7a2959356b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720265277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3720265277
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2080466225
Short name T828
Test name
Test status
Simulation time 432236575 ps
CPU time 3.35 seconds
Started Mar 07 02:48:50 PM PST 24
Finished Mar 07 02:48:53 PM PST 24
Peak memory 210976 kb
Host smart-2b12f378-6297-40cf-9742-bc3f1b2280ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080466225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2080466225
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.908319597
Short name T724
Test name
Test status
Simulation time 10723287 ps
CPU time 0.73 seconds
Started Mar 07 02:48:54 PM PST 24
Finished Mar 07 02:48:55 PM PST 24
Peak memory 206172 kb
Host smart-79dd56b5-db67-403d-9c0b-7ac6a05e1c9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908319597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.908319597
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3947372774
Short name T415
Test name
Test status
Simulation time 115907792 ps
CPU time 4.17 seconds
Started Mar 07 02:48:50 PM PST 24
Finished Mar 07 02:48:55 PM PST 24
Peak memory 214492 kb
Host smart-0a715e09-00ba-4d07-bd0e-334d5e3f2c03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3947372774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3947372774
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1910348828
Short name T29
Test name
Test status
Simulation time 229510955 ps
CPU time 1.99 seconds
Started Mar 07 02:48:53 PM PST 24
Finished Mar 07 02:48:55 PM PST 24
Peak memory 209592 kb
Host smart-7173fb22-60b6-48a7-9f57-4ae37e4ebf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910348828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1910348828
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3202530875
Short name T353
Test name
Test status
Simulation time 73029563 ps
CPU time 2.84 seconds
Started Mar 07 02:48:51 PM PST 24
Finished Mar 07 02:48:54 PM PST 24
Peak memory 208024 kb
Host smart-471f4b1d-e6b1-49fb-a3ff-58751c52197c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202530875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3202530875
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3770674076
Short name T367
Test name
Test status
Simulation time 282753516 ps
CPU time 3.72 seconds
Started Mar 07 02:48:58 PM PST 24
Finished Mar 07 02:49:03 PM PST 24
Peak memory 209152 kb
Host smart-43913ce9-6dc0-444a-91ab-f9a91664e534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770674076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3770674076
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3569930970
Short name T629
Test name
Test status
Simulation time 993586288 ps
CPU time 4.27 seconds
Started Mar 07 02:48:52 PM PST 24
Finished Mar 07 02:48:56 PM PST 24
Peak memory 209924 kb
Host smart-d04eabcc-cb37-48a6-b6ef-6fd9635d2538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569930970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3569930970
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3007981351
Short name T688
Test name
Test status
Simulation time 247717603 ps
CPU time 5.62 seconds
Started Mar 07 02:48:52 PM PST 24
Finished Mar 07 02:48:58 PM PST 24
Peak memory 209384 kb
Host smart-69d16ec3-f1db-4b3b-92eb-c125a6746598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007981351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3007981351
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.5731633
Short name T389
Test name
Test status
Simulation time 6434414674 ps
CPU time 11.76 seconds
Started Mar 07 02:48:53 PM PST 24
Finished Mar 07 02:49:05 PM PST 24
Peak memory 208728 kb
Host smart-445ea8c8-4f5e-4508-87b1-3d9fb4f61ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5731633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.5731633
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1024640589
Short name T247
Test name
Test status
Simulation time 119461246 ps
CPU time 2.37 seconds
Started Mar 07 02:48:51 PM PST 24
Finished Mar 07 02:48:54 PM PST 24
Peak memory 206856 kb
Host smart-e285b7da-4f75-4c2f-b85e-caed91a76857
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024640589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1024640589
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1255523318
Short name T289
Test name
Test status
Simulation time 383476191 ps
CPU time 7.56 seconds
Started Mar 07 02:48:50 PM PST 24
Finished Mar 07 02:48:58 PM PST 24
Peak memory 208444 kb
Host smart-dae64787-6bce-4a06-abc8-6fd0f4178bba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255523318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1255523318
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2143085891
Short name T650
Test name
Test status
Simulation time 436247881 ps
CPU time 3.52 seconds
Started Mar 07 02:48:59 PM PST 24
Finished Mar 07 02:49:04 PM PST 24
Peak memory 209008 kb
Host smart-7ebcf633-e129-475a-974c-e70e7b65bd4c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143085891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2143085891
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2576171439
Short name T4
Test name
Test status
Simulation time 92812428 ps
CPU time 2.33 seconds
Started Mar 07 02:49:00 PM PST 24
Finished Mar 07 02:49:03 PM PST 24
Peak memory 208424 kb
Host smart-fcf259f6-bced-491c-b1a1-b8ce44d11323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576171439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2576171439
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2455693587
Short name T609
Test name
Test status
Simulation time 559333736 ps
CPU time 11.32 seconds
Started Mar 07 02:48:51 PM PST 24
Finished Mar 07 02:49:02 PM PST 24
Peak memory 208272 kb
Host smart-0413c7ec-be42-41c8-b9ca-40a90d672eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455693587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2455693587
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1688189331
Short name T660
Test name
Test status
Simulation time 23630926148 ps
CPU time 406.48 seconds
Started Mar 07 02:49:00 PM PST 24
Finished Mar 07 02:55:47 PM PST 24
Peak memory 222852 kb
Host smart-f0a6ae4c-0123-456f-a084-d144efb2b1fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688189331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1688189331
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.473364024
Short name T635
Test name
Test status
Simulation time 3360768469 ps
CPU time 19.95 seconds
Started Mar 07 02:48:59 PM PST 24
Finished Mar 07 02:49:20 PM PST 24
Peak memory 207868 kb
Host smart-8446b561-db14-4d78-b26b-1e239439c6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473364024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.473364024
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.4147339579
Short name T756
Test name
Test status
Simulation time 366226169 ps
CPU time 2.46 seconds
Started Mar 07 02:48:50 PM PST 24
Finished Mar 07 02:48:53 PM PST 24
Peak memory 211188 kb
Host smart-67ff69e2-b66c-408e-8b19-9a2833ee8f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147339579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.4147339579
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2171891737
Short name T770
Test name
Test status
Simulation time 11026627 ps
CPU time 0.91 seconds
Started Mar 07 02:48:55 PM PST 24
Finished Mar 07 02:48:56 PM PST 24
Peak memory 206164 kb
Host smart-2a7e1f89-9a6a-4172-82c2-838f7961552b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171891737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2171891737
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3316394871
Short name T360
Test name
Test status
Simulation time 566995324 ps
CPU time 15.07 seconds
Started Mar 07 02:48:54 PM PST 24
Finished Mar 07 02:49:09 PM PST 24
Peak memory 214588 kb
Host smart-bfc1e119-7d8a-46bb-b2f1-205997620f39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3316394871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3316394871
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1733859099
Short name T222
Test name
Test status
Simulation time 147459785 ps
CPU time 5.15 seconds
Started Mar 07 02:48:52 PM PST 24
Finished Mar 07 02:48:57 PM PST 24
Peak memory 209112 kb
Host smart-0321812a-1f2c-4548-9cf9-d74905433d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733859099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1733859099
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3629364435
Short name T674
Test name
Test status
Simulation time 267315358 ps
CPU time 6.86 seconds
Started Mar 07 02:48:53 PM PST 24
Finished Mar 07 02:49:00 PM PST 24
Peak memory 209512 kb
Host smart-18e950f6-f6bf-4120-908a-f40c9c59d2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629364435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3629364435
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2094887872
Short name T705
Test name
Test status
Simulation time 93693134 ps
CPU time 4.11 seconds
Started Mar 07 02:48:54 PM PST 24
Finished Mar 07 02:48:58 PM PST 24
Peak memory 209364 kb
Host smart-b82008be-e8ca-4921-b11f-53aa01396944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094887872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2094887872
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3804812916
Short name T38
Test name
Test status
Simulation time 24897305018 ps
CPU time 89.6 seconds
Started Mar 07 02:49:00 PM PST 24
Finished Mar 07 02:50:30 PM PST 24
Peak memory 235700 kb
Host smart-65ff0fe7-ee04-4e21-acee-1d69eade3dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804812916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3804812916
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.129178690
Short name T226
Test name
Test status
Simulation time 677791070 ps
CPU time 3.68 seconds
Started Mar 07 02:48:54 PM PST 24
Finished Mar 07 02:48:58 PM PST 24
Peak memory 216056 kb
Host smart-b739f9d0-9267-471b-a99d-dfcb1b89ffb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129178690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.129178690
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.230515476
Short name T461
Test name
Test status
Simulation time 1176471596 ps
CPU time 35.74 seconds
Started Mar 07 02:48:52 PM PST 24
Finished Mar 07 02:49:28 PM PST 24
Peak memory 208756 kb
Host smart-1c69f6af-d504-4222-9e0e-c03d4eaeb7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230515476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.230515476
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.4195861664
Short name T110
Test name
Test status
Simulation time 124559174 ps
CPU time 2.5 seconds
Started Mar 07 02:48:53 PM PST 24
Finished Mar 07 02:48:56 PM PST 24
Peak memory 207120 kb
Host smart-8fca34f2-103a-4e6f-b437-9e12fed87f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195861664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.4195861664
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2750527268
Short name T763
Test name
Test status
Simulation time 157650427 ps
CPU time 2.51 seconds
Started Mar 07 02:49:00 PM PST 24
Finished Mar 07 02:49:03 PM PST 24
Peak memory 206984 kb
Host smart-1d4c8316-05f9-4825-a336-842543be2c21
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750527268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2750527268
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2724544133
Short name T368
Test name
Test status
Simulation time 24090100 ps
CPU time 2 seconds
Started Mar 07 02:48:50 PM PST 24
Finished Mar 07 02:48:52 PM PST 24
Peak memory 208616 kb
Host smart-3f24354d-5d1b-499c-8819-97d50cd54124
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724544133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2724544133
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3699840449
Short name T700
Test name
Test status
Simulation time 569392158 ps
CPU time 11.86 seconds
Started Mar 07 02:48:59 PM PST 24
Finished Mar 07 02:49:11 PM PST 24
Peak memory 210008 kb
Host smart-40db186d-584d-4393-b19c-48df904b2d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699840449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3699840449
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1745282656
Short name T482
Test name
Test status
Simulation time 88123202 ps
CPU time 3.64 seconds
Started Mar 07 02:48:53 PM PST 24
Finished Mar 07 02:48:57 PM PST 24
Peak memory 208336 kb
Host smart-447ceb71-69a2-4723-9d70-d42d7b33e879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745282656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1745282656
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.112901898
Short name T742
Test name
Test status
Simulation time 1997628278 ps
CPU time 14.35 seconds
Started Mar 07 02:48:59 PM PST 24
Finished Mar 07 02:49:14 PM PST 24
Peak memory 220540 kb
Host smart-1eec4136-44e9-4511-af0f-95f5b778b33b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112901898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.112901898
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.4070595575
Short name T485
Test name
Test status
Simulation time 10387795196 ps
CPU time 102.64 seconds
Started Mar 07 02:48:59 PM PST 24
Finished Mar 07 02:50:42 PM PST 24
Peak memory 222660 kb
Host smart-84e5f4d4-c4ce-4d21-a4a3-c0464688f6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070595575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.4070595575
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1595496149
Short name T848
Test name
Test status
Simulation time 222465807 ps
CPU time 3.01 seconds
Started Mar 07 02:48:53 PM PST 24
Finished Mar 07 02:48:56 PM PST 24
Peak memory 210004 kb
Host smart-9ad98ae3-fc22-45c9-9312-5a2ab6d135cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595496149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1595496149
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1251965436
Short name T478
Test name
Test status
Simulation time 10582526 ps
CPU time 0.73 seconds
Started Mar 07 02:49:00 PM PST 24
Finished Mar 07 02:49:01 PM PST 24
Peak memory 206088 kb
Host smart-24903382-6586-405a-93b3-57b95056272b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251965436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1251965436
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.227227125
Short name T357
Test name
Test status
Simulation time 93979062 ps
CPU time 4.36 seconds
Started Mar 07 02:49:00 PM PST 24
Finished Mar 07 02:49:05 PM PST 24
Peak memory 214564 kb
Host smart-cbf011b7-0c0d-4082-a4eb-33f9226ae3a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=227227125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.227227125
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2792758449
Short name T66
Test name
Test status
Simulation time 1291652457 ps
CPU time 21.44 seconds
Started Mar 07 02:48:59 PM PST 24
Finished Mar 07 02:49:21 PM PST 24
Peak memory 218416 kb
Host smart-bb54a6a7-8778-426a-bf70-19dfc2e94aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792758449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2792758449
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1542907595
Short name T808
Test name
Test status
Simulation time 1976704861 ps
CPU time 16.59 seconds
Started Mar 07 02:48:57 PM PST 24
Finished Mar 07 02:49:14 PM PST 24
Peak memory 219348 kb
Host smart-a6cb48cb-06a9-4239-91b6-81193c8d44d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542907595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1542907595
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1812037036
Short name T344
Test name
Test status
Simulation time 390667222 ps
CPU time 5.25 seconds
Started Mar 07 02:49:01 PM PST 24
Finished Mar 07 02:49:06 PM PST 24
Peak memory 214476 kb
Host smart-4a8eedf5-65b6-4397-afc8-10c0c29a5360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812037036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1812037036
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1712152551
Short name T401
Test name
Test status
Simulation time 105027333 ps
CPU time 3.88 seconds
Started Mar 07 02:48:59 PM PST 24
Finished Mar 07 02:49:04 PM PST 24
Peak memory 206308 kb
Host smart-e8a6c1cd-209d-4a23-b6b6-23d0455c4e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712152551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1712152551
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3330776522
Short name T215
Test name
Test status
Simulation time 85626035 ps
CPU time 4.03 seconds
Started Mar 07 02:49:00 PM PST 24
Finished Mar 07 02:49:05 PM PST 24
Peak memory 209268 kb
Host smart-edc4c459-1c52-41d7-b9bc-2df08cacf850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330776522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3330776522
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3627537444
Short name T803
Test name
Test status
Simulation time 5532675358 ps
CPU time 34.04 seconds
Started Mar 07 02:49:00 PM PST 24
Finished Mar 07 02:49:35 PM PST 24
Peak memory 208320 kb
Host smart-e193180f-592f-4d20-9953-7c0d7de2bdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627537444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3627537444
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.4082675401
Short name T846
Test name
Test status
Simulation time 452002853 ps
CPU time 6.14 seconds
Started Mar 07 02:48:51 PM PST 24
Finished Mar 07 02:48:58 PM PST 24
Peak memory 207932 kb
Host smart-32b9a611-6612-4412-8c38-75d7e2f8d9d8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082675401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.4082675401
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3582472012
Short name T793
Test name
Test status
Simulation time 97324938 ps
CPU time 1.93 seconds
Started Mar 07 02:48:54 PM PST 24
Finished Mar 07 02:48:57 PM PST 24
Peak memory 206772 kb
Host smart-553bd8ce-265e-4bc8-b165-29598c2fd0e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582472012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3582472012
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3010989135
Short name T481
Test name
Test status
Simulation time 2117368860 ps
CPU time 23.9 seconds
Started Mar 07 02:49:00 PM PST 24
Finished Mar 07 02:49:25 PM PST 24
Peak memory 209144 kb
Host smart-b04b92cf-87e3-494c-a362-70c3ab6d3c0e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010989135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3010989135
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3962721223
Short name T16
Test name
Test status
Simulation time 452607269 ps
CPU time 3.26 seconds
Started Mar 07 02:48:58 PM PST 24
Finished Mar 07 02:49:02 PM PST 24
Peak memory 214616 kb
Host smart-e4c338e3-7203-4555-85a0-30ee37437be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962721223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3962721223
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2499072565
Short name T436
Test name
Test status
Simulation time 189965758 ps
CPU time 6.49 seconds
Started Mar 07 02:48:53 PM PST 24
Finished Mar 07 02:49:00 PM PST 24
Peak memory 206648 kb
Host smart-1cdc645e-25ae-48cd-b7d7-7670cb4a734e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499072565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2499072565
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3530251611
Short name T721
Test name
Test status
Simulation time 289110527 ps
CPU time 8.41 seconds
Started Mar 07 02:49:00 PM PST 24
Finished Mar 07 02:49:09 PM PST 24
Peak memory 209888 kb
Host smart-f92ea516-0ed1-47b3-ae49-04520f10ab41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530251611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3530251611
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3730545935
Short name T202
Test name
Test status
Simulation time 423235474 ps
CPU time 4.81 seconds
Started Mar 07 02:48:59 PM PST 24
Finished Mar 07 02:49:05 PM PST 24
Peak memory 210452 kb
Host smart-562620b8-fc67-4485-a481-04fb8c81c3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730545935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3730545935
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2450762128
Short name T654
Test name
Test status
Simulation time 16103547 ps
CPU time 0.93 seconds
Started Mar 07 02:48:00 PM PST 24
Finished Mar 07 02:48:01 PM PST 24
Peak memory 206332 kb
Host smart-6508aa5e-b267-4129-a6ec-c43b0b7ab447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450762128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2450762128
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2232856579
Short name T406
Test name
Test status
Simulation time 250732197 ps
CPU time 4.4 seconds
Started Mar 07 02:47:51 PM PST 24
Finished Mar 07 02:47:56 PM PST 24
Peak memory 215960 kb
Host smart-1a32028f-4f0b-4d60-bee5-b4faf8f65caf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2232856579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2232856579
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.4218507891
Short name T20
Test name
Test status
Simulation time 366694955 ps
CPU time 2.36 seconds
Started Mar 07 02:47:57 PM PST 24
Finished Mar 07 02:48:00 PM PST 24
Peak memory 220092 kb
Host smart-2d863a48-7cb1-4549-aded-23b72bfe85ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218507891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.4218507891
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.606314124
Short name T258
Test name
Test status
Simulation time 67341187 ps
CPU time 2.06 seconds
Started Mar 07 02:47:55 PM PST 24
Finished Mar 07 02:47:58 PM PST 24
Peak memory 208348 kb
Host smart-01308a1f-0038-442b-b053-1fd55c867aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606314124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.606314124
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.58792542
Short name T59
Test name
Test status
Simulation time 134391464 ps
CPU time 5.09 seconds
Started Mar 07 02:48:01 PM PST 24
Finished Mar 07 02:48:06 PM PST 24
Peak memory 215412 kb
Host smart-ad8641e5-8511-4af0-8625-e537c5b4e708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58792542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.58792542
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1686535747
Short name T884
Test name
Test status
Simulation time 190893170 ps
CPU time 5.96 seconds
Started Mar 07 02:47:57 PM PST 24
Finished Mar 07 02:48:03 PM PST 24
Peak memory 218292 kb
Host smart-656500e2-b8f6-4c57-b69b-4c8c59e8504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686535747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1686535747
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1079983768
Short name T13
Test name
Test status
Simulation time 556080755 ps
CPU time 14.96 seconds
Started Mar 07 02:47:59 PM PST 24
Finished Mar 07 02:48:14 PM PST 24
Peak memory 238428 kb
Host smart-be59986f-efe7-4540-a018-756cad1f8ef9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079983768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1079983768
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.4290925677
Short name T133
Test name
Test status
Simulation time 161369494 ps
CPU time 3.84 seconds
Started Mar 07 02:47:50 PM PST 24
Finished Mar 07 02:47:55 PM PST 24
Peak memory 208452 kb
Host smart-7279e5fd-86cf-45a6-87e0-e2207961b639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290925677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.4290925677
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.283258022
Short name T252
Test name
Test status
Simulation time 117145082 ps
CPU time 2.83 seconds
Started Mar 07 02:47:51 PM PST 24
Finished Mar 07 02:47:54 PM PST 24
Peak memory 209116 kb
Host smart-b9ae09cc-7396-4951-8f2d-9d98f39b2da8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283258022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.283258022
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.306798099
Short name T107
Test name
Test status
Simulation time 403204442 ps
CPU time 7.97 seconds
Started Mar 07 02:48:01 PM PST 24
Finished Mar 07 02:48:10 PM PST 24
Peak memory 208916 kb
Host smart-12ecc773-f327-48fd-95c6-b3f9fda9fcc1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306798099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.306798099
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1823556200
Short name T189
Test name
Test status
Simulation time 174920324 ps
CPU time 6.34 seconds
Started Mar 07 02:48:01 PM PST 24
Finished Mar 07 02:48:07 PM PST 24
Peak memory 206732 kb
Host smart-2a4011dd-1477-48fa-93fc-0b7723faa977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823556200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1823556200
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.481920564
Short name T290
Test name
Test status
Simulation time 1081718390 ps
CPU time 16.24 seconds
Started Mar 07 02:48:00 PM PST 24
Finished Mar 07 02:48:16 PM PST 24
Peak memory 215116 kb
Host smart-bb1e68a1-cbc8-47f8-a953-e2bab18ba4f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481920564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.481920564
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1230170621
Short name T312
Test name
Test status
Simulation time 117918751 ps
CPU time 5.65 seconds
Started Mar 07 02:48:00 PM PST 24
Finished Mar 07 02:48:06 PM PST 24
Peak memory 214436 kb
Host smart-2af9134d-15ac-49da-9bf3-13ab374b7ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230170621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1230170621
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3706321635
Short name T458
Test name
Test status
Simulation time 44581400 ps
CPU time 2.55 seconds
Started Mar 07 02:47:58 PM PST 24
Finished Mar 07 02:48:01 PM PST 24
Peak memory 209968 kb
Host smart-4b4d143c-0d1e-468a-bda4-a419263ae163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706321635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3706321635
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2952074236
Short name T668
Test name
Test status
Simulation time 29885526 ps
CPU time 0.91 seconds
Started Mar 07 02:48:59 PM PST 24
Finished Mar 07 02:49:01 PM PST 24
Peak memory 206256 kb
Host smart-25961953-c2a3-41db-b251-3527717e9322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952074236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2952074236
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2283319413
Short name T420
Test name
Test status
Simulation time 51757427 ps
CPU time 3.9 seconds
Started Mar 07 02:48:56 PM PST 24
Finished Mar 07 02:49:01 PM PST 24
Peak memory 214624 kb
Host smart-84c4c16d-9554-460b-b1da-d54e6199a99a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2283319413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2283319413
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1604366609
Short name T10
Test name
Test status
Simulation time 816391824 ps
CPU time 10.05 seconds
Started Mar 07 02:48:59 PM PST 24
Finished Mar 07 02:49:10 PM PST 24
Peak memory 222928 kb
Host smart-5f520bd9-6c0a-4a2e-8690-3e79325196ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604366609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1604366609
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1671491675
Short name T869
Test name
Test status
Simulation time 20790889 ps
CPU time 1.52 seconds
Started Mar 07 02:48:58 PM PST 24
Finished Mar 07 02:49:00 PM PST 24
Peak memory 207156 kb
Host smart-d06091ef-04a2-403f-9a97-af01fc824d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671491675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1671491675
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3435066335
Short name T842
Test name
Test status
Simulation time 75132780 ps
CPU time 4.03 seconds
Started Mar 07 02:49:01 PM PST 24
Finished Mar 07 02:49:06 PM PST 24
Peak memory 218460 kb
Host smart-ccad3716-a790-401c-ac0b-881c84ed3482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435066335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3435066335
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.859079597
Short name T320
Test name
Test status
Simulation time 437249756 ps
CPU time 6.09 seconds
Started Mar 07 02:49:06 PM PST 24
Finished Mar 07 02:49:13 PM PST 24
Peak memory 210688 kb
Host smart-ed103194-7f35-4f60-8967-8674f4d007bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859079597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.859079597
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3289638065
Short name T750
Test name
Test status
Simulation time 246552901 ps
CPU time 7.28 seconds
Started Mar 07 02:48:59 PM PST 24
Finished Mar 07 02:49:07 PM PST 24
Peak memory 209660 kb
Host smart-fb399b60-0601-4b36-9269-865b9ee61ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289638065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3289638065
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3993061687
Short name T392
Test name
Test status
Simulation time 1720665592 ps
CPU time 12.45 seconds
Started Mar 07 02:49:08 PM PST 24
Finished Mar 07 02:49:21 PM PST 24
Peak memory 206804 kb
Host smart-69cfcfc9-236e-4161-9eb3-71a080279387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993061687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3993061687
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.4148292033
Short name T299
Test name
Test status
Simulation time 88769448 ps
CPU time 2.12 seconds
Started Mar 07 02:48:57 PM PST 24
Finished Mar 07 02:49:00 PM PST 24
Peak memory 208504 kb
Host smart-81649e14-5b1c-448f-a3b9-cd10499a671f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148292033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.4148292033
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1424579557
Short name T800
Test name
Test status
Simulation time 3217539498 ps
CPU time 22.81 seconds
Started Mar 07 02:49:02 PM PST 24
Finished Mar 07 02:49:25 PM PST 24
Peak memory 208100 kb
Host smart-1a2fd9a6-f573-40d3-8ffc-88101f4b9195
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424579557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1424579557
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3294275238
Short name T450
Test name
Test status
Simulation time 60566735 ps
CPU time 2.97 seconds
Started Mar 07 02:49:00 PM PST 24
Finished Mar 07 02:49:04 PM PST 24
Peak memory 207968 kb
Host smart-34f1ab0b-be08-4a98-aa8e-8127bd84c33b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294275238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3294275238
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2996806175
Short name T746
Test name
Test status
Simulation time 100289069 ps
CPU time 2.87 seconds
Started Mar 07 02:48:58 PM PST 24
Finished Mar 07 02:49:02 PM PST 24
Peak memory 206868 kb
Host smart-4fe5b642-56fe-4b81-bce0-6727a3ad53e5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996806175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2996806175
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2168005914
Short name T521
Test name
Test status
Simulation time 170886681 ps
CPU time 5.85 seconds
Started Mar 07 02:48:57 PM PST 24
Finished Mar 07 02:49:04 PM PST 24
Peak memory 209712 kb
Host smart-01092368-cbd3-4edb-9177-b0e476545845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168005914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2168005914
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.578017282
Short name T434
Test name
Test status
Simulation time 351160321 ps
CPU time 3.06 seconds
Started Mar 07 02:48:58 PM PST 24
Finished Mar 07 02:49:02 PM PST 24
Peak memory 208268 kb
Host smart-b9a4c408-5e28-492a-b736-dff707633def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578017282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.578017282
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.816226191
Short name T678
Test name
Test status
Simulation time 1533698329 ps
CPU time 46.65 seconds
Started Mar 07 02:49:08 PM PST 24
Finished Mar 07 02:49:55 PM PST 24
Peak memory 221628 kb
Host smart-a539d888-d466-4aa9-8207-07c08f38278e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816226191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.816226191
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2034256737
Short name T588
Test name
Test status
Simulation time 2511660591 ps
CPU time 86.68 seconds
Started Mar 07 02:49:02 PM PST 24
Finished Mar 07 02:50:29 PM PST 24
Peak memory 222708 kb
Host smart-fcc5b576-a45f-446e-ab9d-8a9721515230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034256737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2034256737
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.752429716
Short name T36
Test name
Test status
Simulation time 73540876 ps
CPU time 2.89 seconds
Started Mar 07 02:48:58 PM PST 24
Finished Mar 07 02:49:02 PM PST 24
Peak memory 210080 kb
Host smart-9da33d52-0d34-4c84-992c-cefa0a93ca74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752429716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.752429716
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2347047392
Short name T883
Test name
Test status
Simulation time 68516335 ps
CPU time 0.76 seconds
Started Mar 07 02:49:06 PM PST 24
Finished Mar 07 02:49:07 PM PST 24
Peak memory 206136 kb
Host smart-f09997be-5ea3-4dc9-ba8d-e482bb8a8a46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347047392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2347047392
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2004381665
Short name T362
Test name
Test status
Simulation time 70419106 ps
CPU time 3.48 seconds
Started Mar 07 02:49:06 PM PST 24
Finished Mar 07 02:49:10 PM PST 24
Peak memory 210232 kb
Host smart-3e36e5fe-bd88-4c63-a8da-d5748774d5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004381665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2004381665
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2541254239
Short name T664
Test name
Test status
Simulation time 466411177 ps
CPU time 8.94 seconds
Started Mar 07 02:49:06 PM PST 24
Finished Mar 07 02:49:15 PM PST 24
Peak memory 210024 kb
Host smart-7185f9dc-09d8-41ba-8f81-cd00865a6a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541254239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2541254239
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.4000196926
Short name T815
Test name
Test status
Simulation time 2097250144 ps
CPU time 33.78 seconds
Started Mar 07 02:48:59 PM PST 24
Finished Mar 07 02:49:33 PM PST 24
Peak memory 210028 kb
Host smart-21f2f6fa-aa74-41e3-90d4-f2984bc7b611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000196926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.4000196926
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.633641893
Short name T634
Test name
Test status
Simulation time 2224600654 ps
CPU time 14.1 seconds
Started Mar 07 02:49:01 PM PST 24
Finished Mar 07 02:49:16 PM PST 24
Peak memory 209536 kb
Host smart-03032eca-c3de-4634-8e7a-27729a528222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633641893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.633641893
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2055021144
Short name T495
Test name
Test status
Simulation time 22919795 ps
CPU time 1.85 seconds
Started Mar 07 02:48:59 PM PST 24
Finished Mar 07 02:49:02 PM PST 24
Peak memory 206744 kb
Host smart-da1a7b28-87e5-4cf3-b376-139a6c48fd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055021144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2055021144
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2202701822
Short name T772
Test name
Test status
Simulation time 1602055987 ps
CPU time 32.82 seconds
Started Mar 07 02:49:00 PM PST 24
Finished Mar 07 02:49:34 PM PST 24
Peak memory 208408 kb
Host smart-87ed664c-a3dc-4182-ae08-a9d1271427e5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202701822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2202701822
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1261038324
Short name T672
Test name
Test status
Simulation time 203552244 ps
CPU time 6.86 seconds
Started Mar 07 02:49:00 PM PST 24
Finished Mar 07 02:49:08 PM PST 24
Peak memory 207860 kb
Host smart-47d61a10-a77e-4f9f-a7ec-e0b9e065f3b6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261038324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1261038324
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.637957575
Short name T219
Test name
Test status
Simulation time 49697816 ps
CPU time 2.79 seconds
Started Mar 07 02:49:08 PM PST 24
Finished Mar 07 02:49:11 PM PST 24
Peak memory 206380 kb
Host smart-e0e17ce5-c9b0-4ee0-bb83-41431e2e749e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637957575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.637957575
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.907830454
Short name T518
Test name
Test status
Simulation time 84651499 ps
CPU time 3.12 seconds
Started Mar 07 02:49:06 PM PST 24
Finished Mar 07 02:49:09 PM PST 24
Peak memory 209260 kb
Host smart-95d45663-a215-434f-b646-0a8ddf3ee3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907830454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.907830454
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3137379222
Short name T88
Test name
Test status
Simulation time 87622828 ps
CPU time 3.89 seconds
Started Mar 07 02:49:06 PM PST 24
Finished Mar 07 02:49:10 PM PST 24
Peak memory 208660 kb
Host smart-bcd879ee-7afe-4e5e-809c-964bcae22d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137379222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3137379222
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2244130898
Short name T602
Test name
Test status
Simulation time 1040003705 ps
CPU time 17.2 seconds
Started Mar 07 02:49:06 PM PST 24
Finished Mar 07 02:49:23 PM PST 24
Peak memory 215916 kb
Host smart-d2fc2eae-e1e2-470c-bb17-e006ecf89fcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244130898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2244130898
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.94705502
Short name T132
Test name
Test status
Simulation time 4244547805 ps
CPU time 11.83 seconds
Started Mar 07 02:49:07 PM PST 24
Finished Mar 07 02:49:20 PM PST 24
Peak memory 220308 kb
Host smart-f3bc1d34-a150-490f-9150-8fbb4aee309c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94705502 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.94705502
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2761144891
Short name T261
Test name
Test status
Simulation time 504714750 ps
CPU time 5.28 seconds
Started Mar 07 02:49:09 PM PST 24
Finished Mar 07 02:49:14 PM PST 24
Peak memory 207396 kb
Host smart-b9eb1c91-c9dc-43db-881c-0808a84bfad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761144891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2761144891
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3872898801
Short name T381
Test name
Test status
Simulation time 89647248 ps
CPU time 1.65 seconds
Started Mar 07 02:49:06 PM PST 24
Finished Mar 07 02:49:08 PM PST 24
Peak memory 209732 kb
Host smart-538bd70f-5710-4980-b8dc-1f13481bbdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872898801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3872898801
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3380736742
Short name T856
Test name
Test status
Simulation time 38902940 ps
CPU time 0.84 seconds
Started Mar 07 02:49:07 PM PST 24
Finished Mar 07 02:49:08 PM PST 24
Peak memory 206200 kb
Host smart-abc4054f-0219-438d-ab95-9bd38b875aec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380736742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3380736742
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2458313235
Short name T140
Test name
Test status
Simulation time 192915678 ps
CPU time 10.46 seconds
Started Mar 07 02:49:05 PM PST 24
Finished Mar 07 02:49:16 PM PST 24
Peak memory 214492 kb
Host smart-fd478b47-c897-43bb-a504-59165d58a963
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2458313235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2458313235
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2262606945
Short name T525
Test name
Test status
Simulation time 524787999 ps
CPU time 15.63 seconds
Started Mar 07 02:49:04 PM PST 24
Finished Mar 07 02:49:20 PM PST 24
Peak memory 208080 kb
Host smart-2fe30ce8-695a-4048-b98a-048551779450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262606945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2262606945
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1917972400
Short name T83
Test name
Test status
Simulation time 441277150 ps
CPU time 6.11 seconds
Started Mar 07 02:49:07 PM PST 24
Finished Mar 07 02:49:13 PM PST 24
Peak memory 208376 kb
Host smart-3f52261c-7df9-46cc-b3d9-2a6b4cdc90bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917972400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1917972400
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.110302218
Short name T218
Test name
Test status
Simulation time 1322785567 ps
CPU time 6.71 seconds
Started Mar 07 02:49:04 PM PST 24
Finished Mar 07 02:49:11 PM PST 24
Peak memory 214548 kb
Host smart-47b0e528-6e31-4537-9080-1a1179869c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110302218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.110302218
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.419329528
Short name T329
Test name
Test status
Simulation time 58895475 ps
CPU time 3.52 seconds
Started Mar 07 02:49:05 PM PST 24
Finished Mar 07 02:49:09 PM PST 24
Peak memory 207576 kb
Host smart-4c0ae54a-ff91-4066-95c1-702ea9a75a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419329528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.419329528
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.438888526
Short name T637
Test name
Test status
Simulation time 60295951 ps
CPU time 3.72 seconds
Started Mar 07 02:49:07 PM PST 24
Finished Mar 07 02:49:11 PM PST 24
Peak memory 208600 kb
Host smart-9f1ad312-9f07-4c74-a7b8-a6107924e138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438888526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.438888526
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2890634239
Short name T494
Test name
Test status
Simulation time 219349524 ps
CPU time 3.14 seconds
Started Mar 07 02:49:06 PM PST 24
Finished Mar 07 02:49:09 PM PST 24
Peak memory 206612 kb
Host smart-176dc096-daa5-4ee7-9895-1e7998c86433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890634239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2890634239
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2434154511
Short name T696
Test name
Test status
Simulation time 204975141 ps
CPU time 2.84 seconds
Started Mar 07 02:49:04 PM PST 24
Finished Mar 07 02:49:07 PM PST 24
Peak memory 208028 kb
Host smart-3e42eac9-5a84-4229-a63a-c3fd5fb02a5e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434154511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2434154511
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3295476537
Short name T617
Test name
Test status
Simulation time 242490450 ps
CPU time 2.78 seconds
Started Mar 07 02:49:10 PM PST 24
Finished Mar 07 02:49:13 PM PST 24
Peak memory 208620 kb
Host smart-48dcfca0-051f-4317-aeb6-9880f9885b14
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295476537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3295476537
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3495230516
Short name T260
Test name
Test status
Simulation time 32632052 ps
CPU time 2.42 seconds
Started Mar 07 02:49:06 PM PST 24
Finished Mar 07 02:49:08 PM PST 24
Peak memory 208484 kb
Host smart-28750fe7-0900-4148-a8c3-8c438c5291d1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495230516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3495230516
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.4059291091
Short name T768
Test name
Test status
Simulation time 173101765 ps
CPU time 6.17 seconds
Started Mar 07 02:49:04 PM PST 24
Finished Mar 07 02:49:11 PM PST 24
Peak memory 214512 kb
Host smart-b91074a6-80be-4d51-a010-6fe65e76b2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059291091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.4059291091
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1616627372
Short name T575
Test name
Test status
Simulation time 788038181 ps
CPU time 7.8 seconds
Started Mar 07 02:49:05 PM PST 24
Finished Mar 07 02:49:13 PM PST 24
Peak memory 208280 kb
Host smart-8a915aea-c1b3-47d9-adda-1fe62f89ee11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616627372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1616627372
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2016362183
Short name T199
Test name
Test status
Simulation time 1196329140 ps
CPU time 31.84 seconds
Started Mar 07 02:49:04 PM PST 24
Finished Mar 07 02:49:36 PM PST 24
Peak memory 215916 kb
Host smart-78fafc33-ec31-4247-b71b-43ed6c9146b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016362183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2016362183
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.279531595
Short name T717
Test name
Test status
Simulation time 386554189 ps
CPU time 4.74 seconds
Started Mar 07 02:49:09 PM PST 24
Finished Mar 07 02:49:13 PM PST 24
Peak memory 210200 kb
Host smart-be96f458-42db-40b8-96a1-3b4cdd594c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279531595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.279531595
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3741693278
Short name T892
Test name
Test status
Simulation time 54978248 ps
CPU time 2.54 seconds
Started Mar 07 02:49:06 PM PST 24
Finished Mar 07 02:49:08 PM PST 24
Peak memory 210140 kb
Host smart-37bfd99d-e920-4337-972d-d7c7539f2d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741693278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3741693278
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.4050479178
Short name T816
Test name
Test status
Simulation time 22656113 ps
CPU time 0.76 seconds
Started Mar 07 02:49:11 PM PST 24
Finished Mar 07 02:49:12 PM PST 24
Peak memory 206112 kb
Host smart-44297a1f-fe37-463b-ac1f-62de2744b956
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050479178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.4050479178
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2640437790
Short name T423
Test name
Test status
Simulation time 519509765 ps
CPU time 7.89 seconds
Started Mar 07 02:49:07 PM PST 24
Finished Mar 07 02:49:15 PM PST 24
Peak memory 214524 kb
Host smart-6fb82a6e-81d0-40ce-83ff-305fede26b06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2640437790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2640437790
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3544424775
Short name T665
Test name
Test status
Simulation time 78456919 ps
CPU time 3.74 seconds
Started Mar 07 02:49:19 PM PST 24
Finished Mar 07 02:49:23 PM PST 24
Peak memory 210500 kb
Host smart-2f0cecc9-3126-4eb7-850d-6f8ee30b8ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544424775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3544424775
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2399833228
Short name T745
Test name
Test status
Simulation time 37391233 ps
CPU time 2.24 seconds
Started Mar 07 02:49:17 PM PST 24
Finished Mar 07 02:49:20 PM PST 24
Peak memory 207372 kb
Host smart-d0a30934-2d40-4bb0-baf5-58c2a11d8ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399833228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2399833228
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3521722908
Short name T297
Test name
Test status
Simulation time 1222576813 ps
CPU time 13.87 seconds
Started Mar 07 02:49:18 PM PST 24
Finished Mar 07 02:49:32 PM PST 24
Peak memory 210332 kb
Host smart-807eda34-8ce4-4e9b-8377-d782457431cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521722908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3521722908
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1361023574
Short name T812
Test name
Test status
Simulation time 1087619040 ps
CPU time 9.08 seconds
Started Mar 07 02:49:12 PM PST 24
Finished Mar 07 02:49:22 PM PST 24
Peak memory 215416 kb
Host smart-8fd35d95-f367-4021-8cd1-c94fb684d581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361023574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1361023574
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2256591412
Short name T311
Test name
Test status
Simulation time 182976142 ps
CPU time 4.44 seconds
Started Mar 07 02:49:08 PM PST 24
Finished Mar 07 02:49:13 PM PST 24
Peak memory 208792 kb
Host smart-62328b6b-3a08-44c2-8ea7-5af110032072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256591412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2256591412
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1990713859
Short name T502
Test name
Test status
Simulation time 141372861 ps
CPU time 4.79 seconds
Started Mar 07 02:49:07 PM PST 24
Finished Mar 07 02:49:13 PM PST 24
Peak memory 207848 kb
Host smart-42f4b003-07d2-46fb-8bc3-7f4e4c5104ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990713859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1990713859
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.883488437
Short name T435
Test name
Test status
Simulation time 30081346 ps
CPU time 2.37 seconds
Started Mar 07 02:49:05 PM PST 24
Finished Mar 07 02:49:08 PM PST 24
Peak memory 206852 kb
Host smart-91aa957c-e0f8-4a94-aaea-88d1350af137
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883488437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.883488437
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3981040648
Short name T817
Test name
Test status
Simulation time 187967982 ps
CPU time 2.58 seconds
Started Mar 07 02:49:07 PM PST 24
Finished Mar 07 02:49:10 PM PST 24
Peak memory 206904 kb
Host smart-63220934-5564-4e09-b2e9-75a28015daf0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981040648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3981040648
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3847118002
Short name T568
Test name
Test status
Simulation time 399300059 ps
CPU time 3.96 seconds
Started Mar 07 02:49:09 PM PST 24
Finished Mar 07 02:49:14 PM PST 24
Peak memory 206884 kb
Host smart-084b590e-b441-4d35-9210-2a1c7445d359
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847118002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3847118002
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.123738068
Short name T706
Test name
Test status
Simulation time 111929006 ps
CPU time 2.22 seconds
Started Mar 07 02:49:14 PM PST 24
Finished Mar 07 02:49:17 PM PST 24
Peak memory 208156 kb
Host smart-dbf58fb2-c6b6-44db-aa7f-9cd4ea4792d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123738068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.123738068
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.746563822
Short name T446
Test name
Test status
Simulation time 130935777 ps
CPU time 2.62 seconds
Started Mar 07 02:49:09 PM PST 24
Finished Mar 07 02:49:12 PM PST 24
Peak memory 206612 kb
Host smart-d0f3a08a-c34c-4469-8117-27177b37b133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746563822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.746563822
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2092445906
Short name T801
Test name
Test status
Simulation time 359540350 ps
CPU time 4.07 seconds
Started Mar 07 02:49:18 PM PST 24
Finished Mar 07 02:49:22 PM PST 24
Peak memory 208148 kb
Host smart-07eada79-4b40-4df2-be58-31565358251a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092445906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2092445906
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2408917075
Short name T474
Test name
Test status
Simulation time 14250495 ps
CPU time 0.75 seconds
Started Mar 07 02:49:12 PM PST 24
Finished Mar 07 02:49:13 PM PST 24
Peak memory 206184 kb
Host smart-614afeea-35e9-4730-b110-143d4726e244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408917075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2408917075
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1520178945
Short name T331
Test name
Test status
Simulation time 263140569 ps
CPU time 14.48 seconds
Started Mar 07 02:49:14 PM PST 24
Finished Mar 07 02:49:28 PM PST 24
Peak memory 214536 kb
Host smart-9a893172-d4ec-4d38-bab0-e339e4279ba1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1520178945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1520178945
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3020277456
Short name T834
Test name
Test status
Simulation time 640553689 ps
CPU time 2.85 seconds
Started Mar 07 02:49:17 PM PST 24
Finished Mar 07 02:49:20 PM PST 24
Peak memory 214740 kb
Host smart-477bbbe0-89ae-4279-ac13-96ace100c22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020277456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3020277456
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1672662352
Short name T267
Test name
Test status
Simulation time 23244875 ps
CPU time 1.78 seconds
Started Mar 07 02:49:13 PM PST 24
Finished Mar 07 02:49:16 PM PST 24
Peak memory 207148 kb
Host smart-1e2dd60e-30ec-49d0-bb09-523847b4713b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672662352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1672662352
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2437285598
Short name T91
Test name
Test status
Simulation time 417355864 ps
CPU time 4.65 seconds
Started Mar 07 02:49:13 PM PST 24
Finished Mar 07 02:49:18 PM PST 24
Peak memory 208548 kb
Host smart-556ab056-3e08-4e84-8330-be3b3e56f33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437285598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2437285598
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3446451821
Short name T374
Test name
Test status
Simulation time 487639991 ps
CPU time 6.96 seconds
Started Mar 07 02:49:15 PM PST 24
Finished Mar 07 02:49:22 PM PST 24
Peak memory 214368 kb
Host smart-35f5be95-90f9-48a7-ae73-d49fdef3eb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446451821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3446451821
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_random.1791314366
Short name T651
Test name
Test status
Simulation time 717323335 ps
CPU time 20.27 seconds
Started Mar 07 02:49:17 PM PST 24
Finished Mar 07 02:49:37 PM PST 24
Peak memory 218632 kb
Host smart-0a2e2fa0-b9ee-49da-b0d6-b2489e99fd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791314366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1791314366
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.649358589
Short name T451
Test name
Test status
Simulation time 6655044472 ps
CPU time 17.37 seconds
Started Mar 07 02:49:15 PM PST 24
Finished Mar 07 02:49:33 PM PST 24
Peak memory 208132 kb
Host smart-49fb2975-e9c4-430c-8eee-a864d0e952de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649358589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.649358589
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3400243155
Short name T894
Test name
Test status
Simulation time 156517017 ps
CPU time 2.49 seconds
Started Mar 07 02:49:18 PM PST 24
Finished Mar 07 02:49:21 PM PST 24
Peak memory 208764 kb
Host smart-46f3a79a-b596-496f-8d3d-c4b094194ffd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400243155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3400243155
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.290383640
Short name T276
Test name
Test status
Simulation time 319978481 ps
CPU time 2.12 seconds
Started Mar 07 02:49:14 PM PST 24
Finished Mar 07 02:49:17 PM PST 24
Peak memory 208968 kb
Host smart-a385bfcb-3b8b-47d9-b829-e21839c7f596
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290383640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.290383640
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.919173728
Short name T546
Test name
Test status
Simulation time 31523684 ps
CPU time 2.2 seconds
Started Mar 07 02:49:18 PM PST 24
Finished Mar 07 02:49:21 PM PST 24
Peak memory 208680 kb
Host smart-477424f2-4d99-4f1c-932d-63b8872e8fc6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919173728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.919173728
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.4039767887
Short name T773
Test name
Test status
Simulation time 77213399 ps
CPU time 3.02 seconds
Started Mar 07 02:49:18 PM PST 24
Finished Mar 07 02:49:22 PM PST 24
Peak memory 216188 kb
Host smart-2ecc27cd-3b1a-4610-bd0c-13b4e48f2fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039767887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.4039767887
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2283389548
Short name T547
Test name
Test status
Simulation time 2103282337 ps
CPU time 5.71 seconds
Started Mar 07 02:49:12 PM PST 24
Finished Mar 07 02:49:18 PM PST 24
Peak memory 208004 kb
Host smart-640ba516-dc17-4197-94a0-eed83c58ec09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283389548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2283389548
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2741613992
Short name T281
Test name
Test status
Simulation time 2239151914 ps
CPU time 36.47 seconds
Started Mar 07 02:49:11 PM PST 24
Finished Mar 07 02:49:48 PM PST 24
Peak memory 222680 kb
Host smart-7d700685-94a0-4439-9227-607ad5145e7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741613992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2741613992
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.34790595
Short name T204
Test name
Test status
Simulation time 1845253417 ps
CPU time 32.86 seconds
Started Mar 07 02:49:17 PM PST 24
Finished Mar 07 02:49:51 PM PST 24
Peak memory 209784 kb
Host smart-5f0a9bae-f3f6-41f8-897c-4669e67aa581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34790595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.34790595
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.576856819
Short name T383
Test name
Test status
Simulation time 463498080 ps
CPU time 2.43 seconds
Started Mar 07 02:49:17 PM PST 24
Finished Mar 07 02:49:20 PM PST 24
Peak memory 210096 kb
Host smart-99b1ec6d-b753-4cdd-929d-a927f7248418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576856819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.576856819
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2539120429
Short name T676
Test name
Test status
Simulation time 10855075 ps
CPU time 0.78 seconds
Started Mar 07 02:49:22 PM PST 24
Finished Mar 07 02:49:23 PM PST 24
Peak memory 206148 kb
Host smart-2818b29e-cd8f-4a5b-b054-b3f4d07c9fea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539120429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2539120429
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1473553762
Short name T408
Test name
Test status
Simulation time 1450575250 ps
CPU time 75.95 seconds
Started Mar 07 02:49:17 PM PST 24
Finished Mar 07 02:50:33 PM PST 24
Peak memory 214520 kb
Host smart-b29f4604-af6a-4b3a-939f-68d8360aa61b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1473553762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1473553762
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1211492261
Short name T395
Test name
Test status
Simulation time 518909603 ps
CPU time 5.17 seconds
Started Mar 07 02:49:19 PM PST 24
Finished Mar 07 02:49:24 PM PST 24
Peak memory 207776 kb
Host smart-2adee5f8-eb94-498d-ae28-06fc2b1b4007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211492261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1211492261
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.170215297
Short name T783
Test name
Test status
Simulation time 183094139 ps
CPU time 4.4 seconds
Started Mar 07 02:49:22 PM PST 24
Finished Mar 07 02:49:27 PM PST 24
Peak memory 221100 kb
Host smart-6fdaf0f7-9e03-4071-996f-b1bcd5d327a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170215297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.170215297
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3789590
Short name T579
Test name
Test status
Simulation time 52963698 ps
CPU time 2.93 seconds
Started Mar 07 02:49:19 PM PST 24
Finished Mar 07 02:49:24 PM PST 24
Peak memory 210004 kb
Host smart-8e5c28e6-8692-492e-9ad8-a6e91bd34939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3789590
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.376315535
Short name T134
Test name
Test status
Simulation time 236983147 ps
CPU time 5.84 seconds
Started Mar 07 02:49:20 PM PST 24
Finished Mar 07 02:49:27 PM PST 24
Peak memory 210192 kb
Host smart-23cac8f1-5610-42e5-844c-0d64359e874a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376315535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.376315535
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2979458199
Short name T685
Test name
Test status
Simulation time 30236803 ps
CPU time 1.82 seconds
Started Mar 07 02:49:18 PM PST 24
Finished Mar 07 02:49:20 PM PST 24
Peak memory 206740 kb
Host smart-6a228c64-638d-4659-b621-a6eea3cabb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979458199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2979458199
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1852673538
Short name T631
Test name
Test status
Simulation time 208004402 ps
CPU time 3.13 seconds
Started Mar 07 02:49:18 PM PST 24
Finished Mar 07 02:49:22 PM PST 24
Peak memory 206744 kb
Host smart-0833edbc-26c8-41d3-9609-08b0f37aa2cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852673538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1852673538
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2476016371
Short name T771
Test name
Test status
Simulation time 52076963 ps
CPU time 2.78 seconds
Started Mar 07 02:49:17 PM PST 24
Finished Mar 07 02:49:20 PM PST 24
Peak memory 208700 kb
Host smart-47186737-58b6-4e9c-a3a2-d5f822a74f74
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476016371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2476016371
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3109370014
Short name T333
Test name
Test status
Simulation time 409920422 ps
CPU time 3.4 seconds
Started Mar 07 02:49:24 PM PST 24
Finished Mar 07 02:49:28 PM PST 24
Peak memory 207976 kb
Host smart-c8ee9190-77ce-487e-a8bc-edc5a108c683
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109370014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3109370014
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3723991120
Short name T439
Test name
Test status
Simulation time 25422982 ps
CPU time 1.91 seconds
Started Mar 07 02:49:18 PM PST 24
Finished Mar 07 02:49:20 PM PST 24
Peak memory 207892 kb
Host smart-9fdafa12-e169-4a8c-bc65-ea8111fb4d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723991120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3723991120
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.235067391
Short name T471
Test name
Test status
Simulation time 270130112 ps
CPU time 2.49 seconds
Started Mar 07 02:49:12 PM PST 24
Finished Mar 07 02:49:15 PM PST 24
Peak memory 206760 kb
Host smart-829f5544-00c6-4242-8eda-923655582aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235067391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.235067391
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1018390682
Short name T79
Test name
Test status
Simulation time 2562479301 ps
CPU time 47.22 seconds
Started Mar 07 02:49:19 PM PST 24
Finished Mar 07 02:50:07 PM PST 24
Peak memory 222164 kb
Host smart-3d7009fa-e050-4ec7-9dd9-34bb9d565e85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018390682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1018390682
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.675521896
Short name T330
Test name
Test status
Simulation time 28556747 ps
CPU time 2.31 seconds
Started Mar 07 02:49:18 PM PST 24
Finished Mar 07 02:49:21 PM PST 24
Peak memory 209468 kb
Host smart-45a23bd4-1bd8-4b5a-a93b-57868d633585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675521896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.675521896
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.4078729352
Short name T380
Test name
Test status
Simulation time 77124439 ps
CPU time 1.5 seconds
Started Mar 07 02:49:23 PM PST 24
Finished Mar 07 02:49:25 PM PST 24
Peak memory 210024 kb
Host smart-da147069-673b-4567-ae1e-1226836ff4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078729352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.4078729352
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.4039098483
Short name T760
Test name
Test status
Simulation time 36723593 ps
CPU time 0.72 seconds
Started Mar 07 02:49:18 PM PST 24
Finished Mar 07 02:49:19 PM PST 24
Peak memory 206132 kb
Host smart-6a9cda42-8bf3-47cc-9c00-bad074b9ff05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039098483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.4039098483
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1815394707
Short name T893
Test name
Test status
Simulation time 457536333 ps
CPU time 3.63 seconds
Started Mar 07 02:49:18 PM PST 24
Finished Mar 07 02:49:22 PM PST 24
Peak memory 209972 kb
Host smart-da257a8a-3965-486b-99b1-8e30743bc7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815394707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1815394707
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1687230507
Short name T663
Test name
Test status
Simulation time 32131346 ps
CPU time 2.11 seconds
Started Mar 07 02:49:21 PM PST 24
Finished Mar 07 02:49:23 PM PST 24
Peak memory 214444 kb
Host smart-9dbcb26c-af14-4894-bd95-7b9dfd7d46e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687230507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1687230507
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.4145620399
Short name T707
Test name
Test status
Simulation time 1083743743 ps
CPU time 14.19 seconds
Started Mar 07 02:49:24 PM PST 24
Finished Mar 07 02:49:39 PM PST 24
Peak memory 209500 kb
Host smart-4f22a01e-654b-4f7d-8edc-65c90d43d9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145620399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.4145620399
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1469075583
Short name T417
Test name
Test status
Simulation time 448118838 ps
CPU time 12.8 seconds
Started Mar 07 02:49:22 PM PST 24
Finished Mar 07 02:49:36 PM PST 24
Peak memory 211736 kb
Host smart-fee1bfe2-1c75-4810-b82b-bbc9dccc08ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469075583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1469075583
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1429507049
Short name T562
Test name
Test status
Simulation time 366392892 ps
CPU time 3.62 seconds
Started Mar 07 02:49:19 PM PST 24
Finished Mar 07 02:49:23 PM PST 24
Peak memory 210256 kb
Host smart-f408731b-7752-4147-a403-fcb06a5e49d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429507049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1429507049
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.955939777
Short name T273
Test name
Test status
Simulation time 749031508 ps
CPU time 6.69 seconds
Started Mar 07 02:49:26 PM PST 24
Finished Mar 07 02:49:33 PM PST 24
Peak memory 210168 kb
Host smart-85b96a29-1277-4578-8b9b-bae622b5e11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955939777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.955939777
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.357829246
Short name T249
Test name
Test status
Simulation time 985173043 ps
CPU time 7.09 seconds
Started Mar 07 02:49:18 PM PST 24
Finished Mar 07 02:49:25 PM PST 24
Peak memory 207916 kb
Host smart-e0e40630-dd61-4103-9e47-ed26a869bbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357829246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.357829246
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1297601939
Short name T294
Test name
Test status
Simulation time 524939965 ps
CPU time 7.54 seconds
Started Mar 07 02:49:18 PM PST 24
Finished Mar 07 02:49:27 PM PST 24
Peak memory 207764 kb
Host smart-9f49a849-9040-4c45-98b9-548793e6e539
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297601939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1297601939
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3696432413
Short name T517
Test name
Test status
Simulation time 80755944 ps
CPU time 3.77 seconds
Started Mar 07 02:49:19 PM PST 24
Finished Mar 07 02:49:23 PM PST 24
Peak memory 208796 kb
Host smart-61fe130c-d8f3-42fa-bd1c-d4f56cf2cb1f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696432413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3696432413
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3568927237
Short name T702
Test name
Test status
Simulation time 289930195 ps
CPU time 3.95 seconds
Started Mar 07 02:49:18 PM PST 24
Finished Mar 07 02:49:23 PM PST 24
Peak memory 220584 kb
Host smart-5b5ea135-6dcd-44c8-a9ba-ce98b7bf13b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568927237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3568927237
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.229014842
Short name T719
Test name
Test status
Simulation time 254927797 ps
CPU time 2.41 seconds
Started Mar 07 02:49:27 PM PST 24
Finished Mar 07 02:49:30 PM PST 24
Peak memory 206640 kb
Host smart-9526a852-dd50-4507-b170-dc61c66ef4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229014842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.229014842
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.4216135020
Short name T560
Test name
Test status
Simulation time 13613607998 ps
CPU time 26.14 seconds
Started Mar 07 02:49:25 PM PST 24
Finished Mar 07 02:49:51 PM PST 24
Peak memory 209532 kb
Host smart-cddc562c-ce75-4d26-a4f4-edc4b3d47b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216135020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.4216135020
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2413426714
Short name T137
Test name
Test status
Simulation time 292217188 ps
CPU time 2.58 seconds
Started Mar 07 02:49:17 PM PST 24
Finished Mar 07 02:49:20 PM PST 24
Peak memory 210256 kb
Host smart-e8fc4f08-6776-48e9-9105-867434754c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413426714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2413426714
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.848684226
Short name T749
Test name
Test status
Simulation time 37446744 ps
CPU time 0.77 seconds
Started Mar 07 02:49:27 PM PST 24
Finished Mar 07 02:49:28 PM PST 24
Peak memory 206100 kb
Host smart-d1905aae-6dc6-43a2-866e-81595527a28d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848684226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.848684226
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.549811924
Short name T33
Test name
Test status
Simulation time 1572988941 ps
CPU time 4.96 seconds
Started Mar 07 02:49:26 PM PST 24
Finished Mar 07 02:49:31 PM PST 24
Peak memory 222912 kb
Host smart-ea01b802-e778-44fd-8c60-c2f27e3ed9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549811924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.549811924
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1885515051
Short name T686
Test name
Test status
Simulation time 509899427 ps
CPU time 4.64 seconds
Started Mar 07 02:49:26 PM PST 24
Finished Mar 07 02:49:31 PM PST 24
Peak memory 210092 kb
Host smart-0d8103c2-d1c7-4983-9380-4a0597a9caef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885515051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1885515051
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.868337267
Short name T351
Test name
Test status
Simulation time 1982261999 ps
CPU time 10.82 seconds
Started Mar 07 02:49:24 PM PST 24
Finished Mar 07 02:49:36 PM PST 24
Peak memory 209796 kb
Host smart-ef95115f-6714-4c2b-a040-9732f54a02ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868337267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.868337267
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3760772494
Short name T285
Test name
Test status
Simulation time 199325466 ps
CPU time 6 seconds
Started Mar 07 02:49:26 PM PST 24
Finished Mar 07 02:49:32 PM PST 24
Peak memory 222636 kb
Host smart-906a2d2b-2085-4986-a85e-96299e3aa658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760772494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3760772494
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3199069466
Short name T748
Test name
Test status
Simulation time 84665157 ps
CPU time 3.12 seconds
Started Mar 07 02:49:20 PM PST 24
Finished Mar 07 02:49:24 PM PST 24
Peak memory 220516 kb
Host smart-5291df36-ae8d-43c4-9eaa-2c88ff3e5833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199069466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3199069466
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.275400531
Short name T819
Test name
Test status
Simulation time 134211329 ps
CPU time 3.42 seconds
Started Mar 07 02:49:25 PM PST 24
Finished Mar 07 02:49:29 PM PST 24
Peak memory 214428 kb
Host smart-54ef19d9-f4be-4b1f-a86a-7eb3d4421a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275400531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.275400531
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.4058298772
Short name T552
Test name
Test status
Simulation time 149550052 ps
CPU time 2.3 seconds
Started Mar 07 02:49:19 PM PST 24
Finished Mar 07 02:49:22 PM PST 24
Peak memory 206804 kb
Host smart-c73cb26e-1fb9-41cb-b21e-aa768ffa6722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058298772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.4058298772
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3760669009
Short name T272
Test name
Test status
Simulation time 24348202 ps
CPU time 1.93 seconds
Started Mar 07 02:49:20 PM PST 24
Finished Mar 07 02:49:23 PM PST 24
Peak memory 207372 kb
Host smart-5519676b-7abf-4479-a882-f2a25bccb858
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760669009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3760669009
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3553304884
Short name T455
Test name
Test status
Simulation time 7785484389 ps
CPU time 54.91 seconds
Started Mar 07 02:49:18 PM PST 24
Finished Mar 07 02:50:14 PM PST 24
Peak memory 208476 kb
Host smart-01ec9c50-c437-44e3-ad32-9b1fe80ac251
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553304884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3553304884
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1436668392
Short name T449
Test name
Test status
Simulation time 52842935 ps
CPU time 2.41 seconds
Started Mar 07 02:49:22 PM PST 24
Finished Mar 07 02:49:25 PM PST 24
Peak memory 209044 kb
Host smart-2c9e9901-6b6e-49b8-af01-6b89fa5cdab7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436668392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1436668392
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3276794771
Short name T150
Test name
Test status
Simulation time 77893591 ps
CPU time 1.91 seconds
Started Mar 07 02:49:28 PM PST 24
Finished Mar 07 02:49:30 PM PST 24
Peak memory 208484 kb
Host smart-7d48a9aa-946e-4c0e-916b-1f53aa57a80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276794771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3276794771
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1063717127
Short name T427
Test name
Test status
Simulation time 563385174 ps
CPU time 4.13 seconds
Started Mar 07 02:49:24 PM PST 24
Finished Mar 07 02:49:29 PM PST 24
Peak memory 206832 kb
Host smart-ebe1acb2-d84a-42b0-beee-e480dc8ad300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063717127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1063717127
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.687383119
Short name T737
Test name
Test status
Simulation time 529734412 ps
CPU time 4.73 seconds
Started Mar 07 02:49:26 PM PST 24
Finished Mar 07 02:49:31 PM PST 24
Peak memory 208832 kb
Host smart-46353aed-32a0-4583-9186-895c15f007d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687383119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.687383119
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2128952155
Short name T256
Test name
Test status
Simulation time 82317074 ps
CPU time 4.02 seconds
Started Mar 07 02:49:27 PM PST 24
Finished Mar 07 02:49:31 PM PST 24
Peak memory 207068 kb
Host smart-d5716e23-e663-4bd5-8194-0645673edabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128952155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2128952155
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.444339504
Short name T810
Test name
Test status
Simulation time 56146459 ps
CPU time 1.35 seconds
Started Mar 07 02:49:26 PM PST 24
Finished Mar 07 02:49:28 PM PST 24
Peak memory 209720 kb
Host smart-b92c9d3b-3a9c-4432-adfa-1f8ac6769c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444339504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.444339504
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2404733726
Short name T841
Test name
Test status
Simulation time 32719988 ps
CPU time 0.76 seconds
Started Mar 07 02:49:33 PM PST 24
Finished Mar 07 02:49:34 PM PST 24
Peak memory 206188 kb
Host smart-9c10dba5-80cd-40d3-b7c6-772d29b9ea8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404733726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2404733726
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3163713105
Short name T462
Test name
Test status
Simulation time 51086369 ps
CPU time 2.37 seconds
Started Mar 07 02:49:28 PM PST 24
Finished Mar 07 02:49:30 PM PST 24
Peak memory 207284 kb
Host smart-6bd8f99f-f67b-474c-9ebb-65584412efe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163713105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3163713105
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1392054173
Short name T348
Test name
Test status
Simulation time 409745121 ps
CPU time 5.36 seconds
Started Mar 07 02:49:28 PM PST 24
Finished Mar 07 02:49:34 PM PST 24
Peak memory 208540 kb
Host smart-d5753228-890f-4b43-82a0-1316e60e060d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392054173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1392054173
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.433893770
Short name T253
Test name
Test status
Simulation time 161371012 ps
CPU time 5.41 seconds
Started Mar 07 02:49:26 PM PST 24
Finished Mar 07 02:49:31 PM PST 24
Peak memory 214484 kb
Host smart-8241e160-747f-4622-8a55-522e62bd5f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433893770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.433893770
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.759074024
Short name T68
Test name
Test status
Simulation time 298984276 ps
CPU time 4.9 seconds
Started Mar 07 02:49:27 PM PST 24
Finished Mar 07 02:49:32 PM PST 24
Peak memory 217656 kb
Host smart-3696250c-8fd9-4af3-a936-d5544f8eb62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759074024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.759074024
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.350925294
Short name T340
Test name
Test status
Simulation time 268016767 ps
CPU time 3.95 seconds
Started Mar 07 02:49:27 PM PST 24
Finished Mar 07 02:49:31 PM PST 24
Peak memory 209968 kb
Host smart-3a6e63a1-12ac-4f2f-ae62-780bf0c20854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350925294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.350925294
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.435696775
Short name T310
Test name
Test status
Simulation time 795229667 ps
CPU time 7.45 seconds
Started Mar 07 02:49:28 PM PST 24
Finished Mar 07 02:49:36 PM PST 24
Peak memory 208576 kb
Host smart-7c4fc01a-1872-471b-8f19-a733a0cb6304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435696775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.435696775
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.4212539588
Short name T753
Test name
Test status
Simulation time 220773568 ps
CPU time 6.43 seconds
Started Mar 07 02:49:27 PM PST 24
Finished Mar 07 02:49:33 PM PST 24
Peak memory 208544 kb
Host smart-9d0886e1-4210-4af4-bee9-70a6931b5eb4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212539588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.4212539588
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.4284109510
Short name T255
Test name
Test status
Simulation time 403802078 ps
CPU time 4.95 seconds
Started Mar 07 02:49:32 PM PST 24
Finished Mar 07 02:49:38 PM PST 24
Peak memory 208592 kb
Host smart-bcd8b1dc-b5af-49ef-9897-c3c7975e8451
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284109510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.4284109510
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3637523632
Short name T437
Test name
Test status
Simulation time 6012286101 ps
CPU time 49.3 seconds
Started Mar 07 02:49:29 PM PST 24
Finished Mar 07 02:50:19 PM PST 24
Peak memory 208548 kb
Host smart-2ec2d442-7bcd-4a33-8f58-903b7e13ffdd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637523632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3637523632
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2797423147
Short name T853
Test name
Test status
Simulation time 280068661 ps
CPU time 2.64 seconds
Started Mar 07 02:49:28 PM PST 24
Finished Mar 07 02:49:31 PM PST 24
Peak memory 208140 kb
Host smart-c73c0316-5597-4845-b130-19355f8dcee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797423147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2797423147
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3930548368
Short name T529
Test name
Test status
Simulation time 175972059 ps
CPU time 3.61 seconds
Started Mar 07 02:49:26 PM PST 24
Finished Mar 07 02:49:30 PM PST 24
Peak memory 208596 kb
Host smart-192fc41a-a493-4512-bdde-5e6b3e11b55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930548368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3930548368
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1973077113
Short name T78
Test name
Test status
Simulation time 3396179412 ps
CPU time 85.81 seconds
Started Mar 07 02:49:32 PM PST 24
Finished Mar 07 02:50:58 PM PST 24
Peak memory 216152 kb
Host smart-6160f15c-4b0a-414a-b90c-a452b8c024e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973077113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1973077113
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1799897522
Short name T370
Test name
Test status
Simulation time 781732598 ps
CPU time 8.84 seconds
Started Mar 07 02:49:29 PM PST 24
Finished Mar 07 02:49:38 PM PST 24
Peak memory 208332 kb
Host smart-60f23d95-bef9-4d2f-a919-3ddb582b3a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799897522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1799897522
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.4192100808
Short name T472
Test name
Test status
Simulation time 41623460 ps
CPU time 1.97 seconds
Started Mar 07 02:49:31 PM PST 24
Finished Mar 07 02:49:34 PM PST 24
Peak memory 209576 kb
Host smart-2ba1c648-f5f6-4ec2-95d0-7a71fa26a880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192100808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.4192100808
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.606730200
Short name T774
Test name
Test status
Simulation time 47520967 ps
CPU time 0.86 seconds
Started Mar 07 02:49:41 PM PST 24
Finished Mar 07 02:49:42 PM PST 24
Peak memory 206172 kb
Host smart-bc60ef6e-2ee2-4bd4-a841-ad09565f534c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606730200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.606730200
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3390990354
Short name T424
Test name
Test status
Simulation time 860303185 ps
CPU time 11.6 seconds
Started Mar 07 02:49:30 PM PST 24
Finished Mar 07 02:49:42 PM PST 24
Peak memory 215564 kb
Host smart-cbd97ee9-6a56-41e6-908d-3b906db7315e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3390990354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3390990354
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2206063111
Short name T558
Test name
Test status
Simulation time 316464577 ps
CPU time 9.33 seconds
Started Mar 07 02:49:37 PM PST 24
Finished Mar 07 02:49:47 PM PST 24
Peak memory 217484 kb
Host smart-0bf49b84-2c4f-4dbe-8e3e-000a0ea117dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206063111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2206063111
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2457131461
Short name T61
Test name
Test status
Simulation time 416294849 ps
CPU time 3.32 seconds
Started Mar 07 02:49:34 PM PST 24
Finished Mar 07 02:49:38 PM PST 24
Peak memory 209032 kb
Host smart-b081a565-ca86-4bb2-99bc-1a4990526be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457131461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2457131461
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3372908766
Short name T93
Test name
Test status
Simulation time 861910838 ps
CPU time 4.9 seconds
Started Mar 07 02:49:34 PM PST 24
Finished Mar 07 02:49:39 PM PST 24
Peak memory 209976 kb
Host smart-362ad2c4-da1d-4bfe-869b-80c1ec3ad8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372908766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3372908766
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3590753888
Short name T837
Test name
Test status
Simulation time 116303050 ps
CPU time 3.09 seconds
Started Mar 07 02:49:35 PM PST 24
Finished Mar 07 02:49:38 PM PST 24
Peak memory 208440 kb
Host smart-5ccb39e7-3ac0-4255-b1f6-ddb1973823de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590753888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3590753888
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1023542876
Short name T735
Test name
Test status
Simulation time 264188089 ps
CPU time 7.61 seconds
Started Mar 07 02:49:33 PM PST 24
Finished Mar 07 02:49:42 PM PST 24
Peak memory 209448 kb
Host smart-9fc07ba6-0a73-4291-9bd2-1ca0442b2cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023542876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1023542876
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.539391065
Short name T390
Test name
Test status
Simulation time 316480960 ps
CPU time 6.41 seconds
Started Mar 07 02:49:36 PM PST 24
Finished Mar 07 02:49:42 PM PST 24
Peak memory 207912 kb
Host smart-9f7883e8-2949-4c55-bb76-0b1fd9ea0995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539391065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.539391065
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.454438598
Short name T782
Test name
Test status
Simulation time 93085223 ps
CPU time 1.94 seconds
Started Mar 07 02:49:36 PM PST 24
Finished Mar 07 02:49:38 PM PST 24
Peak memory 208976 kb
Host smart-d111fe9e-c1c9-4f75-83ed-06737ce65b1b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454438598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.454438598
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1414208081
Short name T599
Test name
Test status
Simulation time 92280634 ps
CPU time 2.38 seconds
Started Mar 07 02:49:35 PM PST 24
Finished Mar 07 02:49:38 PM PST 24
Peak memory 207956 kb
Host smart-614fdbd7-37b9-4e26-8885-08a5ced47720
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414208081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1414208081
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.589114493
Short name T496
Test name
Test status
Simulation time 1021054593 ps
CPU time 5.78 seconds
Started Mar 07 02:49:35 PM PST 24
Finished Mar 07 02:49:41 PM PST 24
Peak memory 206080 kb
Host smart-c36982ff-bf63-4664-a0e1-d5a6ce382db4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589114493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.589114493
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1987898260
Short name T821
Test name
Test status
Simulation time 180882920 ps
CPU time 5.45 seconds
Started Mar 07 02:49:36 PM PST 24
Finished Mar 07 02:49:42 PM PST 24
Peak memory 218364 kb
Host smart-9ec94771-3a9b-49fc-ad27-3cbe7ae563c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987898260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1987898260
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2841426234
Short name T716
Test name
Test status
Simulation time 450635381 ps
CPU time 4.87 seconds
Started Mar 07 02:49:34 PM PST 24
Finished Mar 07 02:49:39 PM PST 24
Peak memory 206776 kb
Host smart-3df9e71f-267a-4bbd-b7e1-dd7c4ebef3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841426234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2841426234
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3438330429
Short name T236
Test name
Test status
Simulation time 1952255222 ps
CPU time 22.72 seconds
Started Mar 07 02:49:41 PM PST 24
Finished Mar 07 02:50:04 PM PST 24
Peak memory 215944 kb
Host smart-1d4b905a-7288-4084-8e21-9e75b4dc8bb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438330429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3438330429
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2423507879
Short name T814
Test name
Test status
Simulation time 498641951 ps
CPU time 4.66 seconds
Started Mar 07 02:49:32 PM PST 24
Finished Mar 07 02:49:37 PM PST 24
Peak memory 207520 kb
Host smart-400422da-184b-41ad-8cb2-42cf24855c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423507879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2423507879
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2132037763
Short name T849
Test name
Test status
Simulation time 31101881 ps
CPU time 2.07 seconds
Started Mar 07 02:49:31 PM PST 24
Finished Mar 07 02:49:34 PM PST 24
Peak memory 210040 kb
Host smart-5555c689-cea7-4746-a83a-39ce514dc57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132037763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2132037763
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2383569236
Short name T827
Test name
Test status
Simulation time 35412408 ps
CPU time 0.78 seconds
Started Mar 07 02:47:57 PM PST 24
Finished Mar 07 02:47:58 PM PST 24
Peak memory 206184 kb
Host smart-efc2a81c-a640-4e09-a7a0-3a7423b9a7b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383569236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2383569236
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.4054112197
Short name T239
Test name
Test status
Simulation time 1889079367 ps
CPU time 14.63 seconds
Started Mar 07 02:47:59 PM PST 24
Finished Mar 07 02:48:14 PM PST 24
Peak memory 214876 kb
Host smart-9acd3d63-9461-477b-9835-c4cf20a73a11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4054112197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.4054112197
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.882429003
Short name T531
Test name
Test status
Simulation time 36927861 ps
CPU time 1.54 seconds
Started Mar 07 02:48:03 PM PST 24
Finished Mar 07 02:48:04 PM PST 24
Peak memory 209544 kb
Host smart-ab54833c-6c4f-4eb8-a777-0140e505e16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882429003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.882429003
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1143495335
Short name T532
Test name
Test status
Simulation time 174802620 ps
CPU time 2.6 seconds
Started Mar 07 02:48:03 PM PST 24
Finished Mar 07 02:48:06 PM PST 24
Peak memory 207980 kb
Host smart-ab6d92c0-9a81-41aa-86d6-a8387386f9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143495335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1143495335
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.728134150
Short name T300
Test name
Test status
Simulation time 147021148 ps
CPU time 6.14 seconds
Started Mar 07 02:47:57 PM PST 24
Finished Mar 07 02:48:04 PM PST 24
Peak memory 221960 kb
Host smart-ae098646-2005-403c-82ed-e89719165ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728134150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.728134150
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.420778609
Short name T832
Test name
Test status
Simulation time 154846235 ps
CPU time 4.17 seconds
Started Mar 07 02:48:03 PM PST 24
Finished Mar 07 02:48:07 PM PST 24
Peak memory 210132 kb
Host smart-dc89161b-9241-4871-9564-0da89248a68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420778609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.420778609
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1403937548
Short name T769
Test name
Test status
Simulation time 128693092 ps
CPU time 4.08 seconds
Started Mar 07 02:48:03 PM PST 24
Finished Mar 07 02:48:07 PM PST 24
Peak memory 218452 kb
Host smart-d7e3cf08-275f-4034-a021-8fa70efa2275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403937548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1403937548
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2437084253
Short name T11
Test name
Test status
Simulation time 283851175 ps
CPU time 10.11 seconds
Started Mar 07 02:47:58 PM PST 24
Finished Mar 07 02:48:08 PM PST 24
Peak memory 234272 kb
Host smart-9b146e8b-e171-4239-89eb-fa8e1bd4ba0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437084253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2437084253
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1347383601
Short name T541
Test name
Test status
Simulation time 519533736 ps
CPU time 4.5 seconds
Started Mar 07 02:47:59 PM PST 24
Finished Mar 07 02:48:04 PM PST 24
Peak memory 206792 kb
Host smart-7abef651-9b38-4f34-8b27-e1a6c19b489f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347383601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1347383601
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.753050051
Short name T701
Test name
Test status
Simulation time 1834918200 ps
CPU time 45.9 seconds
Started Mar 07 02:47:58 PM PST 24
Finished Mar 07 02:48:44 PM PST 24
Peak memory 208544 kb
Host smart-c1d05f74-177d-4af0-8df4-d19535687d7b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753050051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.753050051
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1204605581
Short name T630
Test name
Test status
Simulation time 146341016 ps
CPU time 5.28 seconds
Started Mar 07 02:47:58 PM PST 24
Finished Mar 07 02:48:03 PM PST 24
Peak memory 207924 kb
Host smart-7515ad87-50fc-43cb-9c2b-b873d5669c7d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204605581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1204605581
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2751427608
Short name T459
Test name
Test status
Simulation time 3435216639 ps
CPU time 9.57 seconds
Started Mar 07 02:47:57 PM PST 24
Finished Mar 07 02:48:07 PM PST 24
Peak memory 208716 kb
Host smart-20fb93ce-f93b-47ca-b080-29769c588acd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751427608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2751427608
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.176372382
Short name T349
Test name
Test status
Simulation time 27503109 ps
CPU time 1.89 seconds
Started Mar 07 02:47:56 PM PST 24
Finished Mar 07 02:47:59 PM PST 24
Peak memory 210008 kb
Host smart-52d9cfcf-57d6-45df-95d6-3aa3db2325c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176372382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.176372382
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.890660154
Short name T452
Test name
Test status
Simulation time 98334929 ps
CPU time 2.78 seconds
Started Mar 07 02:47:57 PM PST 24
Finished Mar 07 02:48:00 PM PST 24
Peak memory 206624 kb
Host smart-7e4fa18f-ccfd-4724-a4cd-f9da3f7bd0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890660154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.890660154
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2550618469
Short name T618
Test name
Test status
Simulation time 3913808478 ps
CPU time 39.4 seconds
Started Mar 07 02:48:01 PM PST 24
Finished Mar 07 02:48:41 PM PST 24
Peak memory 215984 kb
Host smart-897f34ec-4d59-4788-9d3c-3f2ac2b90524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550618469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2550618469
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.1005752799
Short name T778
Test name
Test status
Simulation time 217835871 ps
CPU time 7.58 seconds
Started Mar 07 02:47:57 PM PST 24
Finished Mar 07 02:48:05 PM PST 24
Peak memory 222824 kb
Host smart-d1c99d99-9d23-422a-98b9-3900a4d8b29c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005752799 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.1005752799
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.564476662
Short name T671
Test name
Test status
Simulation time 574311045 ps
CPU time 6.58 seconds
Started Mar 07 02:47:57 PM PST 24
Finished Mar 07 02:48:04 PM PST 24
Peak memory 214344 kb
Host smart-22410cca-85a5-44ba-85a0-0e0e82022da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564476662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.564476662
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3643442418
Short name T704
Test name
Test status
Simulation time 1004665501 ps
CPU time 8.88 seconds
Started Mar 07 02:48:00 PM PST 24
Finished Mar 07 02:48:09 PM PST 24
Peak memory 210812 kb
Host smart-cc755436-d379-4160-b7c5-c7df2b855b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643442418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3643442418
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1222053890
Short name T647
Test name
Test status
Simulation time 14981944 ps
CPU time 1.07 seconds
Started Mar 07 02:49:39 PM PST 24
Finished Mar 07 02:49:40 PM PST 24
Peak memory 206384 kb
Host smart-1db33cc6-e424-4a6d-af3c-e31c9dccd349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222053890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1222053890
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3071727100
Short name T142
Test name
Test status
Simulation time 116957624 ps
CPU time 2.94 seconds
Started Mar 07 02:49:41 PM PST 24
Finished Mar 07 02:49:44 PM PST 24
Peak memory 214540 kb
Host smart-b8049d95-847d-4402-908d-f5a22320a979
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3071727100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3071727100
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3740484377
Short name T693
Test name
Test status
Simulation time 24290549 ps
CPU time 1.77 seconds
Started Mar 07 02:49:42 PM PST 24
Finished Mar 07 02:49:44 PM PST 24
Peak memory 208384 kb
Host smart-b025ad02-1299-4430-aff9-87e4f9330e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740484377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3740484377
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2971186271
Short name T697
Test name
Test status
Simulation time 194863452 ps
CPU time 3.25 seconds
Started Mar 07 02:49:44 PM PST 24
Finished Mar 07 02:49:48 PM PST 24
Peak memory 219732 kb
Host smart-41760f99-341d-4391-b121-9948cbca8f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971186271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2971186271
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2153690037
Short name T343
Test name
Test status
Simulation time 902543363 ps
CPU time 8.83 seconds
Started Mar 07 02:49:41 PM PST 24
Finished Mar 07 02:49:50 PM PST 24
Peak memory 210908 kb
Host smart-7d1269f6-ecbd-477b-a3b0-c28ad2114497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153690037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2153690037
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.16053241
Short name T143
Test name
Test status
Simulation time 816925232 ps
CPU time 6.78 seconds
Started Mar 07 02:49:41 PM PST 24
Finished Mar 07 02:49:48 PM PST 24
Peak memory 214456 kb
Host smart-82c4012a-30af-4d2c-843a-7c7c17faa94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16053241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.16053241
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.469264504
Short name T3
Test name
Test status
Simulation time 94030252 ps
CPU time 3.27 seconds
Started Mar 07 02:49:42 PM PST 24
Finished Mar 07 02:49:45 PM PST 24
Peak memory 208180 kb
Host smart-3c8a6439-6e6a-48df-b227-1172a78f48f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469264504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.469264504
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.717422935
Short name T112
Test name
Test status
Simulation time 213993528 ps
CPU time 3.2 seconds
Started Mar 07 02:49:38 PM PST 24
Finished Mar 07 02:49:42 PM PST 24
Peak memory 208660 kb
Host smart-fb640e04-d1f8-473c-8b40-4a14a6cbd591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717422935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.717422935
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2852200550
Short name T243
Test name
Test status
Simulation time 199273249 ps
CPU time 2.69 seconds
Started Mar 07 02:49:44 PM PST 24
Finished Mar 07 02:49:47 PM PST 24
Peak memory 206780 kb
Host smart-309457c8-32cd-4818-afb6-01fa3c1a8d2b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852200550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2852200550
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2532172582
Short name T388
Test name
Test status
Simulation time 6605328510 ps
CPU time 68.83 seconds
Started Mar 07 02:49:39 PM PST 24
Finished Mar 07 02:50:48 PM PST 24
Peak memory 208432 kb
Host smart-2eda287e-0f2c-4d16-b723-e59e789d2caa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532172582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2532172582
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1701311130
Short name T337
Test name
Test status
Simulation time 297823094 ps
CPU time 4.24 seconds
Started Mar 07 02:49:41 PM PST 24
Finished Mar 07 02:49:46 PM PST 24
Peak memory 206816 kb
Host smart-163bd4c7-85d6-4ec1-aa65-966c74a65281
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701311130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1701311130
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2868639092
Short name T699
Test name
Test status
Simulation time 246692922 ps
CPU time 4.06 seconds
Started Mar 07 02:49:43 PM PST 24
Finished Mar 07 02:49:47 PM PST 24
Peak memory 209808 kb
Host smart-ad079be6-856f-4855-88ff-3b1aeb5edaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868639092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2868639092
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1621225173
Short name T208
Test name
Test status
Simulation time 1195544452 ps
CPU time 14.27 seconds
Started Mar 07 02:49:42 PM PST 24
Finished Mar 07 02:49:57 PM PST 24
Peak memory 208396 kb
Host smart-bb843549-e99b-408a-a3c3-c6d24b6d0607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621225173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1621225173
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3998354771
Short name T225
Test name
Test status
Simulation time 3257811355 ps
CPU time 48.55 seconds
Started Mar 07 02:49:42 PM PST 24
Finished Mar 07 02:50:30 PM PST 24
Peak memory 216448 kb
Host smart-7725c824-a788-4bdc-80e9-23088271adce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998354771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3998354771
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.4092413538
Short name T315
Test name
Test status
Simulation time 1591856115 ps
CPU time 8.28 seconds
Started Mar 07 02:49:42 PM PST 24
Finished Mar 07 02:49:50 PM PST 24
Peak memory 218700 kb
Host smart-92d94bfd-d7f1-44e6-8477-22da4454c68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092413538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.4092413538
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3612240322
Short name T876
Test name
Test status
Simulation time 195627583 ps
CPU time 3.73 seconds
Started Mar 07 02:49:42 PM PST 24
Finished Mar 07 02:49:46 PM PST 24
Peak memory 210308 kb
Host smart-7b290559-0c34-4f81-bd75-ec31370ebef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612240322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3612240322
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3816891674
Short name T658
Test name
Test status
Simulation time 38112872 ps
CPU time 0.72 seconds
Started Mar 07 02:49:52 PM PST 24
Finished Mar 07 02:49:53 PM PST 24
Peak memory 206112 kb
Host smart-29fbda91-7491-469d-a197-9e7a97e74df5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816891674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3816891674
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3455251510
Short name T386
Test name
Test status
Simulation time 102382287 ps
CPU time 5.82 seconds
Started Mar 07 02:49:49 PM PST 24
Finished Mar 07 02:49:56 PM PST 24
Peak memory 214528 kb
Host smart-5a0bbbec-c6d5-4ac2-8e5a-4460877686b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3455251510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3455251510
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2478926385
Short name T638
Test name
Test status
Simulation time 173942922 ps
CPU time 1.97 seconds
Started Mar 07 02:49:49 PM PST 24
Finished Mar 07 02:49:52 PM PST 24
Peak memory 207976 kb
Host smart-fe867ce1-aafc-4aa2-82cd-0f3245de2c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478926385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2478926385
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3143086133
Short name T94
Test name
Test status
Simulation time 437128865 ps
CPU time 4.84 seconds
Started Mar 07 02:49:55 PM PST 24
Finished Mar 07 02:50:00 PM PST 24
Peak memory 214516 kb
Host smart-f3e51ba5-7481-470a-915a-81bc07a434a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143086133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3143086133
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2565650614
Short name T491
Test name
Test status
Simulation time 124263689 ps
CPU time 5.95 seconds
Started Mar 07 02:49:48 PM PST 24
Finished Mar 07 02:49:54 PM PST 24
Peak memory 222640 kb
Host smart-b3d46d2e-7c7b-49a0-bcc7-59547f47f48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565650614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2565650614
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_random.534382855
Short name T412
Test name
Test status
Simulation time 80244958 ps
CPU time 3.82 seconds
Started Mar 07 02:49:47 PM PST 24
Finished Mar 07 02:49:51 PM PST 24
Peak memory 214508 kb
Host smart-73647024-1e81-4c47-80c6-0706ec93499d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534382855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.534382855
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2774287456
Short name T877
Test name
Test status
Simulation time 90581520 ps
CPU time 3.32 seconds
Started Mar 07 02:49:40 PM PST 24
Finished Mar 07 02:49:44 PM PST 24
Peak memory 208744 kb
Host smart-9ea2eb9b-17a6-4583-bfcb-2cededb9971f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774287456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2774287456
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2781644726
Short name T835
Test name
Test status
Simulation time 641730043 ps
CPU time 8.79 seconds
Started Mar 07 02:49:46 PM PST 24
Finished Mar 07 02:49:55 PM PST 24
Peak memory 208724 kb
Host smart-d174965e-e13e-489f-bdf7-330a3c208996
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781644726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2781644726
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.4088361994
Short name T527
Test name
Test status
Simulation time 238440303 ps
CPU time 3.23 seconds
Started Mar 07 02:49:42 PM PST 24
Finished Mar 07 02:49:45 PM PST 24
Peak memory 206752 kb
Host smart-76d302e7-2b82-4152-808b-6ef11dee5be3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088361994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.4088361994
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.290842535
Short name T601
Test name
Test status
Simulation time 1987097328 ps
CPU time 61.77 seconds
Started Mar 07 02:49:49 PM PST 24
Finished Mar 07 02:50:51 PM PST 24
Peak memory 208344 kb
Host smart-e0937d53-7966-49e8-bd10-3cc65dbef555
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290842535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.290842535
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2054508825
Short name T708
Test name
Test status
Simulation time 4015742397 ps
CPU time 10.93 seconds
Started Mar 07 02:49:51 PM PST 24
Finished Mar 07 02:50:03 PM PST 24
Peak memory 209200 kb
Host smart-0f87fc8e-6195-4615-8c5f-c4df8a3d8ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054508825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2054508825
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1847326831
Short name T523
Test name
Test status
Simulation time 74243305 ps
CPU time 2.79 seconds
Started Mar 07 02:49:44 PM PST 24
Finished Mar 07 02:49:47 PM PST 24
Peak memory 206832 kb
Host smart-4a019cd8-4aa8-4841-a876-f5b1e5712773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847326831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1847326831
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1381775629
Short name T681
Test name
Test status
Simulation time 2166856498 ps
CPU time 41.86 seconds
Started Mar 07 02:49:46 PM PST 24
Finished Mar 07 02:50:28 PM PST 24
Peak memory 215556 kb
Host smart-c32c6fc3-9931-4026-a816-a9a932578009
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381775629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1381775629
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2471907300
Short name T833
Test name
Test status
Simulation time 422829044 ps
CPU time 4.92 seconds
Started Mar 07 02:49:53 PM PST 24
Finished Mar 07 02:49:58 PM PST 24
Peak memory 207372 kb
Host smart-98280cd0-cac0-40ea-abec-93f0cbfc38ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471907300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2471907300
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2527546353
Short name T597
Test name
Test status
Simulation time 1405000511 ps
CPU time 5.22 seconds
Started Mar 07 02:49:48 PM PST 24
Finished Mar 07 02:49:54 PM PST 24
Peak memory 210308 kb
Host smart-e7a4e20d-b1ca-46fc-8886-4a5fb0d16a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527546353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2527546353
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2965662843
Short name T574
Test name
Test status
Simulation time 35466518 ps
CPU time 0.75 seconds
Started Mar 07 02:49:55 PM PST 24
Finished Mar 07 02:49:55 PM PST 24
Peak memory 206164 kb
Host smart-19f49d25-50a6-487a-81f9-dfb6fe6c51d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965662843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2965662843
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1341345696
Short name T405
Test name
Test status
Simulation time 237472642 ps
CPU time 7.26 seconds
Started Mar 07 02:49:56 PM PST 24
Finished Mar 07 02:50:03 PM PST 24
Peak memory 214332 kb
Host smart-f924e780-55be-47d8-9bbc-9ad02d1186f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1341345696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1341345696
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1301345856
Short name T22
Test name
Test status
Simulation time 438887241 ps
CPU time 3.51 seconds
Started Mar 07 02:50:00 PM PST 24
Finished Mar 07 02:50:03 PM PST 24
Peak memory 214700 kb
Host smart-b7819e0e-c43f-4bd7-bfac-d2b07dd8debf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301345856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1301345856
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1988833959
Short name T882
Test name
Test status
Simulation time 654003172 ps
CPU time 7.7 seconds
Started Mar 07 02:49:54 PM PST 24
Finished Mar 07 02:50:02 PM PST 24
Peak memory 214508 kb
Host smart-7abaee6f-154a-44b0-ae4b-1efd68da7e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988833959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1988833959
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1543629524
Short name T779
Test name
Test status
Simulation time 2164258959 ps
CPU time 15.5 seconds
Started Mar 07 02:49:54 PM PST 24
Finished Mar 07 02:50:09 PM PST 24
Peak memory 214572 kb
Host smart-b196efd7-c354-40ad-9fa1-d0ac2ae1d489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543629524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1543629524
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3597945481
Short name T37
Test name
Test status
Simulation time 1342747461 ps
CPU time 13.65 seconds
Started Mar 07 02:49:57 PM PST 24
Finished Mar 07 02:50:11 PM PST 24
Peak memory 210208 kb
Host smart-ab1bba97-a898-4701-bd83-faf3814beeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597945481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3597945481
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1659720532
Short name T6
Test name
Test status
Simulation time 57800142 ps
CPU time 2.5 seconds
Started Mar 07 02:49:54 PM PST 24
Finished Mar 07 02:49:57 PM PST 24
Peak memory 220268 kb
Host smart-218d968b-c177-4cc7-a90d-9d5a25fe7a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659720532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1659720532
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.4033756207
Short name T626
Test name
Test status
Simulation time 116384611 ps
CPU time 5.21 seconds
Started Mar 07 02:49:57 PM PST 24
Finished Mar 07 02:50:02 PM PST 24
Peak memory 209772 kb
Host smart-a3f79fe4-60a3-464a-884d-cc30b4151ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033756207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.4033756207
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.67559657
Short name T292
Test name
Test status
Simulation time 37397472 ps
CPU time 2.23 seconds
Started Mar 07 02:49:52 PM PST 24
Finished Mar 07 02:49:54 PM PST 24
Peak memory 206644 kb
Host smart-518d0258-f12f-49fd-a105-cea1bcdcf24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67559657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.67559657
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.4111130879
Short name T646
Test name
Test status
Simulation time 79071846 ps
CPU time 3.2 seconds
Started Mar 07 02:49:51 PM PST 24
Finished Mar 07 02:49:54 PM PST 24
Peak memory 208492 kb
Host smart-be412de7-e197-469e-a632-eadbacf531ed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111130879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.4111130879
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2947189954
Short name T587
Test name
Test status
Simulation time 36821839 ps
CPU time 2.31 seconds
Started Mar 07 02:49:52 PM PST 24
Finished Mar 07 02:49:54 PM PST 24
Peak memory 206788 kb
Host smart-3e267d08-e3d8-4834-ad81-aa45a3f4365f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947189954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2947189954
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2820664777
Short name T607
Test name
Test status
Simulation time 71976944 ps
CPU time 3.31 seconds
Started Mar 07 02:49:53 PM PST 24
Finished Mar 07 02:49:57 PM PST 24
Peak memory 208828 kb
Host smart-8c23ad1b-a871-462b-9c9a-55edcc89a588
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820664777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2820664777
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.702119077
Short name T438
Test name
Test status
Simulation time 45453997 ps
CPU time 2.35 seconds
Started Mar 07 02:49:56 PM PST 24
Finished Mar 07 02:49:58 PM PST 24
Peak memory 206836 kb
Host smart-3ba3e706-1021-4e30-aae8-060ba95af143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702119077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.702119077
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1837660952
Short name T212
Test name
Test status
Simulation time 77166555 ps
CPU time 3.3 seconds
Started Mar 07 02:49:48 PM PST 24
Finished Mar 07 02:49:52 PM PST 24
Peak memory 208568 kb
Host smart-41fff48e-e002-4f56-91e4-64b6d457e8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837660952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1837660952
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2424129653
Short name T589
Test name
Test status
Simulation time 9753444921 ps
CPU time 88.69 seconds
Started Mar 07 02:50:00 PM PST 24
Finished Mar 07 02:51:29 PM PST 24
Peak memory 217264 kb
Host smart-5092b48e-051f-41e2-ab00-9fadfea4108f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424129653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2424129653
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3963252122
Short name T501
Test name
Test status
Simulation time 584144105 ps
CPU time 5.78 seconds
Started Mar 07 02:49:54 PM PST 24
Finished Mar 07 02:50:00 PM PST 24
Peak memory 210448 kb
Host smart-7f9f9ea9-4079-493b-b77c-4609616678b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963252122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3963252122
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3409810759
Short name T54
Test name
Test status
Simulation time 170683315 ps
CPU time 2.34 seconds
Started Mar 07 02:50:02 PM PST 24
Finished Mar 07 02:50:04 PM PST 24
Peak memory 210384 kb
Host smart-9daa0a5a-68b2-4f5b-bf15-923ae0f08122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409810759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3409810759
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.467800936
Short name T554
Test name
Test status
Simulation time 57042210 ps
CPU time 0.77 seconds
Started Mar 07 02:50:01 PM PST 24
Finished Mar 07 02:50:02 PM PST 24
Peak memory 206172 kb
Host smart-06575642-f004-47a1-a997-b719b78b6449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467800936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.467800936
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3267006503
Short name T9
Test name
Test status
Simulation time 314112105 ps
CPU time 4.28 seconds
Started Mar 07 02:50:01 PM PST 24
Finished Mar 07 02:50:05 PM PST 24
Peak memory 214728 kb
Host smart-62f2dfe2-eb5a-4815-a749-9bf5a7fef6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267006503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3267006503
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2749553414
Short name T550
Test name
Test status
Simulation time 58931788 ps
CPU time 2.69 seconds
Started Mar 07 02:50:02 PM PST 24
Finished Mar 07 02:50:04 PM PST 24
Peak memory 207972 kb
Host smart-515b82af-07e9-4d0d-8123-9e905693ee73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749553414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2749553414
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2882520345
Short name T582
Test name
Test status
Simulation time 521429788 ps
CPU time 4.82 seconds
Started Mar 07 02:50:01 PM PST 24
Finished Mar 07 02:50:06 PM PST 24
Peak memory 208768 kb
Host smart-00b7b06e-ee20-4a13-8e1b-4b9a63970301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882520345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2882520345
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2092909811
Short name T81
Test name
Test status
Simulation time 258406972 ps
CPU time 2.19 seconds
Started Mar 07 02:50:03 PM PST 24
Finished Mar 07 02:50:05 PM PST 24
Peak memory 209772 kb
Host smart-95041c91-b93b-4b06-a48c-f7f3979d2440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092909811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2092909811
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3330388314
Short name T709
Test name
Test status
Simulation time 120863789 ps
CPU time 4.87 seconds
Started Mar 07 02:50:05 PM PST 24
Finished Mar 07 02:50:10 PM PST 24
Peak memory 209468 kb
Host smart-a3b1bf34-28b7-48da-a628-c52022c579db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330388314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3330388314
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.4010221720
Short name T809
Test name
Test status
Simulation time 229213265 ps
CPU time 3.46 seconds
Started Mar 07 02:49:52 PM PST 24
Finished Mar 07 02:49:56 PM PST 24
Peak memory 207920 kb
Host smart-0889883c-31ab-4c03-86c4-7d65641636a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010221720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.4010221720
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3798216564
Short name T571
Test name
Test status
Simulation time 79476313 ps
CPU time 3.66 seconds
Started Mar 07 02:50:03 PM PST 24
Finished Mar 07 02:50:07 PM PST 24
Peak memory 208000 kb
Host smart-4babfb74-a78e-4737-a51b-3524c32aa28e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798216564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3798216564
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3699752367
Short name T593
Test name
Test status
Simulation time 212761062 ps
CPU time 6.07 seconds
Started Mar 07 02:50:00 PM PST 24
Finished Mar 07 02:50:06 PM PST 24
Peak memory 207968 kb
Host smart-f3da91d4-501b-44f0-b2c8-a98559dfddbf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699752367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3699752367
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1749582515
Short name T453
Test name
Test status
Simulation time 1775045520 ps
CPU time 55.23 seconds
Started Mar 07 02:50:02 PM PST 24
Finished Mar 07 02:50:57 PM PST 24
Peak memory 209152 kb
Host smart-8d233b05-6c0f-4a2f-8ebe-1b8c88c1d112
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749582515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1749582515
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.4179720097
Short name T288
Test name
Test status
Simulation time 217081279 ps
CPU time 3.35 seconds
Started Mar 07 02:50:02 PM PST 24
Finished Mar 07 02:50:05 PM PST 24
Peak memory 208340 kb
Host smart-d88d4ab0-1fa9-46bf-9e0c-9b8912f1ad93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179720097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.4179720097
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3718120690
Short name T467
Test name
Test status
Simulation time 139300503 ps
CPU time 3.5 seconds
Started Mar 07 02:49:57 PM PST 24
Finished Mar 07 02:50:01 PM PST 24
Peak memory 208616 kb
Host smart-89e4c54d-1532-4f40-8845-9df837783485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718120690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3718120690
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1375742734
Short name T441
Test name
Test status
Simulation time 385990451 ps
CPU time 3.85 seconds
Started Mar 07 02:50:01 PM PST 24
Finished Mar 07 02:50:05 PM PST 24
Peak memory 209740 kb
Host smart-bfa4af7f-df7b-4710-a0f1-87cd7966f3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375742734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1375742734
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1285018890
Short name T573
Test name
Test status
Simulation time 248283731 ps
CPU time 3.24 seconds
Started Mar 07 02:50:03 PM PST 24
Finished Mar 07 02:50:06 PM PST 24
Peak memory 209760 kb
Host smart-0ce401f2-1082-40c5-9fc2-638aed0169e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285018890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1285018890
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.470386523
Short name T692
Test name
Test status
Simulation time 13842567 ps
CPU time 0.73 seconds
Started Mar 07 02:50:09 PM PST 24
Finished Mar 07 02:50:10 PM PST 24
Peak memory 206128 kb
Host smart-f05fa54d-1a85-496d-9dbc-4acc02c88c48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470386523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.470386523
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1394678356
Short name T857
Test name
Test status
Simulation time 329065415 ps
CPU time 18.61 seconds
Started Mar 07 02:50:02 PM PST 24
Finished Mar 07 02:50:21 PM PST 24
Peak memory 214880 kb
Host smart-9075cfe7-6642-49ba-9c18-79c86ec419c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1394678356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1394678356
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3028253402
Short name T890
Test name
Test status
Simulation time 1133273902 ps
CPU time 3.19 seconds
Started Mar 07 02:50:07 PM PST 24
Finished Mar 07 02:50:10 PM PST 24
Peak memory 207088 kb
Host smart-40b1eda3-3689-48cf-b995-f7a918265f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028253402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3028253402
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1616337622
Short name T871
Test name
Test status
Simulation time 915673442 ps
CPU time 9.57 seconds
Started Mar 07 02:50:09 PM PST 24
Finished Mar 07 02:50:18 PM PST 24
Peak memory 208824 kb
Host smart-bbf2afe1-e3d4-4374-9804-e77c2c38dfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616337622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1616337622
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2294144512
Short name T542
Test name
Test status
Simulation time 940843234 ps
CPU time 12.21 seconds
Started Mar 07 02:50:08 PM PST 24
Finished Mar 07 02:50:21 PM PST 24
Peak memory 211004 kb
Host smart-f417fa23-0606-4b9e-98fa-12940fa9f94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294144512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2294144512
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3320616707
Short name T872
Test name
Test status
Simulation time 123493136 ps
CPU time 4.55 seconds
Started Mar 07 02:50:07 PM PST 24
Finished Mar 07 02:50:11 PM PST 24
Peak memory 209704 kb
Host smart-d4387b94-0e7b-43cf-ab38-a51d7dc33f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320616707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3320616707
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.634873256
Short name T321
Test name
Test status
Simulation time 109640747 ps
CPU time 5.36 seconds
Started Mar 07 02:50:03 PM PST 24
Finished Mar 07 02:50:08 PM PST 24
Peak memory 222724 kb
Host smart-9103fcf4-3c17-4c9b-81ce-3e909b9adfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634873256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.634873256
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2267560088
Short name T649
Test name
Test status
Simulation time 438321764 ps
CPU time 2.85 seconds
Started Mar 07 02:50:00 PM PST 24
Finished Mar 07 02:50:03 PM PST 24
Peak memory 208788 kb
Host smart-675b3de7-5aa3-4500-b024-1e1bd50de161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267560088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2267560088
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1257506468
Short name T139
Test name
Test status
Simulation time 320369500 ps
CPU time 2.72 seconds
Started Mar 07 02:50:01 PM PST 24
Finished Mar 07 02:50:04 PM PST 24
Peak memory 206928 kb
Host smart-b6a9915d-1d40-4613-9a8a-dff68f6b18b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257506468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1257506468
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1075735304
Short name T822
Test name
Test status
Simulation time 32410250 ps
CPU time 2.38 seconds
Started Mar 07 02:50:04 PM PST 24
Finished Mar 07 02:50:07 PM PST 24
Peak memory 207308 kb
Host smart-0522b932-6380-4784-bd15-a4b172d8acd4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075735304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1075735304
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3211117767
Short name T798
Test name
Test status
Simulation time 183750548 ps
CPU time 2.55 seconds
Started Mar 07 02:50:03 PM PST 24
Finished Mar 07 02:50:06 PM PST 24
Peak memory 206888 kb
Host smart-03e71870-6e72-4034-ba7e-900b2d09c670
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211117767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3211117767
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1560725632
Short name T536
Test name
Test status
Simulation time 56873227 ps
CPU time 2.57 seconds
Started Mar 07 02:50:08 PM PST 24
Finished Mar 07 02:50:11 PM PST 24
Peak memory 210164 kb
Host smart-795f83da-2ef4-4b21-abae-38b19c9066c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560725632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1560725632
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.116581549
Short name T695
Test name
Test status
Simulation time 1413011486 ps
CPU time 14.79 seconds
Started Mar 07 02:50:01 PM PST 24
Finished Mar 07 02:50:16 PM PST 24
Peak memory 208308 kb
Host smart-f1314a1e-4595-4e64-8420-1ea4bc573fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116581549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.116581549
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3366205034
Short name T667
Test name
Test status
Simulation time 2171939051 ps
CPU time 10.96 seconds
Started Mar 07 02:50:12 PM PST 24
Finished Mar 07 02:50:23 PM PST 24
Peak memory 208868 kb
Host smart-00a4b28d-a5e8-4c0c-a46d-facea974cc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366205034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3366205034
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1163448540
Short name T642
Test name
Test status
Simulation time 798184119 ps
CPU time 4.28 seconds
Started Mar 07 02:50:09 PM PST 24
Finished Mar 07 02:50:14 PM PST 24
Peak memory 210856 kb
Host smart-7b499b25-6b8d-4900-89f5-50592ac4253d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163448540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1163448540
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.748706579
Short name T687
Test name
Test status
Simulation time 21268502 ps
CPU time 0.75 seconds
Started Mar 07 02:50:18 PM PST 24
Finished Mar 07 02:50:19 PM PST 24
Peak memory 206168 kb
Host smart-622696d2-4b54-4596-899f-46e6f9397cca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748706579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.748706579
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2589605170
Short name T404
Test name
Test status
Simulation time 585213907 ps
CPU time 4.17 seconds
Started Mar 07 02:50:17 PM PST 24
Finished Mar 07 02:50:21 PM PST 24
Peak memory 214516 kb
Host smart-f9390726-9d66-4dc5-84e7-1c8302bb54d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2589605170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2589605170
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1281052745
Short name T539
Test name
Test status
Simulation time 673995058 ps
CPU time 4.59 seconds
Started Mar 07 02:50:23 PM PST 24
Finished Mar 07 02:50:27 PM PST 24
Peak memory 214792 kb
Host smart-6c77eaaa-efc4-470c-9467-d690cfde8206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281052745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1281052745
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1546721212
Short name T751
Test name
Test status
Simulation time 130754122 ps
CPU time 2.65 seconds
Started Mar 07 02:50:15 PM PST 24
Finished Mar 07 02:50:18 PM PST 24
Peak memory 208364 kb
Host smart-87c7923f-38df-48a2-b7bf-180f188d52c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546721212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1546721212
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.2436858961
Short name T605
Test name
Test status
Simulation time 33879516 ps
CPU time 2.34 seconds
Started Mar 07 02:50:22 PM PST 24
Finished Mar 07 02:50:24 PM PST 24
Peak memory 209404 kb
Host smart-7b50dbf7-6f17-4dfe-b789-82d796a3e01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436858961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2436858961
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.452138201
Short name T498
Test name
Test status
Simulation time 695514599 ps
CPU time 2.14 seconds
Started Mar 07 02:50:17 PM PST 24
Finished Mar 07 02:50:19 PM PST 24
Peak memory 219876 kb
Host smart-1ade1427-3c1d-48f0-9217-a8ae6c74503d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452138201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.452138201
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2648162301
Short name T659
Test name
Test status
Simulation time 66420328 ps
CPU time 3.23 seconds
Started Mar 07 02:50:11 PM PST 24
Finished Mar 07 02:50:14 PM PST 24
Peak memory 208032 kb
Host smart-1221006b-634b-4267-b137-1a55aa41f994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648162301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2648162301
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3886270072
Short name T570
Test name
Test status
Simulation time 200719605 ps
CPU time 5.93 seconds
Started Mar 07 02:50:15 PM PST 24
Finished Mar 07 02:50:21 PM PST 24
Peak memory 208540 kb
Host smart-7705890c-9bde-4556-b9ad-def0f973d833
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886270072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3886270072
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3017523077
Short name T887
Test name
Test status
Simulation time 253331644 ps
CPU time 3.15 seconds
Started Mar 07 02:50:10 PM PST 24
Finished Mar 07 02:50:13 PM PST 24
Peak memory 208628 kb
Host smart-563c91d1-d470-4cd1-8be4-1d1a02275f6d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017523077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3017523077
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3330010342
Short name T314
Test name
Test status
Simulation time 275318319 ps
CPU time 3.69 seconds
Started Mar 07 02:50:08 PM PST 24
Finished Mar 07 02:50:11 PM PST 24
Peak memory 208848 kb
Host smart-1813f5b4-d1d6-4a5d-90ed-30971c202aef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330010342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3330010342
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1923951575
Short name T109
Test name
Test status
Simulation time 240546131 ps
CPU time 2.18 seconds
Started Mar 07 02:50:18 PM PST 24
Finished Mar 07 02:50:20 PM PST 24
Peak memory 208144 kb
Host smart-12021419-d9c8-40e2-8a73-e92e5b20e347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923951575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1923951575
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3345270156
Short name T612
Test name
Test status
Simulation time 200324769 ps
CPU time 4.46 seconds
Started Mar 07 02:50:08 PM PST 24
Finished Mar 07 02:50:12 PM PST 24
Peak memory 208540 kb
Host smart-30b5652f-583e-425f-abc3-3c332e8fa903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345270156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3345270156
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3889674597
Short name T130
Test name
Test status
Simulation time 1612153102 ps
CPU time 15.66 seconds
Started Mar 07 02:50:21 PM PST 24
Finished Mar 07 02:50:36 PM PST 24
Peak memory 222808 kb
Host smart-12d02d78-a713-439c-b962-de23872641cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889674597 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3889674597
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.4038494210
Short name T242
Test name
Test status
Simulation time 81802225 ps
CPU time 3.67 seconds
Started Mar 07 02:50:19 PM PST 24
Finished Mar 07 02:50:23 PM PST 24
Peak memory 207572 kb
Host smart-8b387e9d-3544-42d6-a432-4ad5b634ab37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038494210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.4038494210
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2876267460
Short name T203
Test name
Test status
Simulation time 362938378 ps
CPU time 3.06 seconds
Started Mar 07 02:50:17 PM PST 24
Finished Mar 07 02:50:20 PM PST 24
Peak memory 210092 kb
Host smart-fd68ae61-9adc-44bd-b7a4-86741dcae8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876267460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2876267460
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.689384519
Short name T428
Test name
Test status
Simulation time 37479602 ps
CPU time 0.77 seconds
Started Mar 07 02:50:27 PM PST 24
Finished Mar 07 02:50:28 PM PST 24
Peak memory 206160 kb
Host smart-6b66999a-e4eb-4ec1-97bf-d2059a7e64b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689384519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.689384519
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.404240355
Short name T520
Test name
Test status
Simulation time 241894397 ps
CPU time 4.3 seconds
Started Mar 07 02:50:26 PM PST 24
Finished Mar 07 02:50:30 PM PST 24
Peak memory 218320 kb
Host smart-7920e62b-fe04-404e-81dc-a9c31bd6ca66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404240355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.404240355
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.318993683
Short name T759
Test name
Test status
Simulation time 205720858 ps
CPU time 1.75 seconds
Started Mar 07 02:50:24 PM PST 24
Finished Mar 07 02:50:26 PM PST 24
Peak memory 206772 kb
Host smart-6ca4f267-55c8-4c8a-bcff-a1f558c19b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318993683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.318993683
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2149768533
Short name T797
Test name
Test status
Simulation time 341229372 ps
CPU time 4.1 seconds
Started Mar 07 02:50:26 PM PST 24
Finished Mar 07 02:50:30 PM PST 24
Peak memory 219300 kb
Host smart-24658f35-7206-4587-90bd-6bbb008dde7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149768533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2149768533
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.4115548493
Short name T298
Test name
Test status
Simulation time 451906027 ps
CPU time 6.17 seconds
Started Mar 07 02:50:24 PM PST 24
Finished Mar 07 02:50:30 PM PST 24
Peak memory 222640 kb
Host smart-d437d008-e712-4f09-93f1-7203ce60f1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115548493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.4115548493
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.4175528247
Short name T764
Test name
Test status
Simulation time 104445953 ps
CPU time 3.42 seconds
Started Mar 07 02:50:23 PM PST 24
Finished Mar 07 02:50:27 PM PST 24
Peak memory 209904 kb
Host smart-3bba0787-80b6-49f1-9757-f600ea9190e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175528247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.4175528247
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1256567063
Short name T197
Test name
Test status
Simulation time 1538071793 ps
CPU time 21.17 seconds
Started Mar 07 02:50:22 PM PST 24
Finished Mar 07 02:50:44 PM PST 24
Peak memory 218484 kb
Host smart-ce6ab070-5c7a-4fc1-ad79-2a9db8b9bcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256567063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1256567063
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1433271900
Short name T820
Test name
Test status
Simulation time 122239341 ps
CPU time 2.6 seconds
Started Mar 07 02:50:18 PM PST 24
Finished Mar 07 02:50:21 PM PST 24
Peak memory 207412 kb
Host smart-43f0d0bb-1e34-470f-ade8-84deebe01acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433271900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1433271900
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1517300329
Short name T440
Test name
Test status
Simulation time 2263867206 ps
CPU time 8.01 seconds
Started Mar 07 02:50:18 PM PST 24
Finished Mar 07 02:50:26 PM PST 24
Peak memory 208136 kb
Host smart-da7672c5-1a7a-45c6-b619-a4053e445bae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517300329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1517300329
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2980358620
Short name T468
Test name
Test status
Simulation time 999911762 ps
CPU time 7.53 seconds
Started Mar 07 02:50:20 PM PST 24
Finished Mar 07 02:50:28 PM PST 24
Peak memory 208480 kb
Host smart-2d6da003-d85a-4b21-9f01-65d21603f13b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980358620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2980358620
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3204004776
Short name T17
Test name
Test status
Simulation time 207400528 ps
CPU time 2.95 seconds
Started Mar 07 02:50:27 PM PST 24
Finished Mar 07 02:50:30 PM PST 24
Peak memory 208740 kb
Host smart-a86b8fa2-51de-4957-b3d1-c3f1d0c7e1c8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204004776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3204004776
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1433260543
Short name T621
Test name
Test status
Simulation time 60445985 ps
CPU time 2.64 seconds
Started Mar 07 02:50:26 PM PST 24
Finished Mar 07 02:50:29 PM PST 24
Peak memory 207512 kb
Host smart-ba664832-8056-476d-bc96-1e44369b6e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433260543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1433260543
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.768112632
Short name T829
Test name
Test status
Simulation time 476803663 ps
CPU time 11.06 seconds
Started Mar 07 02:50:22 PM PST 24
Finished Mar 07 02:50:33 PM PST 24
Peak memory 207804 kb
Host smart-4562855a-b5d3-4fbd-a7fb-ef91107f7724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768112632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.768112632
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.4004353396
Short name T807
Test name
Test status
Simulation time 203525779 ps
CPU time 3.95 seconds
Started Mar 07 02:50:26 PM PST 24
Finished Mar 07 02:50:31 PM PST 24
Peak memory 210072 kb
Host smart-24678fb0-9101-4f0a-a399-cabd91157553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004353396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.4004353396
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.721061288
Short name T397
Test name
Test status
Simulation time 96607975 ps
CPU time 1.82 seconds
Started Mar 07 02:50:29 PM PST 24
Finished Mar 07 02:50:31 PM PST 24
Peak memory 209980 kb
Host smart-b505ec95-fe52-4930-94ce-4f522f14b098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721061288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.721061288
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2026946538
Short name T473
Test name
Test status
Simulation time 67205640 ps
CPU time 0.76 seconds
Started Mar 07 02:50:42 PM PST 24
Finished Mar 07 02:50:43 PM PST 24
Peak memory 206184 kb
Host smart-4a27b1bd-46d0-44b0-a19e-a1d942b8656b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026946538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2026946538
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.45000408
Short name T384
Test name
Test status
Simulation time 113345072 ps
CPU time 4.33 seconds
Started Mar 07 02:50:35 PM PST 24
Finished Mar 07 02:50:39 PM PST 24
Peak memory 215352 kb
Host smart-5e1367ed-b2ad-41ee-815b-949384a9ad21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45000408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.45000408
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1082461476
Short name T858
Test name
Test status
Simulation time 130143073 ps
CPU time 1.92 seconds
Started Mar 07 02:50:34 PM PST 24
Finished Mar 07 02:50:37 PM PST 24
Peak memory 222860 kb
Host smart-6f75f313-9a33-4324-ba54-67f161215f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082461476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1082461476
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3881926207
Short name T378
Test name
Test status
Simulation time 439920214 ps
CPU time 4.86 seconds
Started Mar 07 02:50:37 PM PST 24
Finished Mar 07 02:50:42 PM PST 24
Peak memory 218644 kb
Host smart-bf19b87f-7b39-4e95-92c3-2adfd90b4c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881926207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3881926207
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_random.1128958006
Short name T34
Test name
Test status
Simulation time 252409788 ps
CPU time 6.93 seconds
Started Mar 07 02:50:37 PM PST 24
Finished Mar 07 02:50:44 PM PST 24
Peak memory 208824 kb
Host smart-4c68621b-e1eb-44cd-a312-f86a9416e355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128958006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1128958006
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1814323208
Short name T245
Test name
Test status
Simulation time 68014980 ps
CPU time 2.33 seconds
Started Mar 07 02:50:27 PM PST 24
Finished Mar 07 02:50:29 PM PST 24
Peak memory 208440 kb
Host smart-94684919-df7c-4b68-9879-bd8bd8700dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814323208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1814323208
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1690720328
Short name T868
Test name
Test status
Simulation time 53672740 ps
CPU time 2.92 seconds
Started Mar 07 02:50:37 PM PST 24
Finished Mar 07 02:50:40 PM PST 24
Peak memory 206852 kb
Host smart-abcc1dd7-3b67-4fa6-818e-b65f8b3a2ab5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690720328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1690720328
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2766639779
Short name T644
Test name
Test status
Simulation time 626181299 ps
CPU time 6.49 seconds
Started Mar 07 02:50:38 PM PST 24
Finished Mar 07 02:50:45 PM PST 24
Peak memory 207744 kb
Host smart-2aac2b80-07c2-49f8-bc94-f01cb8dcbb34
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766639779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2766639779
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.747770939
Short name T655
Test name
Test status
Simulation time 1469319546 ps
CPU time 3.96 seconds
Started Mar 07 02:50:37 PM PST 24
Finished Mar 07 02:50:41 PM PST 24
Peak memory 206716 kb
Host smart-ec5f2440-b526-4f27-9ee6-273421904785
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747770939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.747770939
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.778622329
Short name T684
Test name
Test status
Simulation time 57036408 ps
CPU time 1.72 seconds
Started Mar 07 02:50:38 PM PST 24
Finished Mar 07 02:50:40 PM PST 24
Peak memory 207084 kb
Host smart-663dcdde-affb-4e1d-a837-a0cad5a920f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778622329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.778622329
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2895278430
Short name T845
Test name
Test status
Simulation time 411935714 ps
CPU time 3.07 seconds
Started Mar 07 02:50:30 PM PST 24
Finished Mar 07 02:50:34 PM PST 24
Peak memory 208356 kb
Host smart-afbc0955-2ff2-4d5f-941e-941f7edb0a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895278430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2895278430
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.670023343
Short name T244
Test name
Test status
Simulation time 2725830219 ps
CPU time 21.73 seconds
Started Mar 07 02:50:40 PM PST 24
Finished Mar 07 02:51:02 PM PST 24
Peak memory 215292 kb
Host smart-767eacd6-4fb7-49bf-bba8-477654c21af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670023343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.670023343
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.502235876
Short name T138
Test name
Test status
Simulation time 927742182 ps
CPU time 8.43 seconds
Started Mar 07 02:50:44 PM PST 24
Finished Mar 07 02:50:52 PM PST 24
Peak memory 222728 kb
Host smart-b69ee637-ef9a-4b8f-bb11-613ef376bb05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502235876 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.502235876
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3337905759
Short name T490
Test name
Test status
Simulation time 226087862 ps
CPU time 6.26 seconds
Started Mar 07 02:50:41 PM PST 24
Finished Mar 07 02:50:48 PM PST 24
Peak memory 208384 kb
Host smart-d4b4b1bf-9d98-4a7c-9dbd-fb3d8145cc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337905759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3337905759
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3262778508
Short name T185
Test name
Test status
Simulation time 348935014 ps
CPU time 3.96 seconds
Started Mar 07 02:50:37 PM PST 24
Finished Mar 07 02:50:41 PM PST 24
Peak memory 210240 kb
Host smart-fd871e4b-7911-4275-98fe-a71746907d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262778508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3262778508
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3950365511
Short name T811
Test name
Test status
Simulation time 14054427 ps
CPU time 0.77 seconds
Started Mar 07 02:50:51 PM PST 24
Finished Mar 07 02:50:52 PM PST 24
Peak memory 206188 kb
Host smart-55da990b-58dc-45d6-91c4-4a9f998df1c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950365511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3950365511
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.533622021
Short name T838
Test name
Test status
Simulation time 57071816 ps
CPU time 4.11 seconds
Started Mar 07 02:50:45 PM PST 24
Finished Mar 07 02:50:49 PM PST 24
Peak memory 214332 kb
Host smart-7c6bab8d-ab0f-4411-83db-6d66da891671
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=533622021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.533622021
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1297536172
Short name T891
Test name
Test status
Simulation time 2034052019 ps
CPU time 7.85 seconds
Started Mar 07 02:50:55 PM PST 24
Finished Mar 07 02:51:03 PM PST 24
Peak memory 209400 kb
Host smart-12bbbff6-6edb-4ff8-a03a-6dbec665e120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297536172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1297536172
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1879031736
Short name T652
Test name
Test status
Simulation time 1170737512 ps
CPU time 25.65 seconds
Started Mar 07 02:50:42 PM PST 24
Finished Mar 07 02:51:08 PM PST 24
Peak memory 208472 kb
Host smart-1ce47127-89fc-40f5-9f72-4c480d890254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879031736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1879031736
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.831480901
Short name T98
Test name
Test status
Simulation time 158192422 ps
CPU time 4.06 seconds
Started Mar 07 02:50:43 PM PST 24
Finished Mar 07 02:50:47 PM PST 24
Peak memory 209640 kb
Host smart-e2c7652f-100f-426f-98b2-a82bf2bae73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831480901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.831480901
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1886113161
Short name T398
Test name
Test status
Simulation time 544651627 ps
CPU time 6.23 seconds
Started Mar 07 02:50:50 PM PST 24
Finished Mar 07 02:50:56 PM PST 24
Peak memory 210672 kb
Host smart-da4a4a26-5da7-4a65-ab3e-9f3699d7485a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886113161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1886113161
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.95550077
Short name T444
Test name
Test status
Simulation time 63438808 ps
CPU time 2.87 seconds
Started Mar 07 02:50:43 PM PST 24
Finished Mar 07 02:50:46 PM PST 24
Peak memory 220556 kb
Host smart-72cdc20d-c058-462f-b5ec-de70e8c0cd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95550077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.95550077
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.270384644
Short name T375
Test name
Test status
Simulation time 96083797 ps
CPU time 4.53 seconds
Started Mar 07 02:50:42 PM PST 24
Finished Mar 07 02:50:48 PM PST 24
Peak memory 208676 kb
Host smart-779ba346-8332-426b-90b4-3d9b822afffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270384644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.270384644
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1447900461
Short name T217
Test name
Test status
Simulation time 371153901 ps
CPU time 3.64 seconds
Started Mar 07 02:50:40 PM PST 24
Finished Mar 07 02:50:44 PM PST 24
Peak memory 208552 kb
Host smart-af942e2d-926d-4014-b1d3-ab89f81228a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447900461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1447900461
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2522819895
Short name T715
Test name
Test status
Simulation time 676660880 ps
CPU time 24.23 seconds
Started Mar 07 02:50:43 PM PST 24
Finished Mar 07 02:51:07 PM PST 24
Peak memory 208716 kb
Host smart-5a208165-c100-452a-a840-ac7dddae2a22
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522819895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2522819895
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1916985452
Short name T844
Test name
Test status
Simulation time 344515028 ps
CPU time 2.62 seconds
Started Mar 07 02:50:40 PM PST 24
Finished Mar 07 02:50:43 PM PST 24
Peak memory 207212 kb
Host smart-6ed43126-bdd9-4539-8568-b4ef9e6ecf54
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916985452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1916985452
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1575988425
Short name T889
Test name
Test status
Simulation time 90567242 ps
CPU time 1.78 seconds
Started Mar 07 02:50:41 PM PST 24
Finished Mar 07 02:50:44 PM PST 24
Peak memory 206832 kb
Host smart-dd17fff1-b7b7-43ea-9bc0-5cf00c83f9fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575988425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1575988425
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.4289729400
Short name T254
Test name
Test status
Simulation time 57072463 ps
CPU time 3.02 seconds
Started Mar 07 02:50:49 PM PST 24
Finished Mar 07 02:50:53 PM PST 24
Peak memory 210492 kb
Host smart-d3e0506b-efc7-4086-94ed-8efdcfc9fdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289729400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.4289729400
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.959744987
Short name T795
Test name
Test status
Simulation time 869047598 ps
CPU time 20.86 seconds
Started Mar 07 02:50:41 PM PST 24
Finished Mar 07 02:51:02 PM PST 24
Peak memory 208044 kb
Host smart-ce39ec8a-311e-4846-a015-1ab0267d18a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959744987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.959744987
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1568107460
Short name T235
Test name
Test status
Simulation time 794011106 ps
CPU time 11.78 seconds
Started Mar 07 02:50:54 PM PST 24
Finished Mar 07 02:51:06 PM PST 24
Peak memory 216028 kb
Host smart-2cdc9604-1004-4f4e-ab70-195913b46b25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568107460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1568107460
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2467762409
Short name T293
Test name
Test status
Simulation time 3693529012 ps
CPU time 64.82 seconds
Started Mar 07 02:50:42 PM PST 24
Finished Mar 07 02:51:47 PM PST 24
Peak memory 214572 kb
Host smart-be21ba93-f912-4520-b3da-ab9beb61d214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467762409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2467762409
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1435870315
Short name T540
Test name
Test status
Simulation time 1558338590 ps
CPU time 9.65 seconds
Started Mar 07 02:50:48 PM PST 24
Finished Mar 07 02:50:59 PM PST 24
Peak memory 210840 kb
Host smart-526b37d2-df2e-4290-b55a-b117d3cdbdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435870315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1435870315
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.135561388
Short name T624
Test name
Test status
Simulation time 11225758 ps
CPU time 0.74 seconds
Started Mar 07 02:51:00 PM PST 24
Finished Mar 07 02:51:01 PM PST 24
Peak memory 206196 kb
Host smart-19fd2f85-638d-46ba-b398-4ef8e2034054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135561388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.135561388
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.4022560523
Short name T714
Test name
Test status
Simulation time 764097309 ps
CPU time 9.53 seconds
Started Mar 07 02:50:58 PM PST 24
Finished Mar 07 02:51:07 PM PST 24
Peak memory 209992 kb
Host smart-99c5b4c8-7e3b-4077-af17-11fb73065e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022560523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.4022560523
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1833027677
Short name T55
Test name
Test status
Simulation time 3903420854 ps
CPU time 38.25 seconds
Started Mar 07 02:50:48 PM PST 24
Finished Mar 07 02:51:27 PM PST 24
Peak memory 214480 kb
Host smart-2236abea-fa30-4fce-9ccc-b41dc8381621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833027677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1833027677
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.280827173
Short name T356
Test name
Test status
Simulation time 2854441970 ps
CPU time 28.6 seconds
Started Mar 07 02:50:53 PM PST 24
Finished Mar 07 02:51:22 PM PST 24
Peak memory 219696 kb
Host smart-a7a88083-fcba-416b-b074-067a21840d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280827173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.280827173
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.229492486
Short name T286
Test name
Test status
Simulation time 382652495 ps
CPU time 7.89 seconds
Started Mar 07 02:50:55 PM PST 24
Finished Mar 07 02:51:03 PM PST 24
Peak memory 214412 kb
Host smart-68947e37-692b-4e3c-aa8a-ea2043f3e61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229492486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.229492486
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1658207814
Short name T718
Test name
Test status
Simulation time 58984158 ps
CPU time 2.17 seconds
Started Mar 07 02:50:55 PM PST 24
Finished Mar 07 02:50:58 PM PST 24
Peak memory 207892 kb
Host smart-4102e1fe-00e4-475b-8867-4e352050fa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658207814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1658207814
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2387856469
Short name T888
Test name
Test status
Simulation time 77979565 ps
CPU time 4.05 seconds
Started Mar 07 02:50:54 PM PST 24
Finished Mar 07 02:50:58 PM PST 24
Peak memory 209816 kb
Host smart-0384064f-889a-4d4f-bfef-3db66a3eb48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387856469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2387856469
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2198103663
Short name T614
Test name
Test status
Simulation time 191180217 ps
CPU time 7.67 seconds
Started Mar 07 02:50:52 PM PST 24
Finished Mar 07 02:51:00 PM PST 24
Peak memory 208588 kb
Host smart-b369b851-e4f4-4675-8d54-66b1a5072c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198103663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2198103663
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2214867611
Short name T484
Test name
Test status
Simulation time 531318547 ps
CPU time 3.7 seconds
Started Mar 07 02:50:47 PM PST 24
Finished Mar 07 02:50:51 PM PST 24
Peak memory 206828 kb
Host smart-94d445f7-e5b3-4289-a2e9-351bdf89928f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214867611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2214867611
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2903556456
Short name T557
Test name
Test status
Simulation time 1666120125 ps
CPU time 7.89 seconds
Started Mar 07 02:50:47 PM PST 24
Finished Mar 07 02:50:56 PM PST 24
Peak memory 208952 kb
Host smart-b276ac57-151f-4d56-8d55-a0a476c6daa4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903556456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2903556456
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1620502278
Short name T690
Test name
Test status
Simulation time 132970681 ps
CPU time 2.51 seconds
Started Mar 07 02:50:49 PM PST 24
Finished Mar 07 02:50:53 PM PST 24
Peak memory 206616 kb
Host smart-dff38a9c-94ad-4f0a-be09-2815c706605b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620502278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1620502278
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.783248349
Short name T317
Test name
Test status
Simulation time 119171625 ps
CPU time 3.25 seconds
Started Mar 07 02:50:58 PM PST 24
Finished Mar 07 02:51:02 PM PST 24
Peak memory 209916 kb
Host smart-84058d98-8ff4-4b72-9506-fc27c76a6e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783248349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.783248349
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.4000065926
Short name T720
Test name
Test status
Simulation time 953514399 ps
CPU time 9.14 seconds
Started Mar 07 02:50:48 PM PST 24
Finished Mar 07 02:50:58 PM PST 24
Peak memory 208440 kb
Host smart-f559d52e-9ccf-4c47-910b-cdf09bc8a95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000065926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.4000065926
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.828120418
Short name T65
Test name
Test status
Simulation time 319832522 ps
CPU time 11.51 seconds
Started Mar 07 02:50:57 PM PST 24
Finished Mar 07 02:51:09 PM PST 24
Peak memory 217228 kb
Host smart-3fcf0c8c-977b-4445-b813-e37a67c024df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828120418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.828120418
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2485584758
Short name T358
Test name
Test status
Simulation time 325911677 ps
CPU time 4.12 seconds
Started Mar 07 02:50:56 PM PST 24
Finished Mar 07 02:51:01 PM PST 24
Peak memory 208712 kb
Host smart-611410e7-4b8c-4514-b921-223872c4b676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485584758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2485584758
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2918921206
Short name T186
Test name
Test status
Simulation time 67884177 ps
CPU time 1.09 seconds
Started Mar 07 02:50:59 PM PST 24
Finished Mar 07 02:51:00 PM PST 24
Peak memory 209636 kb
Host smart-fbb707f9-029b-422a-8a70-b665c44f627d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918921206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2918921206
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3139689034
Short name T509
Test name
Test status
Simulation time 44173830 ps
CPU time 0.75 seconds
Started Mar 07 02:48:08 PM PST 24
Finished Mar 07 02:48:09 PM PST 24
Peak memory 206108 kb
Host smart-da89554e-83d2-48fe-8714-6df1c67d897f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139689034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3139689034
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1634900383
Short name T335
Test name
Test status
Simulation time 4059478933 ps
CPU time 109.56 seconds
Started Mar 07 02:48:03 PM PST 24
Finished Mar 07 02:49:53 PM PST 24
Peak memory 215716 kb
Host smart-992dbaf2-78a9-41b5-ba96-69244fb3b186
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1634900383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1634900383
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1109749668
Short name T332
Test name
Test status
Simulation time 117351613 ps
CPU time 3.48 seconds
Started Mar 07 02:48:03 PM PST 24
Finished Mar 07 02:48:08 PM PST 24
Peak memory 207568 kb
Host smart-7c3efb2f-effd-497e-bf19-cae4f8ba7c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109749668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1109749668
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3687387998
Short name T209
Test name
Test status
Simulation time 196807210 ps
CPU time 7.39 seconds
Started Mar 07 02:48:10 PM PST 24
Finished Mar 07 02:48:17 PM PST 24
Peak memory 210188 kb
Host smart-0c1337c0-0899-4984-bf1b-23edba0c8086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687387998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3687387998
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3279368989
Short name T231
Test name
Test status
Simulation time 364808507 ps
CPU time 2.6 seconds
Started Mar 07 02:48:06 PM PST 24
Finished Mar 07 02:48:09 PM PST 24
Peak memory 220568 kb
Host smart-98705d47-007c-44ff-8353-0cbe249d1971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279368989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3279368989
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2972118075
Short name T620
Test name
Test status
Simulation time 328586805 ps
CPU time 10.16 seconds
Started Mar 07 02:48:06 PM PST 24
Finished Mar 07 02:48:17 PM PST 24
Peak memory 214420 kb
Host smart-9fcb45d2-9675-4472-b232-e03bb5f0d2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972118075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2972118075
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.140519115
Short name T214
Test name
Test status
Simulation time 818165301 ps
CPU time 25.47 seconds
Started Mar 07 02:48:00 PM PST 24
Finished Mar 07 02:48:25 PM PST 24
Peak memory 208816 kb
Host smart-14d28ea6-e1ec-4069-a1fc-bee18fe6a7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140519115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.140519115
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1520468123
Short name T712
Test name
Test status
Simulation time 1308454722 ps
CPU time 35.57 seconds
Started Mar 07 02:48:04 PM PST 24
Finished Mar 07 02:48:40 PM PST 24
Peak memory 208304 kb
Host smart-27836931-d758-4b60-bebf-95a059ddc5aa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520468123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1520468123
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.213546474
Short name T447
Test name
Test status
Simulation time 861715318 ps
CPU time 7.14 seconds
Started Mar 07 02:48:02 PM PST 24
Finished Mar 07 02:48:10 PM PST 24
Peak memory 208844 kb
Host smart-755415bd-74ca-4c91-b495-53e12a97e60e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213546474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.213546474
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2965022777
Short name T852
Test name
Test status
Simulation time 111936864 ps
CPU time 2.91 seconds
Started Mar 07 02:48:07 PM PST 24
Finished Mar 07 02:48:10 PM PST 24
Peak memory 206720 kb
Host smart-0bac134a-2880-400a-8412-02c2c8e0311e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965022777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2965022777
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.874191891
Short name T682
Test name
Test status
Simulation time 115950347 ps
CPU time 2.62 seconds
Started Mar 07 02:48:04 PM PST 24
Finished Mar 07 02:48:07 PM PST 24
Peak memory 208356 kb
Host smart-7fe97bad-8f2b-4d44-97d9-ffde567715e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874191891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.874191891
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.4252339061
Short name T456
Test name
Test status
Simulation time 958125395 ps
CPU time 2.92 seconds
Started Mar 07 02:48:03 PM PST 24
Finished Mar 07 02:48:06 PM PST 24
Peak memory 206788 kb
Host smart-bbee5452-a51e-4e2b-ba8c-0e69d8eacd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252339061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.4252339061
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2566625027
Short name T328
Test name
Test status
Simulation time 1005862290 ps
CPU time 36.61 seconds
Started Mar 07 02:48:07 PM PST 24
Finished Mar 07 02:48:43 PM PST 24
Peak memory 219884 kb
Host smart-325693c4-e82c-4648-a1be-3f3164de2f55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566625027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2566625027
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2837064086
Short name T207
Test name
Test status
Simulation time 169707629 ps
CPU time 4.3 seconds
Started Mar 07 02:48:06 PM PST 24
Finished Mar 07 02:48:10 PM PST 24
Peak memory 207300 kb
Host smart-5702ef51-d410-4090-96d3-97b1aa012df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837064086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2837064086
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.286406419
Short name T594
Test name
Test status
Simulation time 231470372 ps
CPU time 2.28 seconds
Started Mar 07 02:48:04 PM PST 24
Finished Mar 07 02:48:07 PM PST 24
Peak memory 209852 kb
Host smart-dae33542-ece2-40ca-9557-5cf8e4bf2075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286406419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.286406419
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1721517324
Short name T786
Test name
Test status
Simulation time 89001539 ps
CPU time 0.89 seconds
Started Mar 07 02:51:07 PM PST 24
Finished Mar 07 02:51:09 PM PST 24
Peak memory 206236 kb
Host smart-89f86b0d-9508-43dd-9ef1-529ea56f0ba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721517324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1721517324
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.934285800
Short name T31
Test name
Test status
Simulation time 707786588 ps
CPU time 5.14 seconds
Started Mar 07 02:51:05 PM PST 24
Finished Mar 07 02:51:11 PM PST 24
Peak memory 221700 kb
Host smart-cd1e7203-4baf-4da2-8cac-317682502408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934285800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.934285800
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3454875349
Short name T823
Test name
Test status
Simulation time 48463760 ps
CPU time 2.92 seconds
Started Mar 07 02:50:57 PM PST 24
Finished Mar 07 02:51:01 PM PST 24
Peak memory 214436 kb
Host smart-d420d269-4b8a-4c0b-b629-cb77e04375fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454875349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3454875349
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3096481998
Short name T843
Test name
Test status
Simulation time 1420081344 ps
CPU time 9.16 seconds
Started Mar 07 02:51:01 PM PST 24
Finished Mar 07 02:51:11 PM PST 24
Peak memory 219484 kb
Host smart-37b061cf-770c-4efc-9ae9-404afeeb939f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096481998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3096481998
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.190679074
Short name T80
Test name
Test status
Simulation time 147074111 ps
CPU time 4.67 seconds
Started Mar 07 02:51:07 PM PST 24
Finished Mar 07 02:51:13 PM PST 24
Peak memory 222612 kb
Host smart-94ee3d94-85bb-4898-887f-f373bf35b304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190679074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.190679074
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2012444302
Short name T669
Test name
Test status
Simulation time 387340379 ps
CPU time 5.41 seconds
Started Mar 07 02:51:01 PM PST 24
Finished Mar 07 02:51:06 PM PST 24
Peak memory 218748 kb
Host smart-4f391d0e-cc5e-4e42-ba44-1614999baebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012444302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2012444302
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1112627237
Short name T418
Test name
Test status
Simulation time 180792989 ps
CPU time 5.98 seconds
Started Mar 07 02:50:56 PM PST 24
Finished Mar 07 02:51:02 PM PST 24
Peak memory 210036 kb
Host smart-ea14d999-cdbc-4a94-aa02-012a6878320e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112627237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1112627237
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.464014847
Short name T583
Test name
Test status
Simulation time 1728306453 ps
CPU time 6.1 seconds
Started Mar 07 02:50:57 PM PST 24
Finished Mar 07 02:51:03 PM PST 24
Peak memory 206884 kb
Host smart-f177813e-908e-4ae2-94ee-f444af915506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464014847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.464014847
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.507569178
Short name T393
Test name
Test status
Simulation time 219723041 ps
CPU time 4.67 seconds
Started Mar 07 02:50:58 PM PST 24
Finished Mar 07 02:51:03 PM PST 24
Peak memory 206848 kb
Host smart-ad15f5e8-4492-4ee8-b266-c0dbe72a3cd6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507569178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.507569178
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3751804363
Short name T576
Test name
Test status
Simulation time 896898743 ps
CPU time 2.78 seconds
Started Mar 07 02:51:01 PM PST 24
Finished Mar 07 02:51:05 PM PST 24
Peak memory 208444 kb
Host smart-6d3ccb6d-cff4-404d-8cc0-0aff6563a792
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751804363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3751804363
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1355756191
Short name T524
Test name
Test status
Simulation time 67783334 ps
CPU time 2.2 seconds
Started Mar 07 02:51:05 PM PST 24
Finished Mar 07 02:51:08 PM PST 24
Peak memory 208588 kb
Host smart-d8cca272-3f1e-43ea-9499-a315f8c6cea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355756191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1355756191
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3540890987
Short name T430
Test name
Test status
Simulation time 151527637 ps
CPU time 3.68 seconds
Started Mar 07 02:51:04 PM PST 24
Finished Mar 07 02:51:08 PM PST 24
Peak memory 208640 kb
Host smart-9487527b-0643-4582-b212-28cf4e47fd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540890987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3540890987
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.209245643
Short name T115
Test name
Test status
Simulation time 363417430 ps
CPU time 13.02 seconds
Started Mar 07 02:51:07 PM PST 24
Finished Mar 07 02:51:21 PM PST 24
Peak memory 222736 kb
Host smart-33b3f25f-cebf-4762-b301-eb1181fe9df0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209245643 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.209245643
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1245279376
Short name T410
Test name
Test status
Simulation time 285824234 ps
CPU time 4.67 seconds
Started Mar 07 02:51:03 PM PST 24
Finished Mar 07 02:51:09 PM PST 24
Peak memory 208380 kb
Host smart-8bb6d2f0-c03a-4820-8088-1a9980efbe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245279376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1245279376
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.23396409
Short name T863
Test name
Test status
Simulation time 53041590 ps
CPU time 1.95 seconds
Started Mar 07 02:51:07 PM PST 24
Finished Mar 07 02:51:10 PM PST 24
Peak memory 209896 kb
Host smart-df93c19d-8d20-4dc7-857f-ce3ad38382e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23396409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.23396409
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2523535905
Short name T86
Test name
Test status
Simulation time 16568731 ps
CPU time 0.81 seconds
Started Mar 07 02:51:16 PM PST 24
Finished Mar 07 02:51:17 PM PST 24
Peak memory 206188 kb
Host smart-a92be9a5-845b-482c-8e7d-3ed2f3656076
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523535905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2523535905
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1075616497
Short name T402
Test name
Test status
Simulation time 195899266 ps
CPU time 3.78 seconds
Started Mar 07 02:51:05 PM PST 24
Finished Mar 07 02:51:09 PM PST 24
Peak memory 215368 kb
Host smart-2eae3c82-d053-45da-a678-6c0b870bef58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1075616497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1075616497
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1353247652
Short name T662
Test name
Test status
Simulation time 302375307 ps
CPU time 2.55 seconds
Started Mar 07 02:51:18 PM PST 24
Finished Mar 07 02:51:21 PM PST 24
Peak memory 210012 kb
Host smart-0f6c4d72-5956-4244-af7e-7b1ac99ad3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353247652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1353247652
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1054489757
Short name T363
Test name
Test status
Simulation time 174708750 ps
CPU time 4.08 seconds
Started Mar 07 02:51:05 PM PST 24
Finished Mar 07 02:51:09 PM PST 24
Peak memory 207104 kb
Host smart-1c5335c9-64b1-4c5b-9fe4-73674360b6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054489757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1054489757
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1502727769
Short name T304
Test name
Test status
Simulation time 64162180 ps
CPU time 3.96 seconds
Started Mar 07 02:51:16 PM PST 24
Finished Mar 07 02:51:20 PM PST 24
Peak memory 214524 kb
Host smart-b44222e2-7b55-466c-8414-895a23097109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502727769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1502727769
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1432766412
Short name T492
Test name
Test status
Simulation time 111510191 ps
CPU time 2.48 seconds
Started Mar 07 02:51:18 PM PST 24
Finished Mar 07 02:51:20 PM PST 24
Peak memory 211800 kb
Host smart-bec1d582-367b-49b8-8749-334aae921c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432766412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1432766412
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_random.2348704279
Short name T563
Test name
Test status
Simulation time 476385894 ps
CPU time 7.33 seconds
Started Mar 07 02:51:04 PM PST 24
Finished Mar 07 02:51:12 PM PST 24
Peak memory 209344 kb
Host smart-f4e54ba7-f956-4df8-9ed7-e2419d528072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348704279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2348704279
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3213760346
Short name T396
Test name
Test status
Simulation time 35230734 ps
CPU time 2.49 seconds
Started Mar 07 02:51:07 PM PST 24
Finished Mar 07 02:51:09 PM PST 24
Peak memory 206664 kb
Host smart-98731604-3df9-497f-804c-6ccd946d466c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213760346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3213760346
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3211734246
Short name T555
Test name
Test status
Simulation time 1936470017 ps
CPU time 13.49 seconds
Started Mar 07 02:51:09 PM PST 24
Finished Mar 07 02:51:23 PM PST 24
Peak memory 208180 kb
Host smart-4e439fb9-9b00-4096-bf23-6828cfcd8971
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211734246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3211734246
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3078332218
Short name T766
Test name
Test status
Simulation time 716467628 ps
CPU time 4.95 seconds
Started Mar 07 02:51:15 PM PST 24
Finished Mar 07 02:51:20 PM PST 24
Peak memory 206904 kb
Host smart-82cf471f-eaad-4a68-adf2-a77697ac52ae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078332218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3078332218
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.447277627
Short name T432
Test name
Test status
Simulation time 482058656 ps
CPU time 4.07 seconds
Started Mar 07 02:51:06 PM PST 24
Finished Mar 07 02:51:10 PM PST 24
Peak memory 206872 kb
Host smart-a99bdb49-b2a5-4389-b25d-863a275ff199
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447277627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.447277627
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1187875774
Short name T860
Test name
Test status
Simulation time 264108758 ps
CPU time 4.43 seconds
Started Mar 07 02:51:19 PM PST 24
Finished Mar 07 02:51:24 PM PST 24
Peak memory 209984 kb
Host smart-d2617d98-091a-4b9a-8ccd-715a7dfd5eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187875774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1187875774
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3334031330
Short name T530
Test name
Test status
Simulation time 65253208 ps
CPU time 2.38 seconds
Started Mar 07 02:51:06 PM PST 24
Finished Mar 07 02:51:09 PM PST 24
Peak memory 208544 kb
Host smart-f958c8d4-921a-4e63-846a-c92ed5fc936e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334031330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3334031330
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3014353269
Short name T277
Test name
Test status
Simulation time 5266366835 ps
CPU time 41.12 seconds
Started Mar 07 02:51:18 PM PST 24
Finished Mar 07 02:52:00 PM PST 24
Peak memory 222668 kb
Host smart-1f57c66f-1aaa-4312-b881-53c40824b64c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014353269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3014353269
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.26092090
Short name T566
Test name
Test status
Simulation time 1070531276 ps
CPU time 28.6 seconds
Started Mar 07 02:51:19 PM PST 24
Finished Mar 07 02:51:48 PM PST 24
Peak memory 218588 kb
Host smart-b8059e93-d2e3-44ee-b0cf-f8c87f07b62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26092090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.26092090
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.900593246
Short name T475
Test name
Test status
Simulation time 1173798125 ps
CPU time 3.12 seconds
Started Mar 07 02:51:16 PM PST 24
Finished Mar 07 02:51:19 PM PST 24
Peak memory 209876 kb
Host smart-042dc07d-f9f4-46f7-b45a-6d686e6c7094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900593246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.900593246
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3699379583
Short name T598
Test name
Test status
Simulation time 13975475 ps
CPU time 0.74 seconds
Started Mar 07 02:51:29 PM PST 24
Finished Mar 07 02:51:29 PM PST 24
Peak memory 206112 kb
Host smart-173108ba-9164-42a8-af1e-8452b099c6b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699379583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3699379583
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1613702291
Short name T403
Test name
Test status
Simulation time 509446426 ps
CPU time 8.07 seconds
Started Mar 07 02:51:20 PM PST 24
Finished Mar 07 02:51:28 PM PST 24
Peak memory 215552 kb
Host smart-f9f203a4-35dd-4c01-9b40-426f2c649453
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1613702291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1613702291
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3792521251
Short name T32
Test name
Test status
Simulation time 53690507 ps
CPU time 1.5 seconds
Started Mar 07 02:51:29 PM PST 24
Finished Mar 07 02:51:30 PM PST 24
Peak memory 215312 kb
Host smart-4d38c538-a84d-43f5-b494-08bed546d327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792521251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3792521251
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.4270454584
Short name T673
Test name
Test status
Simulation time 231572437 ps
CPU time 2.14 seconds
Started Mar 07 02:51:20 PM PST 24
Finished Mar 07 02:51:22 PM PST 24
Peak memory 207592 kb
Host smart-bd0e45f5-6db4-4f0b-b67f-64949e42b3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270454584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.4270454584
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2082473369
Short name T308
Test name
Test status
Simulation time 279021179 ps
CPU time 6.6 seconds
Started Mar 07 02:51:28 PM PST 24
Finished Mar 07 02:51:34 PM PST 24
Peak memory 214292 kb
Host smart-657269fb-5f51-4161-894d-2191c947a379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082473369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2082473369
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.509948242
Short name T553
Test name
Test status
Simulation time 243379242 ps
CPU time 4.49 seconds
Started Mar 07 02:51:17 PM PST 24
Finished Mar 07 02:51:22 PM PST 24
Peak memory 220088 kb
Host smart-dd64daae-ebc1-42e1-84e8-75ffb2f7ef0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509948242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.509948242
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2890901220
Short name T881
Test name
Test status
Simulation time 575344907 ps
CPU time 4.41 seconds
Started Mar 07 02:51:19 PM PST 24
Finished Mar 07 02:51:23 PM PST 24
Peak memory 209640 kb
Host smart-ac17f2ca-d441-4ba6-8b8e-c673b83127ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890901220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2890901220
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.264986087
Short name T585
Test name
Test status
Simulation time 526823263 ps
CPU time 13.23 seconds
Started Mar 07 02:51:19 PM PST 24
Finished Mar 07 02:51:33 PM PST 24
Peak memory 208080 kb
Host smart-c622ae5f-44b1-4cfc-8460-e3252f3ed7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264986087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.264986087
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2844025074
Short name T486
Test name
Test status
Simulation time 264095655 ps
CPU time 3.48 seconds
Started Mar 07 02:51:20 PM PST 24
Finished Mar 07 02:51:23 PM PST 24
Peak memory 208944 kb
Host smart-9e5c7748-6238-4538-a4d1-c98175c2b62f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844025074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2844025074
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3749276648
Short name T326
Test name
Test status
Simulation time 49901342 ps
CPU time 2.07 seconds
Started Mar 07 02:51:17 PM PST 24
Finished Mar 07 02:51:20 PM PST 24
Peak memory 209088 kb
Host smart-df077d7c-be18-4e02-9bc7-440ffced045b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749276648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3749276648
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.827765961
Short name T551
Test name
Test status
Simulation time 82544898 ps
CPU time 2.13 seconds
Started Mar 07 02:51:21 PM PST 24
Finished Mar 07 02:51:23 PM PST 24
Peak memory 207452 kb
Host smart-4c6ba0f5-f22a-44da-9deb-1e9990a611bf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827765961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.827765961
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1029757302
Short name T295
Test name
Test status
Simulation time 983968485 ps
CPU time 4.74 seconds
Started Mar 07 02:51:27 PM PST 24
Finished Mar 07 02:51:32 PM PST 24
Peak memory 207648 kb
Host smart-207f436f-c806-409f-ae67-be54b1cddfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029757302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1029757302
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.4267546769
Short name T196
Test name
Test status
Simulation time 54411676 ps
CPU time 2.84 seconds
Started Mar 07 02:51:17 PM PST 24
Finished Mar 07 02:51:20 PM PST 24
Peak memory 208252 kb
Host smart-5f0b56e4-8b32-4b80-aa8b-58c9e16319d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267546769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.4267546769
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3146444197
Short name T198
Test name
Test status
Simulation time 2281656802 ps
CPU time 15.98 seconds
Started Mar 07 02:51:28 PM PST 24
Finished Mar 07 02:51:44 PM PST 24
Peak memory 219144 kb
Host smart-c103b483-21df-4b53-a94a-c687d1896758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146444197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3146444197
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.576296586
Short name T794
Test name
Test status
Simulation time 261866772 ps
CPU time 2.8 seconds
Started Mar 07 02:51:31 PM PST 24
Finished Mar 07 02:51:34 PM PST 24
Peak memory 210100 kb
Host smart-567ed6e2-f874-4986-8748-5aa932a080b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576296586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.576296586
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.475340128
Short name T497
Test name
Test status
Simulation time 62473794 ps
CPU time 0.92 seconds
Started Mar 07 02:51:37 PM PST 24
Finished Mar 07 02:51:38 PM PST 24
Peak memory 206320 kb
Host smart-049e2e82-6b68-4b6c-9964-65c558505456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475340128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.475340128
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.672813806
Short name T886
Test name
Test status
Simulation time 66402034 ps
CPU time 4.28 seconds
Started Mar 07 02:51:28 PM PST 24
Finished Mar 07 02:51:32 PM PST 24
Peak memory 215612 kb
Host smart-831e7092-5086-42ec-b851-8e1ccc5d5767
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=672813806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.672813806
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1622972668
Short name T780
Test name
Test status
Simulation time 825382199 ps
CPU time 8.01 seconds
Started Mar 07 02:51:36 PM PST 24
Finished Mar 07 02:51:44 PM PST 24
Peak memory 208080 kb
Host smart-b0c0e7cf-bf95-4726-ae46-7fe1dc003adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622972668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1622972668
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2113620883
Short name T259
Test name
Test status
Simulation time 155710592 ps
CPU time 3.59 seconds
Started Mar 07 02:51:28 PM PST 24
Finished Mar 07 02:51:32 PM PST 24
Peak memory 214480 kb
Host smart-4b6f3718-ff5b-4739-b7ea-0469dc3f66c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113620883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2113620883
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3503745258
Short name T818
Test name
Test status
Simulation time 83072778 ps
CPU time 4.29 seconds
Started Mar 07 02:51:36 PM PST 24
Finished Mar 07 02:51:40 PM PST 24
Peak memory 218784 kb
Host smart-be1ecec0-6032-4abb-a0b4-29e364c4b2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503745258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3503745258
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3666679608
Short name T777
Test name
Test status
Simulation time 47011421 ps
CPU time 2.82 seconds
Started Mar 07 02:51:28 PM PST 24
Finished Mar 07 02:51:30 PM PST 24
Peak memory 209632 kb
Host smart-6d88f31f-a935-4968-b04f-b52b8ce6e248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666679608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3666679608
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1970545401
Short name T836
Test name
Test status
Simulation time 989217142 ps
CPU time 4.1 seconds
Started Mar 07 02:51:29 PM PST 24
Finished Mar 07 02:51:34 PM PST 24
Peak memory 208688 kb
Host smart-6baef12d-001f-47ad-ae3c-5166c35a7df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970545401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1970545401
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2303587546
Short name T513
Test name
Test status
Simulation time 136365269 ps
CPU time 2.69 seconds
Started Mar 07 02:51:27 PM PST 24
Finished Mar 07 02:51:30 PM PST 24
Peak memory 206840 kb
Host smart-a7a4fb10-6eda-4c95-92d2-d578c2ede4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303587546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2303587546
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3801912519
Short name T578
Test name
Test status
Simulation time 48441136 ps
CPU time 2.72 seconds
Started Mar 07 02:51:25 PM PST 24
Finished Mar 07 02:51:28 PM PST 24
Peak memory 206852 kb
Host smart-90ad8bab-1b21-473d-998b-b3d9641eee56
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801912519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3801912519
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3847562583
Short name T619
Test name
Test status
Simulation time 1135081402 ps
CPU time 10.93 seconds
Started Mar 07 02:51:26 PM PST 24
Finished Mar 07 02:51:37 PM PST 24
Peak memory 208444 kb
Host smart-054f0181-7b96-4976-ba3b-d237d6e489a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847562583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3847562583
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2494693688
Short name T282
Test name
Test status
Simulation time 702073205 ps
CPU time 18.92 seconds
Started Mar 07 02:51:32 PM PST 24
Finished Mar 07 02:51:51 PM PST 24
Peak memory 207864 kb
Host smart-62fe1b18-49be-4340-9656-af359bc70beb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494693688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2494693688
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1814205880
Short name T854
Test name
Test status
Simulation time 980746820 ps
CPU time 11.07 seconds
Started Mar 07 02:51:35 PM PST 24
Finished Mar 07 02:51:46 PM PST 24
Peak memory 214460 kb
Host smart-4b604bce-3d76-48d6-b056-f9812c7d85bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814205880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1814205880
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.165674766
Short name T596
Test name
Test status
Simulation time 57892910 ps
CPU time 3 seconds
Started Mar 07 02:51:27 PM PST 24
Finished Mar 07 02:51:30 PM PST 24
Peak memory 208476 kb
Host smart-1463b74c-f57f-4bc2-83e3-843c55cf8d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165674766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.165674766
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2809351611
Short name T234
Test name
Test status
Simulation time 1711219852 ps
CPU time 48.24 seconds
Started Mar 07 02:51:34 PM PST 24
Finished Mar 07 02:52:22 PM PST 24
Peak memory 215828 kb
Host smart-9ebe1bf9-d397-46a1-9629-9fbbebc588cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809351611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2809351611
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.4184802408
Short name T116
Test name
Test status
Simulation time 268792207 ps
CPU time 7 seconds
Started Mar 07 02:51:36 PM PST 24
Finished Mar 07 02:51:43 PM PST 24
Peak memory 222752 kb
Host smart-617c691b-e810-4149-b1d2-ad4a0f1ae08c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184802408 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.4184802408
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2065312499
Short name T747
Test name
Test status
Simulation time 711303277 ps
CPU time 7.7 seconds
Started Mar 07 02:51:35 PM PST 24
Finished Mar 07 02:51:42 PM PST 24
Peak memory 214444 kb
Host smart-9877043e-1933-490b-b9af-e6ef007fe76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065312499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2065312499
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2671023526
Short name T63
Test name
Test status
Simulation time 331370491 ps
CPU time 3.66 seconds
Started Mar 07 02:51:34 PM PST 24
Finished Mar 07 02:51:37 PM PST 24
Peak memory 210332 kb
Host smart-346c05fa-6f7e-4b0f-973e-a2be0791b3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671023526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2671023526
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.141661865
Short name T528
Test name
Test status
Simulation time 13705432 ps
CPU time 0.9 seconds
Started Mar 07 02:51:56 PM PST 24
Finished Mar 07 02:51:57 PM PST 24
Peak memory 206288 kb
Host smart-d04788c5-b155-4812-91e0-4ccb1774b12f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141661865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.141661865
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1559058332
Short name T421
Test name
Test status
Simulation time 67891538 ps
CPU time 2.86 seconds
Started Mar 07 02:51:46 PM PST 24
Finished Mar 07 02:51:49 PM PST 24
Peak memory 214444 kb
Host smart-2349f54a-ebde-445f-bc43-a97fac740f9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559058332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1559058332
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1598853923
Short name T30
Test name
Test status
Simulation time 43109296 ps
CPU time 1.97 seconds
Started Mar 07 02:51:49 PM PST 24
Finished Mar 07 02:51:51 PM PST 24
Peak memory 219976 kb
Host smart-cd63bec3-e063-45b9-9cf9-1b14c607e28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598853923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1598853923
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1238861324
Short name T825
Test name
Test status
Simulation time 382004068 ps
CPU time 7.93 seconds
Started Mar 07 02:51:47 PM PST 24
Finished Mar 07 02:51:55 PM PST 24
Peak memory 218572 kb
Host smart-dc1ee7a4-4f35-4b4e-b66b-ed80621daa0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238861324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1238861324
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2448063887
Short name T377
Test name
Test status
Simulation time 9488483170 ps
CPU time 110.59 seconds
Started Mar 07 02:51:47 PM PST 24
Finished Mar 07 02:53:38 PM PST 24
Peak memory 214628 kb
Host smart-1a45eea9-001a-4536-949c-b3b357777881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448063887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2448063887
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.702778384
Short name T505
Test name
Test status
Simulation time 1209443321 ps
CPU time 5.6 seconds
Started Mar 07 02:51:47 PM PST 24
Finished Mar 07 02:51:53 PM PST 24
Peak memory 208032 kb
Host smart-042951e5-f616-4eff-b398-ee75ea326359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702778384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.702778384
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3578127265
Short name T463
Test name
Test status
Simulation time 420519910 ps
CPU time 8.58 seconds
Started Mar 07 02:51:47 PM PST 24
Finished Mar 07 02:51:56 PM PST 24
Peak memory 208100 kb
Host smart-a3ec2b5a-e3a0-4c84-8019-3f85d0460814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578127265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3578127265
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3316121695
Short name T296
Test name
Test status
Simulation time 410730192 ps
CPU time 3.06 seconds
Started Mar 07 02:51:36 PM PST 24
Finished Mar 07 02:51:39 PM PST 24
Peak memory 207544 kb
Host smart-c99a6cbd-efe1-4048-9c70-e514c8a0fe4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316121695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3316121695
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1809332290
Short name T512
Test name
Test status
Simulation time 528653985 ps
CPU time 7.78 seconds
Started Mar 07 02:51:37 PM PST 24
Finished Mar 07 02:51:45 PM PST 24
Peak memory 208468 kb
Host smart-d092881a-5a4c-41fc-92b3-90d5d1a7a9d5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809332290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1809332290
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2114699804
Short name T591
Test name
Test status
Simulation time 61005673 ps
CPU time 2.3 seconds
Started Mar 07 02:51:37 PM PST 24
Finished Mar 07 02:51:39 PM PST 24
Peak memory 206916 kb
Host smart-51b816a5-792f-4b04-b70b-c5bcdcd3ab6b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114699804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2114699804
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.824559766
Short name T640
Test name
Test status
Simulation time 319463835 ps
CPU time 5.61 seconds
Started Mar 07 02:51:54 PM PST 24
Finished Mar 07 02:52:00 PM PST 24
Peak memory 207988 kb
Host smart-0bb7e82f-7ba9-40f9-839d-a141e0f6ef72
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824559766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.824559766
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1179694991
Short name T788
Test name
Test status
Simulation time 42648169 ps
CPU time 2.14 seconds
Started Mar 07 02:51:49 PM PST 24
Finished Mar 07 02:51:51 PM PST 24
Peak memory 209876 kb
Host smart-f582033a-3226-496a-a57f-28832b81eca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179694991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1179694991
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.4133686782
Short name T431
Test name
Test status
Simulation time 320666536 ps
CPU time 3.15 seconds
Started Mar 07 02:51:39 PM PST 24
Finished Mar 07 02:51:42 PM PST 24
Peak memory 206680 kb
Host smart-41795ff5-bd0e-4d39-abf7-569cba16f77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133686782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.4133686782
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1767759025
Short name T75
Test name
Test status
Simulation time 904487969 ps
CPU time 33.77 seconds
Started Mar 07 02:51:46 PM PST 24
Finished Mar 07 02:52:20 PM PST 24
Peak memory 216744 kb
Host smart-2a6e4a3c-12c9-42b9-973e-8a88407bb5e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767759025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1767759025
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.2125260230
Short name T169
Test name
Test status
Simulation time 207085375 ps
CPU time 7.36 seconds
Started Mar 07 02:51:57 PM PST 24
Finished Mar 07 02:52:05 PM PST 24
Peak memory 222720 kb
Host smart-85a460da-3ea9-4752-b35e-e807b7980b00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125260230 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.2125260230
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1857244515
Short name T400
Test name
Test status
Simulation time 136849013 ps
CPU time 5.94 seconds
Started Mar 07 02:51:46 PM PST 24
Finished Mar 07 02:51:52 PM PST 24
Peak memory 210012 kb
Host smart-68efb532-829b-4f91-8efa-d64ad1956aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857244515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1857244515
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2137309253
Short name T537
Test name
Test status
Simulation time 120246096 ps
CPU time 2.81 seconds
Started Mar 07 02:51:48 PM PST 24
Finished Mar 07 02:51:50 PM PST 24
Peak memory 210536 kb
Host smart-6df66a0e-154f-4e9c-81da-8d074c35ff72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137309253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2137309253
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3416991210
Short name T648
Test name
Test status
Simulation time 32239838 ps
CPU time 0.74 seconds
Started Mar 07 02:52:09 PM PST 24
Finished Mar 07 02:52:09 PM PST 24
Peak memory 206112 kb
Host smart-6e4c49d8-de77-4f5a-b063-d48fdd20d9c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416991210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3416991210
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.142281340
Short name T867
Test name
Test status
Simulation time 162545550 ps
CPU time 9.08 seconds
Started Mar 07 02:51:59 PM PST 24
Finished Mar 07 02:52:09 PM PST 24
Peak memory 215308 kb
Host smart-ee718e6f-fdd1-40a4-95e5-cdd0803f4ea0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=142281340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.142281340
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1023776856
Short name T48
Test name
Test status
Simulation time 60398955 ps
CPU time 3.03 seconds
Started Mar 07 02:51:57 PM PST 24
Finished Mar 07 02:52:00 PM PST 24
Peak memory 207864 kb
Host smart-42efe2f3-3d60-4193-85e0-16ce7e488e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023776856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1023776856
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3319268525
Short name T23
Test name
Test status
Simulation time 5270242457 ps
CPU time 12.33 seconds
Started Mar 07 02:51:58 PM PST 24
Finished Mar 07 02:52:11 PM PST 24
Peak memory 220584 kb
Host smart-10d7b21f-bc57-492a-b1fe-a6a809ec1370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319268525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3319268525
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.796784092
Short name T241
Test name
Test status
Simulation time 1583222361 ps
CPU time 36.34 seconds
Started Mar 07 02:52:00 PM PST 24
Finished Mar 07 02:52:37 PM PST 24
Peak memory 222496 kb
Host smart-c97e9d1b-0140-4d5a-a706-203b7466267d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796784092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.796784092
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.988706502
Short name T50
Test name
Test status
Simulation time 1179175236 ps
CPU time 4.76 seconds
Started Mar 07 02:52:01 PM PST 24
Finished Mar 07 02:52:06 PM PST 24
Peak memory 219868 kb
Host smart-98e3dedb-eb59-45c9-8e5a-daf4f287c6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988706502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.988706502
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1826592109
Short name T210
Test name
Test status
Simulation time 1772720089 ps
CPU time 25.84 seconds
Started Mar 07 02:51:56 PM PST 24
Finished Mar 07 02:52:22 PM PST 24
Peak memory 208648 kb
Host smart-9e7d32b6-7d21-4b18-aab5-e007358f6cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826592109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1826592109
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2161723248
Short name T246
Test name
Test status
Simulation time 1434341342 ps
CPU time 34.35 seconds
Started Mar 07 02:51:57 PM PST 24
Finished Mar 07 02:52:32 PM PST 24
Peak memory 208540 kb
Host smart-3fb33f28-f00a-4724-bd5c-f524a0f2ded2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161723248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2161723248
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2453111425
Short name T508
Test name
Test status
Simulation time 191609966 ps
CPU time 5.23 seconds
Started Mar 07 02:51:56 PM PST 24
Finished Mar 07 02:52:02 PM PST 24
Peak memory 207868 kb
Host smart-0b4f863b-b587-41fc-aff7-7ba39c2fffaf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453111425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2453111425
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.545168035
Short name T824
Test name
Test status
Simulation time 592862205 ps
CPU time 3.75 seconds
Started Mar 07 02:52:00 PM PST 24
Finished Mar 07 02:52:04 PM PST 24
Peak memory 208508 kb
Host smart-89963726-d8ad-4827-95f2-0044f67e4e5b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545168035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.545168035
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.4221529321
Short name T193
Test name
Test status
Simulation time 1874136554 ps
CPU time 49.98 seconds
Started Mar 07 02:51:56 PM PST 24
Finished Mar 07 02:52:46 PM PST 24
Peak memory 208952 kb
Host smart-7f5415fa-fe00-49d8-a129-2277949a2ed6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221529321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.4221529321
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1008149685
Short name T632
Test name
Test status
Simulation time 190334176 ps
CPU time 1.85 seconds
Started Mar 07 02:51:59 PM PST 24
Finished Mar 07 02:52:01 PM PST 24
Peak memory 215428 kb
Host smart-3024ce3a-6169-4def-acb0-8d30ce81a43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008149685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1008149685
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2363226959
Short name T633
Test name
Test status
Simulation time 192084998 ps
CPU time 3.02 seconds
Started Mar 07 02:51:57 PM PST 24
Finished Mar 07 02:52:00 PM PST 24
Peak memory 208516 kb
Host smart-4b5b2984-e70f-42aa-8224-5c86eec63641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363226959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2363226959
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.372331667
Short name T279
Test name
Test status
Simulation time 233256658 ps
CPU time 3.21 seconds
Started Mar 07 02:51:55 PM PST 24
Finished Mar 07 02:51:59 PM PST 24
Peak memory 207336 kb
Host smart-83de8a6e-6851-4ce3-b6cf-f45f893298cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372331667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.372331667
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2026058558
Short name T548
Test name
Test status
Simulation time 429790197 ps
CPU time 2.73 seconds
Started Mar 07 02:52:01 PM PST 24
Finished Mar 07 02:52:04 PM PST 24
Peak memory 209928 kb
Host smart-1a5dbc81-1491-4910-b69f-342269eb4c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026058558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2026058558
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.459070915
Short name T113
Test name
Test status
Simulation time 20661491 ps
CPU time 0.81 seconds
Started Mar 07 02:52:18 PM PST 24
Finished Mar 07 02:52:19 PM PST 24
Peak memory 206024 kb
Host smart-bc37b4b4-f8c5-4f8b-8361-b033b1b1fa2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459070915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.459070915
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.696651012
Short name T195
Test name
Test status
Simulation time 68125887 ps
CPU time 2.56 seconds
Started Mar 07 02:52:10 PM PST 24
Finished Mar 07 02:52:14 PM PST 24
Peak memory 215384 kb
Host smart-95ec4310-1405-49a5-9d0f-929249860bb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=696651012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.696651012
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.154032744
Short name T861
Test name
Test status
Simulation time 109606975 ps
CPU time 3.25 seconds
Started Mar 07 02:52:11 PM PST 24
Finished Mar 07 02:52:14 PM PST 24
Peak memory 217448 kb
Host smart-6dde27e3-5145-48c4-9495-cd540e940575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154032744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.154032744
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2185408236
Short name T731
Test name
Test status
Simulation time 1396629562 ps
CPU time 17.61 seconds
Started Mar 07 02:52:13 PM PST 24
Finished Mar 07 02:52:31 PM PST 24
Peak memory 216252 kb
Host smart-136d60ce-281f-49f4-9029-aa6c2ce1aef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185408236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2185408236
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3206595036
Short name T101
Test name
Test status
Simulation time 175710843 ps
CPU time 3.07 seconds
Started Mar 07 02:52:12 PM PST 24
Finished Mar 07 02:52:16 PM PST 24
Peak memory 208404 kb
Host smart-bdd856f3-3fe6-4db0-b07c-b95e4e32d205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206595036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3206595036
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3471030440
Short name T270
Test name
Test status
Simulation time 170128113 ps
CPU time 7.6 seconds
Started Mar 07 02:52:09 PM PST 24
Finished Mar 07 02:52:17 PM PST 24
Peak memory 211512 kb
Host smart-d82e4db9-00ae-4278-9460-06d2e530e17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471030440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3471030440
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2038047031
Short name T545
Test name
Test status
Simulation time 1470027760 ps
CPU time 5.4 seconds
Started Mar 07 02:52:09 PM PST 24
Finished Mar 07 02:52:15 PM PST 24
Peak memory 210352 kb
Host smart-47877fb3-0dd0-4260-b2b1-4fb9d4dc11c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038047031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2038047031
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.324241680
Short name T266
Test name
Test status
Simulation time 259202315 ps
CPU time 4.07 seconds
Started Mar 07 02:52:07 PM PST 24
Finished Mar 07 02:52:12 PM PST 24
Peak memory 206832 kb
Host smart-1d7453cc-43f7-4cb2-9193-a666439c693d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324241680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.324241680
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1181268307
Short name T354
Test name
Test status
Simulation time 34016185 ps
CPU time 2.41 seconds
Started Mar 07 02:52:10 PM PST 24
Finished Mar 07 02:52:13 PM PST 24
Peak memory 207648 kb
Host smart-6916f46c-0e0a-4064-bceb-c6da8941fa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181268307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1181268307
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3838514675
Short name T391
Test name
Test status
Simulation time 79357325 ps
CPU time 3.59 seconds
Started Mar 07 02:52:11 PM PST 24
Finished Mar 07 02:52:15 PM PST 24
Peak memory 208792 kb
Host smart-e2780606-b8b6-47cb-bab0-792ef5c29ce6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838514675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3838514675
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3110594583
Short name T466
Test name
Test status
Simulation time 5522223659 ps
CPU time 16.92 seconds
Started Mar 07 02:52:09 PM PST 24
Finished Mar 07 02:52:26 PM PST 24
Peak memory 208776 kb
Host smart-9a041670-87f8-4f7a-b983-b7b1374daefb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110594583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3110594583
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3538181308
Short name T752
Test name
Test status
Simulation time 220395127 ps
CPU time 3.05 seconds
Started Mar 07 02:52:08 PM PST 24
Finished Mar 07 02:52:11 PM PST 24
Peak memory 208104 kb
Host smart-026f8ebd-f02d-4256-8d64-b6212203c722
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538181308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3538181308
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1271411935
Short name T411
Test name
Test status
Simulation time 911642449 ps
CPU time 5.75 seconds
Started Mar 07 02:52:09 PM PST 24
Finished Mar 07 02:52:15 PM PST 24
Peak memory 208992 kb
Host smart-3b6596ad-59de-4608-8fe8-9aa3f7494ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271411935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1271411935
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1737456765
Short name T445
Test name
Test status
Simulation time 487501655 ps
CPU time 4.6 seconds
Started Mar 07 02:52:10 PM PST 24
Finished Mar 07 02:52:15 PM PST 24
Peak memory 208524 kb
Host smart-e60d93b7-57f8-4b2f-bb32-8e49d80dda2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737456765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1737456765
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.3090044943
Short name T170
Test name
Test status
Simulation time 1537371149 ps
CPU time 8.31 seconds
Started Mar 07 02:52:14 PM PST 24
Finished Mar 07 02:52:23 PM PST 24
Peak memory 220424 kb
Host smart-4ec5c8c2-777e-4594-8ece-f9970916409f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090044943 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.3090044943
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.4165664120
Short name T740
Test name
Test status
Simulation time 458576388 ps
CPU time 7.22 seconds
Started Mar 07 02:52:10 PM PST 24
Finished Mar 07 02:52:17 PM PST 24
Peak memory 209444 kb
Host smart-273209cf-cb53-4a8b-b555-55eb0e85c3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165664120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.4165664120
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2091096707
Short name T57
Test name
Test status
Simulation time 144583591 ps
CPU time 3.16 seconds
Started Mar 07 02:52:10 PM PST 24
Finished Mar 07 02:52:14 PM PST 24
Peak memory 210560 kb
Host smart-a8c4d459-3d54-4b5e-b83e-bdc32f093d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091096707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2091096707
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.719179045
Short name T577
Test name
Test status
Simulation time 13074043 ps
CPU time 0.69 seconds
Started Mar 07 02:52:26 PM PST 24
Finished Mar 07 02:52:27 PM PST 24
Peak memory 206172 kb
Host smart-57550d00-dc7c-4212-9aea-bd78d9007ac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719179045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.719179045
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3795593562
Short name T191
Test name
Test status
Simulation time 210311059 ps
CPU time 10.93 seconds
Started Mar 07 02:52:15 PM PST 24
Finished Mar 07 02:52:26 PM PST 24
Peak memory 214672 kb
Host smart-1b66bb3f-1fd0-49c1-8cb5-4950c8564441
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795593562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3795593562
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1461022941
Short name T39
Test name
Test status
Simulation time 186084858 ps
CPU time 2.66 seconds
Started Mar 07 02:52:25 PM PST 24
Finished Mar 07 02:52:28 PM PST 24
Peak memory 218780 kb
Host smart-b8092fd6-d217-477b-9020-89673d3485c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461022941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1461022941
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3021990698
Short name T873
Test name
Test status
Simulation time 101431451 ps
CPU time 2.32 seconds
Started Mar 07 02:52:15 PM PST 24
Finished Mar 07 02:52:17 PM PST 24
Peak memory 207988 kb
Host smart-17ad70c2-9a6f-4d67-b866-91be72a8cdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021990698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3021990698
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1226094360
Short name T725
Test name
Test status
Simulation time 90925471 ps
CPU time 3.79 seconds
Started Mar 07 02:52:16 PM PST 24
Finished Mar 07 02:52:20 PM PST 24
Peak memory 222580 kb
Host smart-3a671f35-19f9-4f5d-b709-6a6a5c218207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226094360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1226094360
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2182744179
Short name T213
Test name
Test status
Simulation time 327238647 ps
CPU time 4.45 seconds
Started Mar 07 02:52:27 PM PST 24
Finished Mar 07 02:52:32 PM PST 24
Peak memory 211656 kb
Host smart-52ae8c3c-4ffb-4569-96e4-817c6af91390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182744179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2182744179
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1881321640
Short name T364
Test name
Test status
Simulation time 678041098 ps
CPU time 5.19 seconds
Started Mar 07 02:52:17 PM PST 24
Finished Mar 07 02:52:22 PM PST 24
Peak memory 215432 kb
Host smart-251abf4d-5b84-4d95-a6db-b88c94638511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881321640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1881321640
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.581438147
Short name T878
Test name
Test status
Simulation time 1200374672 ps
CPU time 7.84 seconds
Started Mar 07 02:52:22 PM PST 24
Finished Mar 07 02:52:30 PM PST 24
Peak memory 207928 kb
Host smart-dfd7d7c1-930e-4b81-81cd-b3c8beb42fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581438147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.581438147
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.211359320
Short name T339
Test name
Test status
Simulation time 664692103 ps
CPU time 5.27 seconds
Started Mar 07 02:52:19 PM PST 24
Finished Mar 07 02:52:24 PM PST 24
Peak memory 208412 kb
Host smart-432ac81f-4aba-4b14-aa92-1ec5d9d51825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211359320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.211359320
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.857185309
Short name T608
Test name
Test status
Simulation time 253902402 ps
CPU time 6.1 seconds
Started Mar 07 02:52:14 PM PST 24
Finished Mar 07 02:52:20 PM PST 24
Peak memory 207732 kb
Host smart-41480946-77da-47a3-a2a8-0eacef7c84da
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857185309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.857185309
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2889483389
Short name T352
Test name
Test status
Simulation time 113397113 ps
CPU time 2.42 seconds
Started Mar 07 02:52:16 PM PST 24
Finished Mar 07 02:52:19 PM PST 24
Peak memory 207496 kb
Host smart-18254bf1-9a81-4f74-a5e0-3cafcbe28f13
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889483389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2889483389
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.29199770
Short name T549
Test name
Test status
Simulation time 2911427213 ps
CPU time 41.42 seconds
Started Mar 07 02:52:15 PM PST 24
Finished Mar 07 02:52:57 PM PST 24
Peak memory 208472 kb
Host smart-b903b353-ab11-40d8-9c2d-12af2caa9650
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29199770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.29199770
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2821595546
Short name T504
Test name
Test status
Simulation time 66048347 ps
CPU time 2.83 seconds
Started Mar 07 02:52:24 PM PST 24
Finished Mar 07 02:52:27 PM PST 24
Peak memory 206808 kb
Host smart-6ff5964f-9476-49ed-96f5-1640bcfe6def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821595546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2821595546
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3212833184
Short name T804
Test name
Test status
Simulation time 267808819 ps
CPU time 6.14 seconds
Started Mar 07 02:52:20 PM PST 24
Finished Mar 07 02:52:26 PM PST 24
Peak memory 208536 kb
Host smart-2017d9db-083e-4f6c-9b17-daa274d4e75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212833184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3212833184
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2402752458
Short name T302
Test name
Test status
Simulation time 105780009 ps
CPU time 5.09 seconds
Started Mar 07 02:52:24 PM PST 24
Finished Mar 07 02:52:30 PM PST 24
Peak memory 220480 kb
Host smart-4d7b799e-e569-4deb-992d-6c8a286a788e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402752458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2402752458
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.264831989
Short name T862
Test name
Test status
Simulation time 1691077570 ps
CPU time 7.77 seconds
Started Mar 07 02:52:27 PM PST 24
Finished Mar 07 02:52:36 PM PST 24
Peak memory 219956 kb
Host smart-57447ef3-2fa2-4896-9da8-78191a011c14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264831989 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.264831989
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.247307671
Short name T274
Test name
Test status
Simulation time 376956139 ps
CPU time 6.61 seconds
Started Mar 07 02:52:17 PM PST 24
Finished Mar 07 02:52:23 PM PST 24
Peak memory 215140 kb
Host smart-389ef0e6-84ef-4f50-88a4-5a117cbdf839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247307671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.247307671
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1497847950
Short name T120
Test name
Test status
Simulation time 88681383 ps
CPU time 3.3 seconds
Started Mar 07 02:52:25 PM PST 24
Finished Mar 07 02:52:28 PM PST 24
Peak memory 209816 kb
Host smart-84e44b12-0b1a-404b-9aea-1cd2806d8402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497847950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1497847950
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3559482661
Short name T460
Test name
Test status
Simulation time 8145996 ps
CPU time 0.73 seconds
Started Mar 07 02:52:44 PM PST 24
Finished Mar 07 02:52:45 PM PST 24
Peak memory 206176 kb
Host smart-6f7a9f4d-a4a9-45d6-822d-70389c7d66e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559482661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3559482661
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3960216748
Short name T263
Test name
Test status
Simulation time 746948702 ps
CPU time 3.21 seconds
Started Mar 07 02:52:36 PM PST 24
Finished Mar 07 02:52:39 PM PST 24
Peak memory 215316 kb
Host smart-b13e62a0-a044-43e3-98d6-6e67458f422d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3960216748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3960216748
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2816726993
Short name T623
Test name
Test status
Simulation time 504484582 ps
CPU time 7.15 seconds
Started Mar 07 02:52:44 PM PST 24
Finished Mar 07 02:52:51 PM PST 24
Peak memory 221508 kb
Host smart-1a3c3962-6f8d-4544-9401-710c6b626005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816726993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2816726993
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3421026313
Short name T514
Test name
Test status
Simulation time 119167193 ps
CPU time 1.96 seconds
Started Mar 07 02:52:35 PM PST 24
Finished Mar 07 02:52:38 PM PST 24
Peak memory 207640 kb
Host smart-0dd5178c-c7a3-44ae-a7de-2e14ef828fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421026313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3421026313
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3130628144
Short name T95
Test name
Test status
Simulation time 140137543 ps
CPU time 4.08 seconds
Started Mar 07 02:52:36 PM PST 24
Finished Mar 07 02:52:41 PM PST 24
Peak memory 209000 kb
Host smart-023183f4-09b4-4e40-a24c-d4becc5f8367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130628144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3130628144
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3113202267
Short name T476
Test name
Test status
Simulation time 40793699 ps
CPU time 2.95 seconds
Started Mar 07 02:52:38 PM PST 24
Finished Mar 07 02:52:41 PM PST 24
Peak memory 215816 kb
Host smart-22252776-1a34-4787-835a-cd1c3678803d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113202267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3113202267
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3604942361
Short name T855
Test name
Test status
Simulation time 816967912 ps
CPU time 28.81 seconds
Started Mar 07 02:52:38 PM PST 24
Finished Mar 07 02:53:07 PM PST 24
Peak memory 209696 kb
Host smart-5b43cbf4-5a3c-40be-9c32-3bc402a3228d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604942361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3604942361
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2265576540
Short name T787
Test name
Test status
Simulation time 85820989 ps
CPU time 3.15 seconds
Started Mar 07 02:52:37 PM PST 24
Finished Mar 07 02:52:41 PM PST 24
Peak memory 206732 kb
Host smart-bd784fea-9f00-419f-936e-e9c1a8aed446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265576540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2265576540
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.4103415413
Short name T870
Test name
Test status
Simulation time 189942819 ps
CPU time 2.41 seconds
Started Mar 07 02:52:37 PM PST 24
Finished Mar 07 02:52:40 PM PST 24
Peak memory 206712 kb
Host smart-c1fad561-c5e7-4f8e-9a0a-e95619663b09
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103415413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.4103415413
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3028904277
Short name T515
Test name
Test status
Simulation time 1076936366 ps
CPU time 7.36 seconds
Started Mar 07 02:52:34 PM PST 24
Finished Mar 07 02:52:41 PM PST 24
Peak memory 208516 kb
Host smart-fd31dc9f-46c3-4ce2-9931-e8638b5e3365
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028904277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3028904277
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3050791475
Short name T479
Test name
Test status
Simulation time 78575776 ps
CPU time 2.41 seconds
Started Mar 07 02:52:39 PM PST 24
Finished Mar 07 02:52:41 PM PST 24
Peak memory 206892 kb
Host smart-951fa54e-b566-4ee1-b0cc-c251c1c47391
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050791475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3050791475
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2690452094
Short name T14
Test name
Test status
Simulation time 6729195887 ps
CPU time 19.45 seconds
Started Mar 07 02:52:42 PM PST 24
Finished Mar 07 02:53:02 PM PST 24
Peak memory 210012 kb
Host smart-f411d5a3-58dc-454a-b335-f1c725885fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690452094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2690452094
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1358305913
Short name T616
Test name
Test status
Simulation time 815190839 ps
CPU time 5.81 seconds
Started Mar 07 02:52:35 PM PST 24
Finished Mar 07 02:52:41 PM PST 24
Peak memory 208656 kb
Host smart-76b0de5b-4503-406a-8f93-78847ba1fa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358305913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1358305913
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.613134319
Short name T216
Test name
Test status
Simulation time 28133528 ps
CPU time 2.06 seconds
Started Mar 07 02:52:45 PM PST 24
Finished Mar 07 02:52:48 PM PST 24
Peak memory 206972 kb
Host smart-3cee1cc4-152e-47b0-8105-175e08788cf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613134319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.613134319
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.183012600
Short name T131
Test name
Test status
Simulation time 1031270180 ps
CPU time 18.53 seconds
Started Mar 07 02:52:44 PM PST 24
Finished Mar 07 02:53:03 PM PST 24
Peak memory 220616 kb
Host smart-1e7dbacc-75fe-4df5-b1f0-c96544794487
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183012600 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.183012600
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.500358705
Short name T316
Test name
Test status
Simulation time 577084320 ps
CPU time 7.92 seconds
Started Mar 07 02:52:34 PM PST 24
Finished Mar 07 02:52:43 PM PST 24
Peak memory 218284 kb
Host smart-6ff97e65-f583-4cf0-b143-c907a26a7900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500358705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.500358705
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2672448359
Short name T35
Test name
Test status
Simulation time 1006564069 ps
CPU time 6.14 seconds
Started Mar 07 02:52:44 PM PST 24
Finished Mar 07 02:52:50 PM PST 24
Peak memory 210836 kb
Host smart-4dd7ef55-5644-40cd-aac5-9a0a506dbef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672448359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2672448359
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.219014149
Short name T586
Test name
Test status
Simulation time 11351553 ps
CPU time 0.77 seconds
Started Mar 07 02:53:01 PM PST 24
Finished Mar 07 02:53:01 PM PST 24
Peak memory 206060 kb
Host smart-7c5f198e-f9d1-407b-8bdf-d1ce33c4e4dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219014149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.219014149
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1181944685
Short name T41
Test name
Test status
Simulation time 184841531 ps
CPU time 5.94 seconds
Started Mar 07 02:52:57 PM PST 24
Finished Mar 07 02:53:04 PM PST 24
Peak memory 209632 kb
Host smart-a5cca3f8-b72f-45a0-bf59-f423bb19edca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181944685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1181944685
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2831928997
Short name T74
Test name
Test status
Simulation time 81083944 ps
CPU time 3.07 seconds
Started Mar 07 02:52:52 PM PST 24
Finished Mar 07 02:52:55 PM PST 24
Peak memory 209692 kb
Host smart-3e594c9a-0861-4e41-abb5-0d4bbb8a66b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831928997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2831928997
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1689479406
Short name T790
Test name
Test status
Simulation time 52534238 ps
CPU time 2.98 seconds
Started Mar 07 02:52:49 PM PST 24
Finished Mar 07 02:52:52 PM PST 24
Peak memory 209316 kb
Host smart-ab0ac13c-8c02-4d4b-8c21-436a6dc3894b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689479406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1689479406
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2917885065
Short name T625
Test name
Test status
Simulation time 97356040 ps
CPU time 3.8 seconds
Started Mar 07 02:52:52 PM PST 24
Finished Mar 07 02:52:55 PM PST 24
Peak memory 218620 kb
Host smart-0d057f97-677f-4338-9cdb-984a24ca7a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917885065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2917885065
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3723303056
Short name T538
Test name
Test status
Simulation time 2065851524 ps
CPU time 20.82 seconds
Started Mar 07 02:52:50 PM PST 24
Finished Mar 07 02:53:11 PM PST 24
Peak memory 218300 kb
Host smart-a03807af-e6be-4fbb-bbd4-8351e7883223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723303056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3723303056
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2651968058
Short name T543
Test name
Test status
Simulation time 32432582 ps
CPU time 2.4 seconds
Started Mar 07 02:52:51 PM PST 24
Finished Mar 07 02:52:54 PM PST 24
Peak memory 206900 kb
Host smart-d379d6ae-cd2c-4263-a4f9-5339077af6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651968058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2651968058
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.374996284
Short name T670
Test name
Test status
Simulation time 1398494008 ps
CPU time 10.09 seconds
Started Mar 07 02:52:50 PM PST 24
Finished Mar 07 02:53:01 PM PST 24
Peak memory 208440 kb
Host smart-8e6c3fe1-b2dc-4ff4-85b5-505106823578
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374996284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.374996284
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.4171107704
Short name T359
Test name
Test status
Simulation time 163318073 ps
CPU time 3.74 seconds
Started Mar 07 02:52:50 PM PST 24
Finished Mar 07 02:52:54 PM PST 24
Peak memory 207144 kb
Host smart-853f3b08-6ea8-47c3-8a92-ab5f535f012c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171107704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.4171107704
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.366267500
Short name T653
Test name
Test status
Simulation time 79712526 ps
CPU time 3.28 seconds
Started Mar 07 02:52:52 PM PST 24
Finished Mar 07 02:52:56 PM PST 24
Peak memory 206864 kb
Host smart-80a11826-6b50-41b7-99a2-3983a9844bba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366267500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.366267500
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2115156688
Short name T519
Test name
Test status
Simulation time 22997366 ps
CPU time 1.77 seconds
Started Mar 07 02:53:01 PM PST 24
Finished Mar 07 02:53:03 PM PST 24
Peak memory 207368 kb
Host smart-f60be948-5b26-4377-a88d-9e2af5597a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115156688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2115156688
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.4093398129
Short name T767
Test name
Test status
Simulation time 210892098 ps
CPU time 4.52 seconds
Started Mar 07 02:52:45 PM PST 24
Finished Mar 07 02:52:50 PM PST 24
Peak memory 206900 kb
Host smart-51c593e6-a0d9-4c9a-ab6b-697cec5d9518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093398129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.4093398129
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.417775446
Short name T622
Test name
Test status
Simulation time 3695625166 ps
CPU time 24.36 seconds
Started Mar 07 02:52:57 PM PST 24
Finished Mar 07 02:53:21 PM PST 24
Peak memory 215032 kb
Host smart-76967ca5-fad5-4159-b890-fbc7dfdb3446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417775446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.417775446
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1021856287
Short name T604
Test name
Test status
Simulation time 398487910 ps
CPU time 4.93 seconds
Started Mar 07 02:52:50 PM PST 24
Finished Mar 07 02:52:56 PM PST 24
Peak memory 218348 kb
Host smart-bf3405c7-f9a7-4df4-a4cd-0866fa3ee36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021856287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1021856287
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.595629030
Short name T477
Test name
Test status
Simulation time 111219937 ps
CPU time 3.37 seconds
Started Mar 07 02:52:57 PM PST 24
Finished Mar 07 02:53:01 PM PST 24
Peak memory 210204 kb
Host smart-d935f6b8-6971-4988-9a9c-8cf2bc1d79f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595629030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.595629030
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.4053403505
Short name T874
Test name
Test status
Simulation time 20263855 ps
CPU time 0.82 seconds
Started Mar 07 02:48:03 PM PST 24
Finished Mar 07 02:48:04 PM PST 24
Peak memory 206140 kb
Host smart-58d65476-bf63-4472-aad4-a1e45f023602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053403505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.4053403505
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.4019487505
Short name T141
Test name
Test status
Simulation time 276223163 ps
CPU time 3.54 seconds
Started Mar 07 02:48:06 PM PST 24
Finished Mar 07 02:48:10 PM PST 24
Peak memory 214468 kb
Host smart-3e1fc78b-e895-424f-8a51-c2581477eba3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4019487505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.4019487505
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.77004359
Short name T372
Test name
Test status
Simulation time 48295787 ps
CPU time 2.22 seconds
Started Mar 07 02:48:08 PM PST 24
Finished Mar 07 02:48:11 PM PST 24
Peak memory 207808 kb
Host smart-7aa14b15-21fc-43b4-a97b-d01cb1d9d244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77004359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.77004359
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1149331685
Short name T325
Test name
Test status
Simulation time 138455902 ps
CPU time 4.83 seconds
Started Mar 07 02:48:07 PM PST 24
Finished Mar 07 02:48:12 PM PST 24
Peak memory 214444 kb
Host smart-8ee4c25f-69c9-4465-a395-61f7414c7e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149331685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1149331685
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1444923504
Short name T556
Test name
Test status
Simulation time 117102733 ps
CPU time 5.83 seconds
Started Mar 07 02:48:05 PM PST 24
Finished Mar 07 02:48:11 PM PST 24
Peak memory 214504 kb
Host smart-0b19af13-7bd0-4492-90c1-de352dc4ad6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444923504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1444923504
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.400681589
Short name T610
Test name
Test status
Simulation time 227062819 ps
CPU time 3.16 seconds
Started Mar 07 02:48:06 PM PST 24
Finished Mar 07 02:48:09 PM PST 24
Peak memory 208800 kb
Host smart-6d2105b7-312e-401f-9d75-c20ff1e25cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400681589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.400681589
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.30744680
Short name T711
Test name
Test status
Simulation time 989391967 ps
CPU time 32.48 seconds
Started Mar 07 02:48:06 PM PST 24
Finished Mar 07 02:48:39 PM PST 24
Peak memory 209424 kb
Host smart-b73c3037-e49d-4262-9d44-1672c2f474e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30744680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.30744680
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2313555432
Short name T499
Test name
Test status
Simulation time 36358264 ps
CPU time 2.28 seconds
Started Mar 07 02:48:07 PM PST 24
Finished Mar 07 02:48:10 PM PST 24
Peak memory 206828 kb
Host smart-e05b73d4-c262-4905-b5e9-20eed38baef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313555432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2313555432
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1067637473
Short name T334
Test name
Test status
Simulation time 60136965 ps
CPU time 3.26 seconds
Started Mar 07 02:48:05 PM PST 24
Finished Mar 07 02:48:08 PM PST 24
Peak memory 208856 kb
Host smart-bdad5389-255b-4f25-858d-a64c17da3036
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067637473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1067637473
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2894757081
Short name T572
Test name
Test status
Simulation time 10514022707 ps
CPU time 53.65 seconds
Started Mar 07 02:48:06 PM PST 24
Finished Mar 07 02:49:00 PM PST 24
Peak memory 208796 kb
Host smart-9a31c543-8da7-4002-8f2d-c639727e9be9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894757081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2894757081
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1519088969
Short name T366
Test name
Test status
Simulation time 4022276881 ps
CPU time 44.7 seconds
Started Mar 07 02:48:06 PM PST 24
Finished Mar 07 02:48:51 PM PST 24
Peak memory 208724 kb
Host smart-a55712b3-1eeb-41ba-a24c-304c9fc1dd84
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519088969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1519088969
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2439357379
Short name T730
Test name
Test status
Simulation time 462959063 ps
CPU time 4.02 seconds
Started Mar 07 02:48:07 PM PST 24
Finished Mar 07 02:48:11 PM PST 24
Peak memory 208632 kb
Host smart-92f1ea2c-d5fb-4445-a7af-7ebae229fd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439357379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2439357379
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.4096807236
Short name T691
Test name
Test status
Simulation time 42128901 ps
CPU time 2.18 seconds
Started Mar 07 02:48:06 PM PST 24
Finished Mar 07 02:48:09 PM PST 24
Peak memory 207840 kb
Host smart-620d9682-84f5-4a71-91c4-f1782f76403a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096807236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.4096807236
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.493658350
Short name T201
Test name
Test status
Simulation time 536003521 ps
CPU time 13.36 seconds
Started Mar 07 02:48:09 PM PST 24
Finished Mar 07 02:48:22 PM PST 24
Peak memory 216944 kb
Host smart-07fbee4d-79c0-44b3-8466-f47dd1a20aef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493658350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.493658350
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2313205456
Short name T792
Test name
Test status
Simulation time 82824722 ps
CPU time 3.66 seconds
Started Mar 07 02:48:05 PM PST 24
Finished Mar 07 02:48:08 PM PST 24
Peak memory 207428 kb
Host smart-a04f5219-6c3c-452d-a86a-f6bb8851c3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313205456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2313205456
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.415293725
Short name T114
Test name
Test status
Simulation time 62210872 ps
CPU time 1.78 seconds
Started Mar 07 02:48:05 PM PST 24
Finished Mar 07 02:48:07 PM PST 24
Peak memory 209820 kb
Host smart-2437028f-79de-4bd0-9731-a48978952c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415293725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.415293725
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.4059618073
Short name T19
Test name
Test status
Simulation time 14583983 ps
CPU time 0.8 seconds
Started Mar 07 02:48:13 PM PST 24
Finished Mar 07 02:48:14 PM PST 24
Peak memory 206220 kb
Host smart-edae5e72-2268-41ea-b2ca-09e50e7972d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059618073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.4059618073
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2671336429
Short name T369
Test name
Test status
Simulation time 501993736 ps
CPU time 3.27 seconds
Started Mar 07 02:48:14 PM PST 24
Finished Mar 07 02:48:17 PM PST 24
Peak memory 215432 kb
Host smart-d4b90b49-0c4c-43e5-85c0-7e82c207b112
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2671336429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2671336429
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3577935190
Short name T698
Test name
Test status
Simulation time 52800471 ps
CPU time 2.07 seconds
Started Mar 07 02:48:19 PM PST 24
Finished Mar 07 02:48:22 PM PST 24
Peak memory 214756 kb
Host smart-fd1c6d30-7287-4c73-b415-eb2b57c93c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577935190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3577935190
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1860431840
Short name T192
Test name
Test status
Simulation time 47046081 ps
CPU time 2.72 seconds
Started Mar 07 02:48:15 PM PST 24
Finished Mar 07 02:48:18 PM PST 24
Peak memory 210360 kb
Host smart-643c6c76-cfe0-42e7-8584-1387c09431a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860431840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1860431840
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2103393590
Short name T346
Test name
Test status
Simulation time 683859141 ps
CPU time 12.28 seconds
Started Mar 07 02:48:11 PM PST 24
Finished Mar 07 02:48:23 PM PST 24
Peak memory 214508 kb
Host smart-34e82b3a-04de-4aae-81f4-df0cbe3dfffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103393590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2103393590
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2045430735
Short name T251
Test name
Test status
Simulation time 292406825 ps
CPU time 8.68 seconds
Started Mar 07 02:48:11 PM PST 24
Finished Mar 07 02:48:20 PM PST 24
Peak memory 214396 kb
Host smart-06062957-1d5b-4cb2-8a70-338b1e9f38e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045430735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2045430735
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3162400414
Short name T46
Test name
Test status
Simulation time 58640406 ps
CPU time 2.79 seconds
Started Mar 07 02:48:17 PM PST 24
Finished Mar 07 02:48:20 PM PST 24
Peak memory 222580 kb
Host smart-744dba52-96cd-468e-b099-549f5f82aa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162400414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3162400414
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2079910351
Short name T470
Test name
Test status
Simulation time 417650950 ps
CPU time 9.36 seconds
Started Mar 07 02:48:12 PM PST 24
Finished Mar 07 02:48:22 PM PST 24
Peak memory 209916 kb
Host smart-4d48267c-c329-4744-b368-760a6f6f4670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079910351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2079910351
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.497790357
Short name T656
Test name
Test status
Simulation time 34338177 ps
CPU time 2.28 seconds
Started Mar 07 02:48:11 PM PST 24
Finished Mar 07 02:48:13 PM PST 24
Peak memory 206880 kb
Host smart-37bc9ba1-329e-4e3a-9b15-2f019f141323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497790357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.497790357
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.4233629470
Short name T847
Test name
Test status
Simulation time 39013448 ps
CPU time 1.9 seconds
Started Mar 07 02:48:18 PM PST 24
Finished Mar 07 02:48:20 PM PST 24
Peak memory 206792 kb
Host smart-7d084e4e-7106-40b4-bad3-f7f0afefffdb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233629470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.4233629470
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.4257771492
Short name T581
Test name
Test status
Simulation time 95147513 ps
CPU time 2.61 seconds
Started Mar 07 02:48:12 PM PST 24
Finished Mar 07 02:48:15 PM PST 24
Peak memory 206908 kb
Host smart-32290e62-c955-48e7-9aab-d0a613ed523a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257771492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.4257771492
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2566250801
Short name T442
Test name
Test status
Simulation time 601956336 ps
CPU time 6.15 seconds
Started Mar 07 02:48:10 PM PST 24
Finished Mar 07 02:48:16 PM PST 24
Peak memory 208576 kb
Host smart-9704c293-4f86-4cb1-a5de-889c689b3609
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566250801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2566250801
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.65349851
Short name T257
Test name
Test status
Simulation time 160027236 ps
CPU time 3.48 seconds
Started Mar 07 02:48:11 PM PST 24
Finished Mar 07 02:48:14 PM PST 24
Peak memory 210196 kb
Host smart-e4f7a221-bfe2-420d-a843-5714aff241fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65349851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.65349851
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.248190384
Short name T710
Test name
Test status
Simulation time 243027605 ps
CPU time 1.88 seconds
Started Mar 07 02:48:14 PM PST 24
Finished Mar 07 02:48:16 PM PST 24
Peak memory 206348 kb
Host smart-64a37537-ee12-4dfc-a8cd-36727e711924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248190384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.248190384
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2953144229
Short name T200
Test name
Test status
Simulation time 680764801 ps
CPU time 6.61 seconds
Started Mar 07 02:48:12 PM PST 24
Finished Mar 07 02:48:19 PM PST 24
Peak memory 216688 kb
Host smart-3551c609-114b-40bc-9935-db092dac37d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953144229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2953144229
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2820613266
Short name T603
Test name
Test status
Simulation time 176689152 ps
CPU time 3.05 seconds
Started Mar 07 02:48:10 PM PST 24
Finished Mar 07 02:48:13 PM PST 24
Peak memory 208076 kb
Host smart-d150f887-90dc-4468-9a63-a8056c7bc00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820613266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2820613266
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2823091248
Short name T564
Test name
Test status
Simulation time 79057612 ps
CPU time 3.26 seconds
Started Mar 07 02:48:14 PM PST 24
Finished Mar 07 02:48:18 PM PST 24
Peak memory 210096 kb
Host smart-90cb72ce-4258-4fb8-a8f6-0f00427d6529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823091248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2823091248
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1354942721
Short name T732
Test name
Test status
Simulation time 45653307 ps
CPU time 0.86 seconds
Started Mar 07 02:48:19 PM PST 24
Finished Mar 07 02:48:21 PM PST 24
Peak memory 206188 kb
Host smart-efdbe62a-ed87-479f-848d-0261fd7f41cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354942721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1354942721
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3183570817
Short name T414
Test name
Test status
Simulation time 35842947 ps
CPU time 2.78 seconds
Started Mar 07 02:48:12 PM PST 24
Finished Mar 07 02:48:15 PM PST 24
Peak memory 214432 kb
Host smart-79ebb70b-cced-4ba6-a471-eaa62060dbbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3183570817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3183570817
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2897656961
Short name T765
Test name
Test status
Simulation time 301692894 ps
CPU time 3.96 seconds
Started Mar 07 02:48:11 PM PST 24
Finished Mar 07 02:48:15 PM PST 24
Peak memory 214492 kb
Host smart-c1d12a4f-e957-486c-822e-1c41247b7eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897656961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2897656961
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1440874869
Short name T645
Test name
Test status
Simulation time 239941775 ps
CPU time 5.14 seconds
Started Mar 07 02:48:11 PM PST 24
Finished Mar 07 02:48:16 PM PST 24
Peak memory 220900 kb
Host smart-28a29ec8-bb01-42ea-8259-22ba7c8f7b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440874869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1440874869
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1225171263
Short name T727
Test name
Test status
Simulation time 8142701266 ps
CPU time 61.67 seconds
Started Mar 07 02:48:18 PM PST 24
Finished Mar 07 02:49:20 PM PST 24
Peak memory 224524 kb
Host smart-b8cfbccf-3192-4222-9b43-c72d6ef28957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225171263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1225171263
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1905134257
Short name T45
Test name
Test status
Simulation time 269178263 ps
CPU time 3.81 seconds
Started Mar 07 02:48:11 PM PST 24
Finished Mar 07 02:48:15 PM PST 24
Peak memory 214528 kb
Host smart-0848e6df-afe9-40a2-abab-a8e3cf9351b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905134257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1905134257
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1950987138
Short name T544
Test name
Test status
Simulation time 131712195 ps
CPU time 5.95 seconds
Started Mar 07 02:48:12 PM PST 24
Finished Mar 07 02:48:18 PM PST 24
Peak memory 207848 kb
Host smart-64a64a46-df5e-49e0-b87f-46a62339c86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950987138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1950987138
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.751524360
Short name T775
Test name
Test status
Simulation time 22866526 ps
CPU time 2.06 seconds
Started Mar 07 02:48:16 PM PST 24
Finished Mar 07 02:48:18 PM PST 24
Peak memory 208440 kb
Host smart-fbf55a8b-c61c-47e0-b41a-2ee5cdff84ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751524360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.751524360
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2757426089
Short name T136
Test name
Test status
Simulation time 64845287 ps
CPU time 3.02 seconds
Started Mar 07 02:48:11 PM PST 24
Finished Mar 07 02:48:14 PM PST 24
Peak memory 208212 kb
Host smart-04339d75-9f9a-4c0e-9791-b9716b10889d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757426089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2757426089
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1247043580
Short name T511
Test name
Test status
Simulation time 134326345 ps
CPU time 3.46 seconds
Started Mar 07 02:48:13 PM PST 24
Finished Mar 07 02:48:17 PM PST 24
Peak memory 206936 kb
Host smart-a884295b-3f14-44cd-8409-d9c6205815b3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247043580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1247043580
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2842344283
Short name T305
Test name
Test status
Simulation time 191819140 ps
CPU time 6.65 seconds
Started Mar 07 02:48:10 PM PST 24
Finished Mar 07 02:48:17 PM PST 24
Peak memory 208564 kb
Host smart-1d5a64ef-7cbe-44a2-a58b-c39a9a74ad58
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842344283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2842344283
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.589920118
Short name T796
Test name
Test status
Simulation time 41730290 ps
CPU time 2.26 seconds
Started Mar 07 02:48:14 PM PST 24
Finished Mar 07 02:48:17 PM PST 24
Peak memory 208952 kb
Host smart-75937672-647d-4fa3-8c25-00d10128fc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589920118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.589920118
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3404913446
Short name T615
Test name
Test status
Simulation time 403349664 ps
CPU time 2.9 seconds
Started Mar 07 02:48:11 PM PST 24
Finished Mar 07 02:48:14 PM PST 24
Peak memory 207100 kb
Host smart-5dd5a323-1736-4056-afb9-2db26472223e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404913446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3404913446
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.4136660768
Short name T306
Test name
Test status
Simulation time 137067185 ps
CPU time 3.53 seconds
Started Mar 07 02:48:18 PM PST 24
Finished Mar 07 02:48:22 PM PST 24
Peak memory 209516 kb
Host smart-c2adade4-52b9-46b3-a40e-349d81dacbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136660768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.4136660768
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1355250066
Short name T177
Test name
Test status
Simulation time 46876273 ps
CPU time 2.78 seconds
Started Mar 07 02:48:18 PM PST 24
Finished Mar 07 02:48:21 PM PST 24
Peak memory 209952 kb
Host smart-dbae9c11-4913-423f-9a33-e351018c9d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355250066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1355250066
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3798127454
Short name T791
Test name
Test status
Simulation time 31307267 ps
CPU time 0.78 seconds
Started Mar 07 02:48:18 PM PST 24
Finished Mar 07 02:48:19 PM PST 24
Peak memory 206028 kb
Host smart-0992c188-1e19-46db-8e2d-3b21ee0d9038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798127454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3798127454
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.101898028
Short name T365
Test name
Test status
Simulation time 7440221985 ps
CPU time 23.96 seconds
Started Mar 07 02:48:23 PM PST 24
Finished Mar 07 02:48:47 PM PST 24
Peak memory 222600 kb
Host smart-1a2da1e5-49ee-4410-9c3e-517b8d9a1cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101898028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.101898028
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3964942145
Short name T657
Test name
Test status
Simulation time 96893559 ps
CPU time 1.82 seconds
Started Mar 07 02:48:17 PM PST 24
Finished Mar 07 02:48:19 PM PST 24
Peak memory 207888 kb
Host smart-355e24d3-de3e-4069-a460-9e2fbada98d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964942145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3964942145
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1369506279
Short name T641
Test name
Test status
Simulation time 198438458 ps
CPU time 2.8 seconds
Started Mar 07 02:48:20 PM PST 24
Finished Mar 07 02:48:23 PM PST 24
Peak memory 218076 kb
Host smart-1aee0d63-b676-452e-8899-9a69fd9ffcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369506279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1369506279
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2185989682
Short name T149
Test name
Test status
Simulation time 8973012025 ps
CPU time 23.86 seconds
Started Mar 07 02:48:18 PM PST 24
Finished Mar 07 02:48:42 PM PST 24
Peak memory 208772 kb
Host smart-fdb7274d-1e8e-45d7-aab2-ba1c05e09bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185989682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2185989682
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3587872261
Short name T611
Test name
Test status
Simulation time 73555704 ps
CPU time 3.35 seconds
Started Mar 07 02:48:20 PM PST 24
Finished Mar 07 02:48:24 PM PST 24
Peak memory 206852 kb
Host smart-f1a55eee-cb08-43ea-ad45-3bed474328ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587872261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3587872261
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2958830020
Short name T784
Test name
Test status
Simulation time 61780970 ps
CPU time 2.91 seconds
Started Mar 07 02:48:17 PM PST 24
Finished Mar 07 02:48:20 PM PST 24
Peak memory 206960 kb
Host smart-d9da4e44-ef0b-40b2-bd18-ad2b8a63f1e3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958830020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2958830020
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2077835816
Short name T90
Test name
Test status
Simulation time 79837120 ps
CPU time 3.16 seconds
Started Mar 07 02:48:17 PM PST 24
Finished Mar 07 02:48:20 PM PST 24
Peak memory 206608 kb
Host smart-b71488e2-828f-4dd4-9e3f-8f175c79639a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077835816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2077835816
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2912594495
Short name T666
Test name
Test status
Simulation time 45628034 ps
CPU time 1.92 seconds
Started Mar 07 02:48:18 PM PST 24
Finished Mar 07 02:48:20 PM PST 24
Peak memory 208644 kb
Host smart-593a7ea5-b081-4594-bbf9-5510f7db8847
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912594495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2912594495
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2804459288
Short name T722
Test name
Test status
Simulation time 821080509 ps
CPU time 2.23 seconds
Started Mar 07 02:48:17 PM PST 24
Finished Mar 07 02:48:19 PM PST 24
Peak memory 209180 kb
Host smart-c2939d52-fa78-47b1-b73a-17bdbd594f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804459288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2804459288
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.36032197
Short name T726
Test name
Test status
Simulation time 227838980 ps
CPU time 6.46 seconds
Started Mar 07 02:48:18 PM PST 24
Finished Mar 07 02:48:24 PM PST 24
Peak memory 206756 kb
Host smart-692227d9-5dfa-446e-9551-2ebdb158296b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36032197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.36032197
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1431965369
Short name T454
Test name
Test status
Simulation time 82553694 ps
CPU time 4 seconds
Started Mar 07 02:48:18 PM PST 24
Finished Mar 07 02:48:22 PM PST 24
Peak memory 208392 kb
Host smart-1615b844-02e8-4972-923b-f9038c94af82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431965369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1431965369
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2125804397
Short name T813
Test name
Test status
Simulation time 74316764 ps
CPU time 3.15 seconds
Started Mar 07 02:48:18 PM PST 24
Finished Mar 07 02:48:21 PM PST 24
Peak memory 209860 kb
Host smart-b3eb020d-486f-4351-b7a0-e5a04d8a7e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125804397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2125804397
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3344546604
Short name T510
Test name
Test status
Simulation time 21816802 ps
CPU time 0.77 seconds
Started Mar 07 02:48:27 PM PST 24
Finished Mar 07 02:48:28 PM PST 24
Peak memory 206124 kb
Host smart-9c678fbb-6125-4a42-9d5a-0293e802e258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344546604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3344546604
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1858303709
Short name T535
Test name
Test status
Simulation time 386768848 ps
CPU time 4.41 seconds
Started Mar 07 02:48:19 PM PST 24
Finished Mar 07 02:48:23 PM PST 24
Peak memory 208808 kb
Host smart-884b6e34-4963-477c-94a5-96a72289f90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858303709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1858303709
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3327070168
Short name T483
Test name
Test status
Simulation time 11009110247 ps
CPU time 29.18 seconds
Started Mar 07 02:48:18 PM PST 24
Finished Mar 07 02:48:48 PM PST 24
Peak memory 209620 kb
Host smart-dabd600b-8b16-4552-ade5-68ed23177e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327070168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3327070168
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2101549977
Short name T97
Test name
Test status
Simulation time 79593964 ps
CPU time 4.06 seconds
Started Mar 07 02:48:23 PM PST 24
Finished Mar 07 02:48:28 PM PST 24
Peak memory 214456 kb
Host smart-2149348e-a8f0-4ef8-84e4-72884f17218e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101549977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2101549977
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1639586429
Short name T224
Test name
Test status
Simulation time 625863975 ps
CPU time 4.37 seconds
Started Mar 07 02:48:17 PM PST 24
Finished Mar 07 02:48:22 PM PST 24
Peak memory 209524 kb
Host smart-27b3769f-575a-4228-bb21-7e8a590c347d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639586429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1639586429
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3559950905
Short name T413
Test name
Test status
Simulation time 419298774 ps
CPU time 6.86 seconds
Started Mar 07 02:48:17 PM PST 24
Finished Mar 07 02:48:24 PM PST 24
Peak memory 209484 kb
Host smart-ece2862a-e02c-4099-83c7-1c827f34d4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559950905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3559950905
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1519471330
Short name T506
Test name
Test status
Simulation time 197538625 ps
CPU time 1.84 seconds
Started Mar 07 02:48:17 PM PST 24
Finished Mar 07 02:48:19 PM PST 24
Peak memory 206820 kb
Host smart-0c15ed05-090f-461f-b496-ba698a83d9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519471330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1519471330
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.4226429448
Short name T559
Test name
Test status
Simulation time 129144473 ps
CPU time 5.52 seconds
Started Mar 07 02:48:18 PM PST 24
Finished Mar 07 02:48:24 PM PST 24
Peak memory 208516 kb
Host smart-df5e4bc2-49d9-4264-9ab4-a3fe8582c098
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226429448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.4226429448
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.4076359850
Short name T465
Test name
Test status
Simulation time 148262545 ps
CPU time 5.01 seconds
Started Mar 07 02:48:18 PM PST 24
Finished Mar 07 02:48:23 PM PST 24
Peak memory 206900 kb
Host smart-b437d3ba-f8ce-42a3-be12-0e059c69c68f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076359850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.4076359850
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.470325105
Short name T338
Test name
Test status
Simulation time 207752351 ps
CPU time 7.9 seconds
Started Mar 07 02:48:18 PM PST 24
Finished Mar 07 02:48:26 PM PST 24
Peak memory 206912 kb
Host smart-e1db4e12-a869-4e66-9930-13f2e23c1381
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470325105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.470325105
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3553914091
Short name T350
Test name
Test status
Simulation time 6891835631 ps
CPU time 31.92 seconds
Started Mar 07 02:48:26 PM PST 24
Finished Mar 07 02:48:59 PM PST 24
Peak memory 214548 kb
Host smart-da03e8f6-5c0e-4e0f-8d0f-8e7f4b8daaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553914091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3553914091
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.276526343
Short name T628
Test name
Test status
Simulation time 415491317 ps
CPU time 3.45 seconds
Started Mar 07 02:48:19 PM PST 24
Finished Mar 07 02:48:22 PM PST 24
Peak memory 208348 kb
Host smart-f4416097-5687-4ef7-b23e-75df0b62e13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276526343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.276526343
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1582209687
Short name T87
Test name
Test status
Simulation time 3284079787 ps
CPU time 17.35 seconds
Started Mar 07 02:48:26 PM PST 24
Finished Mar 07 02:48:43 PM PST 24
Peak memory 208120 kb
Host smart-ca377134-87f0-485b-ab85-3e5c7c2a68d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582209687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1582209687
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2543200772
Short name T661
Test name
Test status
Simulation time 532178709 ps
CPU time 10.72 seconds
Started Mar 07 02:48:23 PM PST 24
Finished Mar 07 02:48:34 PM PST 24
Peak memory 222824 kb
Host smart-6ecc99db-ea73-4eb6-a8e6-1a8fca11c377
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543200772 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2543200772
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2785983439
Short name T592
Test name
Test status
Simulation time 581136584 ps
CPU time 7.05 seconds
Started Mar 07 02:48:18 PM PST 24
Finished Mar 07 02:48:25 PM PST 24
Peak memory 207952 kb
Host smart-07d60053-6a7a-44cc-9493-18a762126b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785983439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2785983439
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3848541645
Short name T865
Test name
Test status
Simulation time 482262946 ps
CPU time 2.08 seconds
Started Mar 07 02:48:24 PM PST 24
Finished Mar 07 02:48:27 PM PST 24
Peak memory 210052 kb
Host smart-3a171b38-9adf-4aae-87a4-2c5b14205d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848541645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3848541645
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%