SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
87.50 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 1 | 7 | 87.50 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
invalid_hw_input_cp | 8 | 1 | 7 | 87.50 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 8 | 1 | 7 | 87.50 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[FlashCreatorSeedInvalid] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[OtpRootKeyInvalid] | 888 | 1 | T17 | 20 | T21 | 10 | T22 | 28 | ||||
auto[OtpRootKeyValidLow] | 210 | 1 | T17 | 2 | T21 | 7 | T22 | 3 | ||||
auto[LcStateInvalid] | 142 | 1 | T88 | 10 | T89 | 36 | T326 | 12 | ||||
auto[OtpDevIdInvalid] | 144 | 1 | T76 | 12 | T87 | 24 | T90 | 48 | ||||
auto[RomDigestInvalid] | 96 | 1 | T76 | 36 | T375 | 36 | T376 | 24 | ||||
auto[RomDigestValidLow] | 96 | 1 | T277 | 36 | T377 | 12 | T378 | 12 | ||||
auto[FlashOwnerSeedInvalid] | 96 | 1 | T91 | 60 | T92 | 36 | - | - |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |