Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.60	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	15	34	69.39

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	14	21	60.00	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	59	1			T3	1		T6	1		T48	1
auto[OpGenId]	13	1			T52	1		T24	1		T50	1
auto[OpGenSwOut]	16	1			T51	1		T218	1		T40	1
auto[OpGenHwOut]	15	1			T1	1		T23	1		T7	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1556	1			T40	1		T56	1		T41	1
auto[StInit]	75	1			T1	1		T3	1		T23	1
auto[StCreatorRootKey]	51	1			T4	1		T6	1		T48	1
auto[StOwnerIntKey]	39	1			T51	1		T40	1		T53	1
auto[StOwnerKey]	36	1			T57	1		T58	1		T50	1
auto[StDisabled]	433	1			T40	15		T56	7		T47	11
auto[StInvalid]	42	1			T17	1		T32	1		T22	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3194

1

T1

1

T2

1

T3

1

auto[1]

103

1

T1

1

T3

1

T6

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1547	1			T40	1		T56	1		T47	2
auto[StReset]	auto[1]	9	1			T41	1		T44	1		T45	3
auto[StInit]	auto[0]	30	1			T46	1		T99	1		T56	2
auto[StInit]	auto[1]	45	1			T1	1		T3	1		T23	1
auto[StCreatorRootKey]	auto[0]	32	1			T4	1		T40	1		T50	2
auto[StCreatorRootKey]	auto[1]	19	1			T6	1		T48	1		T40	2
auto[StOwnerIntKey]	auto[0]	26	1			T53	1		T219	1		T220	1
auto[StOwnerIntKey]	auto[1]	13	1			T51	1		T40	1		T52	1
auto[StOwnerKey]	auto[0]	30	1			T57	1		T58	1		T50	1
auto[StOwnerKey]	auto[1]	6	1			T60	1		T221	2		T222	1
auto[StDisabled]	auto[0]	422	1			T40	14		T56	7		T47	11
auto[StDisabled]	auto[1]	11	1			T40	1		T223	1		T61	1
auto[StInvalid]	auto[0]	42	1			T17	1		T32	1		T22	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	14	21	60.00	14

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	3
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpGenSwOut]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	8	1			T41	1		T44	1		T45	3
auto[StReset]	auto[OpGenId]	1	1			T35	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	22	1			T3	1		T130	1		T224	1
auto[StInit]	auto[OpGenId]	6	1			T24	1		T50	1		T225	1
auto[StInit]	auto[OpGenSwOut]	8	1			T218	1		T125	1		T226	1
auto[StInit]	auto[OpGenHwOut]	9	1			T1	1		T23	1		T7	1
auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T6	1		T48	1		T40	1
auto[StCreatorRootKey]	auto[OpGenId]	2	1			T9	1		T227	1		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T45	1		T228	1		T229	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	2	1			T40	1		T230	1		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T40	1		T54	1		T231	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T52	1		T29	1		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T51	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	2	1			T232	1		T233	1		-	-
auto[StOwnerKey]	auto[OpAdvance]	4	1			T60	1		T221	1		T222	1
auto[StOwnerKey]	auto[OpGenId]	1	1			T221	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T234	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	6	1			T223	1		T61	1		T231	1
auto[StDisabled]	auto[OpGenId]	1	1			T235	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	3	1			T40	1		T236	1		T221	1
auto[StDisabled]	auto[OpGenHwOut]	1	1			T237	1		-	-		-	-