Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11156

1

T2

18

T3

1

T4

1

auto[Attestation]

7936

1

T2

11

T4

4

T5

6

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2787	1			T2	2		T4	3		T5	4
auto[Aes]	3305	1			T2	5		T5	1		T6	1
auto[Kmac]	3468	1			T2	3		T5	2		T6	1
auto[Otbn]	3473	1			T2	8		T3	1		T5	3

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7825	1			T1	1		T2	8		T3	1
auto[OpGenId]	6059	1			T2	11		T4	2		T5	4
auto[OpGenSwOut]	6119	1			T2	6		T4	2		T5	3
auto[OpGenHwOut]	6914	1			T2	12		T3	1		T4	1
auto[OpDisable]	140	1			T42	1		T39	1		T43	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10201

1

T1

1

T2

12

T3

1

auto[OpDoneFail]

16856

1

T2

25

T3

1

T4

2

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6112	1			T1	1		T2	8		T3	1
auto[StInit]	4419	1			T2	6		T3	1		T4	3
auto[StCreatorRootKey]	3018	1			T2	2		T4	3		T5	4
auto[StOwnerIntKey]	2675	1			T2	6		T5	8		T14	2
auto[StOwnerKey]	2385	1			T2	2		T14	2		T15	5
auto[StDisabled]	7537	1			T2	13		T14	7		T15	11
auto[StInvalid]	911	1			T17	18		T32	26		T22	12

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	325	1			T15	1		T17	2		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	121	1			T5	1		T16	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	70	1			T4	1		T187	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	63	1			T56	1		T52	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	76	1			T81	1		T100	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	226	1			T16	1		T37	1		T188	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	32	1			T32	1		T78	2		T88	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	314	1			T16	1		T17	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	130	1			T38	1		T100	1		T43	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	77	1			T85	2		T40	2		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	72	1			T189	1		T190	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	63	1			T191	1		T40	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	187	1			T15	1		T16	2		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	36	1			T17	3		T32	3		T78	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	313	1			T2	1		T16	3		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	135	1			T2	1		T17	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T16	1		T192	1		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	62	1			T57	1		T191	2		T47	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	59	1			T192	2		T191	1		T193	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	223	1			T42	1		T81	1		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	30	1			T78	1		T88	2		T194	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	309	1			T2	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	125	1			T2	1		T100	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	82	1			T55	1		T191	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	69	1			T16	1		T56	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	72	1			T16	1		T195	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	172	1			T2	1		T15	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	27	1			T17	1		T32	2		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	65	1			T40	2		T56	1		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	124	1			T4	1		T116	1		T22	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	80	1			T5	1		T192	1		T190	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	76	1			T2	1		T196	1		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	46	1			T193	1		T197	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	216	1			T15	1		T16	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	27	1			T78	3		T198	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	66	1			T40	2		T47	4		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	109	1			T196	1		T22	1		T67	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	77	1			T191	1		T40	2		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	66	1			T116	2		T190	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	60	1			T200	1		T108	1		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	203	1			T15	1		T16	1		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	24	1			T198	2		T202	1		T203	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	78	1			T40	6		T56	1		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	129	1			T39	1		T38	1		T81	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	96	1			T16	1		T192	2		T195	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	69	1			T51	1		T200	1		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	70	1			T16	1		T100	1		T193	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	218	1			T16	1		T189	1		T40	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	22	1			T78	1		T205	1		T194	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	73	1			T40	3		T56	1		T47	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	130	1			T188	1		T43	1		T22	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	66	1			T206	1		T200	1		T40	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	66	1			T5	1		T204	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	53	1			T16	1		T57	1		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	224	1			T16	1		T38	2		T192	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	25	1			T32	1		T88	2		T205	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	239	1			T15	2		T16	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	101	1			T21	1		T57	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	79	1			T5	1		T208	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	43	1			T5	1		T192	1		T190	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	38	1			T15	1		T37	1		T100	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	163	1			T100	2		T188	1		T189	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	21	1			T209	1		T198	1		T199	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	446	1			T15	1		T17	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	128	1			T2	1		T192	1		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	103	1			T55	1		T40	1		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	80	1			T5	1		T16	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	67	1			T2	1		T210	1		T208	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	262	1			T2	1		T42	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	25	1			T32	2		T205	2		T199	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	429	1			T14	3		T17	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	135	1			T2	1		T14	1		T21	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	90	1			T14	1		T82	1		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	77	1			T14	1		T211	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	71	1			T82	1		T189	1		T212	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	288	1			T14	2		T15	2		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	28	1			T17	1		T32	1		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	454	1			T15	2		T17	2		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	144	1			T3	1		T5	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	110	1			T84	1		T213	1		T214	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	103	1			T38	1		T215	1		T216	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	92	1			T83	1		T196	1		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	260	1			T2	2		T83	2		T84	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	42	1			T17	1		T78	1		T88	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	53	1			T22	1		T40	3		T47	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	110	1			T4	1		T17	1		T21	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	69	1			T15	1		T116	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	74	1			T2	1		T55	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	46	1			T16	1		T100	1		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	172	1			T39	1		T38	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	32	1			T17	1		T32	3		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	41	1			T40	2		T47	2		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	128	1			T6	1		T15	1		T21	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	102	1			T116	1		T40	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	81	1			T2	2		T116	1		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	80	1			T16	1		T196	1		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	262	1			T85	1		T100	1		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	16	1			T22	1		T78	1		T95	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	45	1			T40	1		T47	1		T63	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	169	1			T6	1		T15	1		T100	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	83	1			T5	1		T56	1		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	84	1			T5	1		T16	1		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	97	1			T14	1		T211	1		T210	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	244	1			T14	2		T37	1		T100	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	33	1			T17	1		T22	1		T205	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	40	1			T40	5		T56	2		T47	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	149	1			T2	1		T39	1		T21	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	116	1			T38	1		T83	1		T217	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	82	1			T2	1		T5	1		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	92	1			T38	1		T84	1		T196	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	272	1			T2	1		T15	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	24	1			T22	1		T95	1		T205	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	194	1			T4	1		T81	1		T100	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	719	1			T5	1		T15	1		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	200	1			T85	2		T189	1		T190	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	679	1			T15	1		T16	3		T17	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	196	1			T16	1		T192	3		T57	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	717	1			T2	2		T16	3		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	208	1			T16	2		T195	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	648	1			T2	3		T15	2		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	187	1			T2	1		T5	1		T196	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	447	1			T4	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	192	1			T116	2		T190	1		T200	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	413	1			T15	1		T16	1		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	211	1			T16	2		T192	2		T100	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	471	1			T16	1		T39	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	171	1			T5	1		T16	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	466	1			T16	1		T38	2		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	148	1			T5	2		T15	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	536	1			T15	2		T16	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	231	1			T2	1		T5	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	880	1			T2	2		T15	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	230	1			T14	2		T82	2		T211	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	888	1			T2	1		T14	6		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	290	1			T38	1		T83	1		T84	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	915	1			T2	2		T3	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	170	1			T2	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	386	1			T4	1		T17	2		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	250	1			T2	2		T16	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	460	1			T6	1		T15	1		T21	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	253	1			T5	2		T14	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	502	1			T6	1		T14	2		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	277	1			T2	1		T5	1		T38	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	498	1			T2	2		T15	1		T37	1