Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31064

1

T1

2

T2

41

T3

3

auto[1]

287

1

T16

6

T38

6

T116

14

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31074	1			T1	2		T2	41		T3	3
auto[134217728:268435455]	11	1			T16	1		T38	1		T201	1
auto[268435456:402653183]	8	1			T109	1		T356	1		T303	2
auto[402653184:536870911]	4	1			T116	1		T201	1		T387	1
auto[536870912:671088639]	11	1			T116	1		T201	1		T369	1
auto[671088640:805306367]	16	1			T16	1		T116	3		T108	1
auto[805306368:939524095]	13	1			T16	1		T108	1		T238	1
auto[939524096:1073741823]	10	1			T201	1		T369	1		T386	1
auto[1073741824:1207959551]	8	1			T201	1		T320	1		T401	1
auto[1207959552:1342177279]	10	1			T38	2		T116	1		T366	1
auto[1342177280:1476395007]	6	1			T116	1		T238	1		T256	2
auto[1476395008:1610612735]	9	1			T291	1		T356	1		T320	1
auto[1610612736:1744830463]	7	1			T38	1		T116	1		T366	1
auto[1744830464:1879048191]	10	1			T201	1		T356	1		T402	1
auto[1879048192:2013265919]	8	1			T366	1		T244	1		T387	1
auto[2013265920:2147483647]	5	1			T291	1		T366	1		T402	1
auto[2147483648:2281701375]	10	1			T116	1		T108	1		T265	1
auto[2281701376:2415919103]	6	1			T108	2		T368	1		T308	1
auto[2415919104:2550136831]	8	1			T38	1		T108	1		T403	1
auto[2550136832:2684354559]	9	1			T16	1		T291	2		T366	1
auto[2684354560:2818572287]	8	1			T16	1		T291	1		T238	1
auto[2818572288:2952790015]	7	1			T291	1		T246	1		T244	1
auto[2952790016:3087007743]	6	1			T116	1		T108	1		T256	1
auto[3087007744:3221225471]	9	1			T291	1		T238	1		T246	1
auto[3221225472:3355443199]	9	1			T116	1		T244	1		T356	1
auto[3355443200:3489660927]	14	1			T108	1		T201	1		T291	1
auto[3489660928:3623878655]	11	1			T108	1		T201	1		T246	1
auto[3623878656:3758096383]	9	1			T366	1		T265	1		T320	1
auto[3758096384:3892314111]	3	1			T16	1		T239	1		T338	1
auto[3892314112:4026531839]	7	1			T38	1		T108	1		T320	1
auto[4026531840:4160749567]	16	1			T116	1		T108	1		T201	1
auto[4160749568:4294967295]	9	1			T116	2		T108	1		T291	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31064	1			T1	2		T2	41		T3	3
auto[0:134217727]	auto[1]	10	1			T108	1		T308	1		T401	1
auto[134217728:268435455]	auto[1]	11	1			T16	1		T38	1		T201	1
auto[268435456:402653183]	auto[1]	8	1			T109	1		T356	1		T303	2
auto[402653184:536870911]	auto[1]	4	1			T116	1		T201	1		T387	1
auto[536870912:671088639]	auto[1]	11	1			T116	1		T201	1		T369	1
auto[671088640:805306367]	auto[1]	16	1			T16	1		T116	3		T108	1
auto[805306368:939524095]	auto[1]	13	1			T16	1		T108	1		T238	1
auto[939524096:1073741823]	auto[1]	10	1			T201	1		T369	1		T386	1
auto[1073741824:1207959551]	auto[1]	8	1			T201	1		T320	1		T401	1
auto[1207959552:1342177279]	auto[1]	10	1			T38	2		T116	1		T366	1
auto[1342177280:1476395007]	auto[1]	6	1			T116	1		T238	1		T256	2
auto[1476395008:1610612735]	auto[1]	9	1			T291	1		T356	1		T320	1
auto[1610612736:1744830463]	auto[1]	7	1			T38	1		T116	1		T366	1
auto[1744830464:1879048191]	auto[1]	10	1			T201	1		T356	1		T402	1
auto[1879048192:2013265919]	auto[1]	8	1			T366	1		T244	1		T387	1
auto[2013265920:2147483647]	auto[1]	5	1			T291	1		T366	1		T402	1
auto[2147483648:2281701375]	auto[1]	10	1			T116	1		T108	1		T265	1
auto[2281701376:2415919103]	auto[1]	6	1			T108	2		T368	1		T308	1
auto[2415919104:2550136831]	auto[1]	8	1			T38	1		T108	1		T403	1
auto[2550136832:2684354559]	auto[1]	9	1			T16	1		T291	2		T366	1
auto[2684354560:2818572287]	auto[1]	8	1			T16	1		T291	1		T238	1
auto[2818572288:2952790015]	auto[1]	7	1			T291	1		T246	1		T244	1
auto[2952790016:3087007743]	auto[1]	6	1			T116	1		T108	1		T256	1
auto[3087007744:3221225471]	auto[1]	9	1			T291	1		T238	1		T246	1
auto[3221225472:3355443199]	auto[1]	9	1			T116	1		T244	1		T356	1
auto[3355443200:3489660927]	auto[1]	14	1			T108	1		T201	1		T291	1
auto[3489660928:3623878655]	auto[1]	11	1			T108	1		T201	1		T246	1
auto[3623878656:3758096383]	auto[1]	9	1			T366	1		T265	1		T320	1
auto[3758096384:3892314111]	auto[1]	3	1			T16	1		T239	1		T338	1
auto[3892314112:4026531839]	auto[1]	7	1			T38	1		T108	1		T320	1
auto[4026531840:4160749567]	auto[1]	16	1			T116	1		T108	1		T201	1
auto[4160749568:4294967295]	auto[1]	9	1			T116	2		T108	1		T291	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1589

1

T1

4

T2

1

T3

1

auto[1]

1690

1

T1

1

T2

2

T3

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	84	1			T1	2		T32	1		T190	1
auto[134217728:268435455]	98	1			T15	1		T116	1		T40	3
auto[268435456:402653183]	104	1			T1	1		T37	1		T189	1
auto[402653184:536870911]	111	1			T1	1		T85	1		T46	1
auto[536870912:671088639]	111	1			T2	1		T17	1		T196	1
auto[671088640:805306367]	105	1			T38	1		T218	1		T193	2
auto[805306368:939524095]	102	1			T2	1		T38	1		T196	1
auto[939524096:1073741823]	120	1			T192	1		T40	2		T56	2
auto[1073741824:1207959551]	120	1			T15	1		T17	1		T21	1
auto[1207959552:1342177279]	87	1			T39	1		T116	1		T218	1
auto[1342177280:1476395007]	96	1			T16	1		T192	1		T189	1
auto[1476395008:1610612735]	110	1			T16	1		T37	1		T38	1
auto[1610612736:1744830463]	102	1			T37	1		T196	1		T100	1
auto[1744830464:1879048191]	99	1			T21	1		T196	1		T192	1
auto[1879048192:2013265919]	103	1			T51	1		T191	1		T7	1
auto[2013265920:2147483647]	108	1			T1	1		T6	1		T16	1
auto[2147483648:2281701375]	86	1			T16	1		T55	1		T48	1
auto[2281701376:2415919103]	112	1			T23	1		T38	1		T192	1
auto[2415919104:2550136831]	89	1			T3	1		T5	1		T16	1
auto[2550136832:2684354559]	90	1			T40	2		T77	1		T224	1
auto[2684354560:2818572287]	117	1			T5	1		T17	2		T39	1
auto[2818572288:2952790015]	109	1			T2	1		T15	1		T21	1
auto[2952790016:3087007743]	102	1			T85	1		T189	1		T218	1
auto[3087007744:3221225471]	105	1			T17	1		T21	1		T85	1
auto[3221225472:3355443199]	104	1			T16	1		T17	1		T23	1
auto[3355443200:3489660927]	109	1			T17	1		T85	1		T100	1
auto[3489660928:3623878655]	121	1			T6	1		T15	1		T17	1
auto[3623878656:3758096383]	87	1			T5	1		T38	1		T207	1
auto[3758096384:3892314111]	107	1			T3	1		T15	1		T16	1
auto[3892314112:4026531839]	92	1			T3	1		T16	1		T37	1
auto[4026531840:4160749567]	95	1			T16	1		T21	1		T100	1
auto[4160749568:4294967295]	94	1			T23	1		T51	1		T218	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	41	1			T1	2		T32	1		T40	1
auto[0:134217727]	auto[1]	43	1			T190	1		T47	1		T50	1
auto[134217728:268435455]	auto[0]	42	1			T116	1		T76	1		T110	1
auto[134217728:268435455]	auto[1]	56	1			T15	1		T40	3		T56	1
auto[268435456:402653183]	auto[0]	48	1			T1	1		T189	1		T51	1
auto[268435456:402653183]	auto[1]	56	1			T37	1		T52	1		T104	1
auto[402653184:536870911]	auto[0]	60	1			T46	1		T40	1		T201	1
auto[402653184:536870911]	auto[1]	51	1			T1	1		T85	1		T135	1
auto[536870912:671088639]	auto[0]	61	1			T2	1		T17	1		T196	1
auto[536870912:671088639]	auto[1]	50	1			T190	1		T55	1		T40	1
auto[671088640:805306367]	auto[0]	50	1			T40	2		T224	2		T109	1
auto[671088640:805306367]	auto[1]	55	1			T38	1		T218	1		T193	2
auto[805306368:939524095]	auto[0]	54	1			T38	1		T196	1		T190	1
auto[805306368:939524095]	auto[1]	48	1			T2	1		T51	1		T40	3
auto[939524096:1073741823]	auto[0]	62	1			T192	1		T40	1		T88	1
auto[939524096:1073741823]	auto[1]	58	1			T40	1		T56	2		T204	2
auto[1073741824:1207959551]	auto[0]	64	1			T15	1		T17	1		T21	1
auto[1073741824:1207959551]	auto[1]	56	1			T218	1		T40	2		T77	1
auto[1207959552:1342177279]	auto[0]	42	1			T39	1		T50	1		T63	1
auto[1207959552:1342177279]	auto[1]	45	1			T116	1		T218	1		T40	1
auto[1342177280:1476395007]	auto[0]	39	1			T22	1		T56	1		T107	1
auto[1342177280:1476395007]	auto[1]	57	1			T16	1		T192	1		T189	1
auto[1476395008:1610612735]	auto[0]	46	1			T16	1		T37	1		T22	1
auto[1476395008:1610612735]	auto[1]	64	1			T38	1		T116	1		T51	1
auto[1610612736:1744830463]	auto[0]	52	1			T196	1		T32	1		T77	1
auto[1610612736:1744830463]	auto[1]	50	1			T37	1		T100	1		T56	1
auto[1744830464:1879048191]	auto[0]	52	1			T21	1		T192	1		T32	1
auto[1744830464:1879048191]	auto[1]	47	1			T196	1		T40	1		T63	1
auto[1879048192:2013265919]	auto[0]	55	1			T51	1		T191	1		T7	1
auto[1879048192:2013265919]	auto[1]	48	1			T40	1		T41	1		T52	1
auto[2013265920:2147483647]	auto[0]	47	1			T1	1		T16	1		T38	2
auto[2013265920:2147483647]	auto[1]	61	1			T6	1		T38	1		T40	2
auto[2147483648:2281701375]	auto[0]	38	1			T55	1		T48	1		T40	1
auto[2147483648:2281701375]	auto[1]	48	1			T16	1		T40	2		T77	1
auto[2281701376:2415919103]	auto[0]	49	1			T38	1		T51	1		T56	2
auto[2281701376:2415919103]	auto[1]	63	1			T23	1		T192	1		T210	1
auto[2415919104:2550136831]	auto[0]	38	1			T16	1		T40	1		T49	1
auto[2415919104:2550136831]	auto[1]	51	1			T3	1		T5	1		T76	1
auto[2550136832:2684354559]	auto[0]	46	1			T77	1		T224	1		T63	1
auto[2550136832:2684354559]	auto[1]	44	1			T40	2		T135	1		T268	1
auto[2684354560:2818572287]	auto[0]	57	1			T17	2		T39	1		T21	1
auto[2684354560:2818572287]	auto[1]	60	1			T5	1		T22	1		T46	1
auto[2818572288:2952790015]	auto[0]	51	1			T21	1		T40	1		T56	1
auto[2818572288:2952790015]	auto[1]	58	1			T2	1		T15	1		T7	1
auto[2952790016:3087007743]	auto[0]	55	1			T41	1		T49	1		T201	1
auto[2952790016:3087007743]	auto[1]	47	1			T85	1		T189	1		T218	1
auto[3087007744:3221225471]	auto[0]	56	1			T17	1		T21	1		T51	1
auto[3087007744:3221225471]	auto[1]	49	1			T85	1		T67	1		T191	1
auto[3221225472:3355443199]	auto[0]	44	1			T17	1		T100	1		T7	1
auto[3221225472:3355443199]	auto[1]	60	1			T16	1		T23	1		T40	1
auto[3355443200:3489660927]	auto[0]	48	1			T17	1		T100	1		T22	1
auto[3355443200:3489660927]	auto[1]	61	1			T85	1		T55	1		T40	3
auto[3489660928:3623878655]	auto[0]	53	1			T6	1		T15	1		T17	1
auto[3489660928:3623878655]	auto[1]	68	1			T23	1		T85	1		T193	1
auto[3623878656:3758096383]	auto[0]	45	1			T38	1		T201	1		T63	1
auto[3623878656:3758096383]	auto[1]	42	1			T5	1		T207	1		T47	1
auto[3758096384:3892314111]	auto[0]	56	1			T16	1		T21	1		T22	1
auto[3758096384:3892314111]	auto[1]	51	1			T3	1		T15	1		T210	1
auto[3892314112:4026531839]	auto[0]	50	1			T3	1		T16	1		T40	2
auto[3892314112:4026531839]	auto[1]	42	1			T37	1		T40	1		T56	1
auto[4026531840:4160749567]	auto[0]	43	1			T100	1		T22	1		T40	2
auto[4026531840:4160749567]	auto[1]	52	1			T16	1		T21	1		T40	1
auto[4160749568:4294967295]	auto[0]	45	1			T51	1		T40	1		T77	1
auto[4160749568:4294967295]	auto[1]	49	1			T23	1		T218	1		T50	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1575

1

T1

4

T2

1

T3

1

auto[1]

1704

1

T1

1

T2

2

T3

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T15	1		T16	1		T17	1
auto[134217728:268435455]	95	1			T2	1		T32	1		T55	1
auto[268435456:402653183]	92	1			T17	1		T192	1		T22	1
auto[402653184:536870911]	120	1			T17	1		T37	1		T85	2
auto[536870912:671088639]	98	1			T2	1		T5	1		T21	1
auto[671088640:805306367]	91	1			T16	1		T22	1		T55	1
auto[805306368:939524095]	110	1			T15	2		T21	1		T100	1
auto[939524096:1073741823]	100	1			T17	1		T38	1		T85	1
auto[1073741824:1207959551]	101	1			T23	1		T116	1		T51	1
auto[1207959552:1342177279]	88	1			T15	1		T17	1		T7	1
auto[1342177280:1476395007]	114	1			T16	2		T21	1		T210	2
auto[1476395008:1610612735]	122	1			T38	1		T85	1		T190	1
auto[1610612736:1744830463]	105	1			T16	2		T191	1		T7	1
auto[1744830464:1879048191]	101	1			T17	1		T38	1		T192	1
auto[1879048192:2013265919]	97	1			T85	1		T67	1		T40	3
auto[2013265920:2147483647]	110	1			T1	1		T15	1		T16	1
auto[2147483648:2281701375]	108	1			T2	1		T3	1		T38	1
auto[2281701376:2415919103]	118	1			T37	2		T21	1		T51	1
auto[2415919104:2550136831]	109	1			T16	1		T23	1		T39	1
auto[2550136832:2684354559]	107	1			T1	1		T37	1		T189	1
auto[2684354560:2818572287]	86	1			T196	1		T22	1		T40	1
auto[2818572288:2952790015]	100	1			T192	1		T100	1		T7	1
auto[2952790016:3087007743]	109	1			T3	1		T7	2		T218	1
auto[3087007744:3221225471]	127	1			T23	1		T32	1		T116	1
auto[3221225472:3355443199]	83	1			T1	1		T39	1		T38	1
auto[3355443200:3489660927]	96	1			T1	1		T21	1		T40	4
auto[3489660928:3623878655]	86	1			T192	1		T40	2		T56	1
auto[3623878656:3758096383]	107	1			T1	1		T5	1		T6	1
auto[3758096384:3892314111]	97	1			T23	1		T51	1		T40	1
auto[3892314112:4026531839]	90	1			T6	1		T17	1		T189	1
auto[4026531840:4160749567]	103	1			T5	1		T16	1		T196	1
auto[4160749568:4294967295]	104	1			T3	1		T17	1		T67	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T196	1		T192	1		T40	1
auto[0:134217727]	auto[1]	62	1			T15	1		T16	1		T17	1
auto[134217728:268435455]	auto[0]	42	1			T32	1		T56	1		T77	1
auto[134217728:268435455]	auto[1]	53	1			T2	1		T55	1		T40	3
auto[268435456:402653183]	auto[0]	41	1			T17	1		T22	1		T191	1
auto[268435456:402653183]	auto[1]	51	1			T192	1		T193	1		T40	1
auto[402653184:536870911]	auto[0]	62	1			T17	1		T85	1		T51	1
auto[402653184:536870911]	auto[1]	58	1			T37	1		T85	1		T46	1
auto[536870912:671088639]	auto[0]	53	1			T2	1		T100	1		T56	2
auto[536870912:671088639]	auto[1]	45	1			T5	1		T21	1		T85	1
auto[671088640:805306367]	auto[0]	42	1			T22	1		T55	1		T40	1
auto[671088640:805306367]	auto[1]	49	1			T16	1		T40	1		T63	1
auto[805306368:939524095]	auto[0]	53	1			T15	1		T21	1		T100	1
auto[805306368:939524095]	auto[1]	57	1			T15	1		T218	1		T40	3
auto[939524096:1073741823]	auto[0]	55	1			T17	1		T38	1		T40	1
auto[939524096:1073741823]	auto[1]	45	1			T85	1		T116	1		T218	1
auto[1073741824:1207959551]	auto[0]	47	1			T116	1		T51	1		T52	1
auto[1073741824:1207959551]	auto[1]	54	1			T23	1		T40	2		T404	1
auto[1207959552:1342177279]	auto[0]	44	1			T17	1		T7	1		T40	1
auto[1207959552:1342177279]	auto[1]	44	1			T15	1		T40	2		T76	1
auto[1342177280:1476395007]	auto[0]	57	1			T16	2		T21	1		T210	1
auto[1342177280:1476395007]	auto[1]	57	1			T210	1		T55	1		T40	1
auto[1476395008:1610612735]	auto[0]	68	1			T38	1		T190	1		T40	1
auto[1476395008:1610612735]	auto[1]	54	1			T85	1		T40	2		T56	1
auto[1610612736:1744830463]	auto[0]	58	1			T7	1		T76	1		T47	1
auto[1610612736:1744830463]	auto[1]	47	1			T16	2		T191	1		T40	1
auto[1744830464:1879048191]	auto[0]	44	1			T17	1		T189	1		T51	1
auto[1744830464:1879048191]	auto[1]	57	1			T38	1		T192	1		T100	1
auto[1879048192:2013265919]	auto[0]	41	1			T224	1		T24	1		T109	1
auto[1879048192:2013265919]	auto[1]	56	1			T85	1		T67	1		T40	3
auto[2013265920:2147483647]	auto[0]	48	1			T1	1		T15	1		T16	1
auto[2013265920:2147483647]	auto[1]	62	1			T38	1		T56	1		T88	1
auto[2147483648:2281701375]	auto[0]	52	1			T38	1		T196	1		T32	1
auto[2147483648:2281701375]	auto[1]	56	1			T2	1		T3	1		T189	1
auto[2281701376:2415919103]	auto[0]	50	1			T37	1		T21	1		T22	1
auto[2281701376:2415919103]	auto[1]	68	1			T37	1		T51	1		T218	1
auto[2415919104:2550136831]	auto[0]	56	1			T39	1		T38	1		T21	1
auto[2415919104:2550136831]	auto[1]	53	1			T16	1		T23	1		T51	1
auto[2550136832:2684354559]	auto[0]	54	1			T1	1		T189	1		T40	1
auto[2550136832:2684354559]	auto[1]	53	1			T37	1		T63	2		T135	3
auto[2684354560:2818572287]	auto[0]	37	1			T196	1		T22	1		T47	1
auto[2684354560:2818572287]	auto[1]	49	1			T40	1		T56	2		T88	1
auto[2818572288:2952790015]	auto[0]	45	1			T100	1		T7	1		T56	1
auto[2818572288:2952790015]	auto[1]	55	1			T192	1		T109	1		T63	1
auto[2952790016:3087007743]	auto[0]	49	1			T7	1		T48	1		T56	1
auto[2952790016:3087007743]	auto[1]	60	1			T3	1		T7	1		T218	1
auto[3087007744:3221225471]	auto[0]	58	1			T23	1		T51	1		T22	1
auto[3087007744:3221225471]	auto[1]	69	1			T32	1		T116	1		T218	1
auto[3221225472:3355443199]	auto[0]	43	1			T1	1		T39	1		T40	2
auto[3221225472:3355443199]	auto[1]	40	1			T38	1		T218	1		T40	2
auto[3355443200:3489660927]	auto[0]	48	1			T1	1		T21	1		T40	1
auto[3355443200:3489660927]	auto[1]	48	1			T40	3		T110	1		T201	1
auto[3489660928:3623878655]	auto[0]	33	1			T192	1		T40	1		T47	1
auto[3489660928:3623878655]	auto[1]	53	1			T40	1		T56	1		T63	1
auto[3623878656:3758096383]	auto[0]	50	1			T38	1		T88	1		T50	1
auto[3623878656:3758096383]	auto[1]	57	1			T1	1		T5	1		T6	1
auto[3758096384:3892314111]	auto[0]	55	1			T51	1		T40	1		T77	1
auto[3758096384:3892314111]	auto[1]	42	1			T23	1		T41	1		T80	1
auto[3892314112:4026531839]	auto[0]	38	1			T6	1		T17	1		T40	1
auto[3892314112:4026531839]	auto[1]	52	1			T189	1		T22	1		T40	5
auto[4026531840:4160749567]	auto[0]	54	1			T16	1		T196	1		T51	1
auto[4026531840:4160749567]	auto[1]	49	1			T5	1		T193	1		T80	1
auto[4160749568:4294967295]	auto[0]	55	1			T3	1		T17	1		T40	1
auto[4160749568:4294967295]	auto[1]	49	1			T67	1		T208	1		T47	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1602

1

T1

4

T3

2

T6

1

auto[1]

1677

1

T1

1

T2

3

T3

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T15	1		T16	1		T17	1
auto[134217728:268435455]	80	1			T189	1		T22	1		T191	1
auto[268435456:402653183]	118	1			T16	2		T23	1		T55	1
auto[402653184:536870911]	110	1			T3	1		T16	1		T210	1
auto[536870912:671088639]	102	1			T5	1		T38	1		T51	1
auto[671088640:805306367]	106	1			T23	1		T38	2		T21	1
auto[805306368:939524095]	112	1			T1	1		T5	1		T16	1
auto[939524096:1073741823]	89	1			T3	1		T192	1		T190	1
auto[1073741824:1207959551]	101	1			T2	1		T100	2		T40	2
auto[1207959552:1342177279]	112	1			T17	3		T51	1		T218	1
auto[1342177280:1476395007]	108	1			T15	1		T17	1		T37	2
auto[1476395008:1610612735]	89	1			T6	2		T21	1		T190	1
auto[1610612736:1744830463]	106	1			T16	1		T17	1		T23	1
auto[1744830464:1879048191]	113	1			T3	1		T17	1		T38	2
auto[1879048192:2013265919]	97	1			T1	1		T196	1		T210	1
auto[2013265920:2147483647]	106	1			T1	1		T196	1		T85	1
auto[2147483648:2281701375]	123	1			T1	2		T17	1		T39	1
auto[2281701376:2415919103]	96	1			T38	1		T85	1		T51	1
auto[2415919104:2550136831]	106	1			T15	2		T116	1		T51	1
auto[2550136832:2684354559]	103	1			T2	1		T21	1		T192	1
auto[2684354560:2818572287]	121	1			T85	1		T40	5		T76	1
auto[2818572288:2952790015]	105	1			T189	1		T67	1		T40	2
auto[2952790016:3087007743]	97	1			T67	1		T48	1		T40	2
auto[3087007744:3221225471]	104	1			T23	1		T38	1		T51	1
auto[3221225472:3355443199]	99	1			T39	1		T32	1		T22	1
auto[3355443200:3489660927]	88	1			T2	1		T37	1		T192	1
auto[3489660928:3623878655]	103	1			T16	1		T21	1		T85	1
auto[3623878656:3758096383]	82	1			T16	1		T116	1		T46	1
auto[3758096384:3892314111]	92	1			T38	1		T40	1		T77	2
auto[3892314112:4026531839]	106	1			T5	1		T16	1		T21	1
auto[4026531840:4160749567]	101	1			T21	1		T55	1		T40	3
auto[4160749568:4294967295]	110	1			T15	1		T22	1		T40	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T15	1		T17	1		T21	1
auto[0:134217727]	auto[1]	51	1			T16	1		T218	1		T104	1
auto[134217728:268435455]	auto[0]	46	1			T189	1		T22	1		T191	1
auto[134217728:268435455]	auto[1]	34	1			T40	1		T95	1		T135	1
auto[268435456:402653183]	auto[0]	55	1			T16	1		T224	1		T104	1
auto[268435456:402653183]	auto[1]	63	1			T16	1		T23	1		T55	1
auto[402653184:536870911]	auto[0]	57	1			T3	1		T51	1		T40	2
auto[402653184:536870911]	auto[1]	53	1			T16	1		T210	1		T193	1
auto[536870912:671088639]	auto[0]	53	1			T38	1		T51	1		T40	3
auto[536870912:671088639]	auto[1]	49	1			T5	1		T40	2		T24	1
auto[671088640:805306367]	auto[0]	55	1			T23	1		T38	1		T21	1
auto[671088640:805306367]	auto[1]	51	1			T38	1		T40	1		T77	1
auto[805306368:939524095]	auto[0]	50	1			T16	1		T37	1		T196	1
auto[805306368:939524095]	auto[1]	62	1			T1	1		T5	1		T218	1
auto[939524096:1073741823]	auto[0]	43	1			T7	1		T76	1		T56	1
auto[939524096:1073741823]	auto[1]	46	1			T3	1		T192	1		T190	1
auto[1073741824:1207959551]	auto[0]	46	1			T100	2		T47	1		T50	1
auto[1073741824:1207959551]	auto[1]	55	1			T2	1		T40	2		T41	1
auto[1207959552:1342177279]	auto[0]	49	1			T17	2		T50	1		T257	1
auto[1207959552:1342177279]	auto[1]	63	1			T17	1		T51	1		T218	1
auto[1342177280:1476395007]	auto[0]	49	1			T17	1		T37	1		T32	1
auto[1342177280:1476395007]	auto[1]	59	1			T15	1		T37	1		T192	1
auto[1476395008:1610612735]	auto[0]	50	1			T6	1		T21	1		T190	1
auto[1476395008:1610612735]	auto[1]	39	1			T6	1		T40	1		T63	1
auto[1610612736:1744830463]	auto[0]	52	1			T17	1		T100	1		T40	1
auto[1610612736:1744830463]	auto[1]	54	1			T16	1		T23	1		T85	1
auto[1744830464:1879048191]	auto[0]	51	1			T3	1		T17	1		T38	1
auto[1744830464:1879048191]	auto[1]	62	1			T38	1		T85	1		T46	1
auto[1879048192:2013265919]	auto[0]	57	1			T1	1		T196	1		T210	1
auto[1879048192:2013265919]	auto[1]	40	1			T208	1		T47	1		T267	1
auto[2013265920:2147483647]	auto[0]	57	1			T1	1		T85	1		T192	1
auto[2013265920:2147483647]	auto[1]	49	1			T196	1		T40	2		T56	1
auto[2147483648:2281701375]	auto[0]	62	1			T1	2		T17	1		T39	1
auto[2147483648:2281701375]	auto[1]	61	1			T189	1		T55	1		T7	1
auto[2281701376:2415919103]	auto[0]	47	1			T38	1		T51	1		T22	1
auto[2281701376:2415919103]	auto[1]	49	1			T85	1		T40	2		T76	1
auto[2415919104:2550136831]	auto[0]	49	1			T116	1		T51	1		T22	1
auto[2415919104:2550136831]	auto[1]	57	1			T15	2		T135	1		T242	1
auto[2550136832:2684354559]	auto[0]	57	1			T21	1		T192	1		T100	1
auto[2550136832:2684354559]	auto[1]	46	1			T2	1		T189	1		T47	1
auto[2684354560:2818572287]	auto[0]	56	1			T40	2		T76	1		T224	1
auto[2684354560:2818572287]	auto[1]	65	1			T85	1		T40	3		T63	4
auto[2818572288:2952790015]	auto[0]	51	1			T189	1		T224	1		T257	1
auto[2818572288:2952790015]	auto[1]	54	1			T67	1		T40	2		T56	1
auto[2952790016:3087007743]	auto[0]	47	1			T48	1		T40	1		T107	1
auto[2952790016:3087007743]	auto[1]	50	1			T67	1		T40	1		T56	1
auto[3087007744:3221225471]	auto[0]	45	1			T38	1		T51	1		T7	1
auto[3087007744:3221225471]	auto[1]	59	1			T23	1		T190	1		T193	1
auto[3221225472:3355443199]	auto[0]	41	1			T39	1		T32	1		T22	1
auto[3221225472:3355443199]	auto[1]	58	1			T40	1		T56	1		T47	1
auto[3355443200:3489660927]	auto[0]	44	1			T47	1		T63	2		T291	1
auto[3355443200:3489660927]	auto[1]	44	1			T2	1		T37	1		T192	1
auto[3489660928:3623878655]	auto[0]	54	1			T16	1		T85	1		T40	1
auto[3489660928:3623878655]	auto[1]	49	1			T21	1		T51	1		T40	3
auto[3623878656:3758096383]	auto[0]	39	1			T16	1		T116	1		T77	1
auto[3623878656:3758096383]	auto[1]	43	1			T46	1		T218	1		T40	2
auto[3758096384:3892314111]	auto[0]	48	1			T38	1		T40	1		T77	2
auto[3758096384:3892314111]	auto[1]	44	1			T63	1		T135	1		T223	1
auto[3892314112:4026531839]	auto[0]	49	1			T16	1		T21	1		T196	1
auto[3892314112:4026531839]	auto[1]	57	1			T5	1		T218	1		T193	1
auto[4026531840:4160749567]	auto[0]	49	1			T21	1		T40	1		T56	1
auto[4026531840:4160749567]	auto[1]	52	1			T55	1		T40	2		T56	1
auto[4160749568:4294967295]	auto[0]	51	1			T76	1		T63	1		T316	1
auto[4160749568:4294967295]	auto[1]	59	1			T15	1		T22	1		T40	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1604

1

T1

3

T3

2

T6

1

auto[1]

1675

1

T1

2

T2

3

T3

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T15	1		T17	1		T38	1
auto[134217728:268435455]	105	1			T6	1		T17	1		T38	1
auto[268435456:402653183]	103	1			T17	1		T21	1		T48	1
auto[402653184:536870911]	108	1			T1	1		T192	1		T100	2
auto[536870912:671088639]	72	1			T16	1		T17	1		T40	2
auto[671088640:805306367]	114	1			T5	1		T16	1		T38	1
auto[805306368:939524095]	113	1			T1	1		T5	1		T6	1
auto[939524096:1073741823]	112	1			T16	1		T23	1		T21	1
auto[1073741824:1207959551]	98	1			T1	1		T3	1		T37	1
auto[1207959552:1342177279]	116	1			T15	1		T23	2		T40	2
auto[1342177280:1476395007]	85	1			T1	1		T38	1		T196	1
auto[1476395008:1610612735]	107	1			T3	1		T16	1		T85	2
auto[1610612736:1744830463]	109	1			T16	1		T37	1		T51	1
auto[1744830464:1879048191]	96	1			T15	1		T16	1		T17	1
auto[1879048192:2013265919]	104	1			T38	1		T85	1		T192	1
auto[2013265920:2147483647]	103	1			T17	1		T21	1		T100	1
auto[2147483648:2281701375]	99	1			T17	1		T21	1		T51	1
auto[2281701376:2415919103]	105	1			T23	1		T51	1		T191	1
auto[2415919104:2550136831]	99	1			T15	1		T85	1		T22	1
auto[2550136832:2684354559]	96	1			T16	1		T193	1		T41	1
auto[2684354560:2818572287]	93	1			T196	1		T210	1		T22	1
auto[2818572288:2952790015]	85	1			T16	1		T17	1		T38	1
auto[2952790016:3087007743]	106	1			T1	1		T39	1		T192	1
auto[3087007744:3221225471]	108	1			T37	1		T116	1		T22	1
auto[3221225472:3355443199]	109	1			T5	1		T21	1		T208	1
auto[3355443200:3489660927]	103	1			T21	1		T210	1		T218	1
auto[3489660928:3623878655]	102	1			T2	2		T3	1		T189	3
auto[3623878656:3758096383]	109	1			T32	2		T7	1		T104	1
auto[3758096384:3892314111]	110	1			T2	1		T15	1		T38	1
auto[3892314112:4026531839]	111	1			T39	1		T192	1		T46	1
auto[4026531840:4160749567]	108	1			T191	1		T7	1		T40	3
auto[4160749568:4294967295]	96	1			T16	1		T196	1		T190	1