Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6458

1

T1

2

T2

6

T3

2

auto[1]

305

1

T16

9

T38

4

T116

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2701	1			T1	1		T2	4		T3	1
auto[134217728:268435455]	169	1			T17	1		T192	1		T116	3
auto[268435456:402653183]	164	1			T17	2		T23	1		T39	1
auto[402653184:536870911]	149	1			T2	1		T15	1		T17	1
auto[536870912:671088639]	147	1			T21	1		T85	1		T189	1
auto[671088640:805306367]	135	1			T16	1		T21	1		T192	1
auto[805306368:939524095]	137	1			T5	1		T189	1		T22	2
auto[939524096:1073741823]	114	1			T16	1		T37	1		T38	1
auto[1073741824:1207959551]	142	1			T196	1		T116	1		T191	1
auto[1207959552:1342177279]	140	1			T38	1		T22	1		T55	1
auto[1342177280:1476395007]	127	1			T15	1		T37	1		T22	1
auto[1476395008:1610612735]	140	1			T16	1		T38	1		T196	1
auto[1610612736:1744830463]	128	1			T6	1		T16	1		T17	1
auto[1744830464:1879048191]	131	1			T6	1		T39	1		T85	1
auto[1879048192:2013265919]	139	1			T23	1		T38	1		T85	1
auto[2013265920:2147483647]	138	1			T5	1		T38	1		T85	1
auto[2147483648:2281701375]	125	1			T16	2		T38	2		T190	1
auto[2281701376:2415919103]	136	1			T16	1		T23	1		T37	1
auto[2415919104:2550136831]	113	1			T15	1		T40	1		T56	1
auto[2550136832:2684354559]	116	1			T16	1		T21	2		T85	1
auto[2684354560:2818572287]	128	1			T15	1		T32	1		T51	1
auto[2818572288:2952790015]	124	1			T15	1		T17	1		T38	1
auto[2952790016:3087007743]	126	1			T15	1		T16	1		T17	1
auto[3087007744:3221225471]	137	1			T15	1		T21	1		T192	1
auto[3221225472:3355443199]	117	1			T1	1		T2	1		T16	2
auto[3355443200:3489660927]	132	1			T15	1		T17	1		T21	1
auto[3489660928:3623878655]	108	1			T15	1		T16	2		T17	1
auto[3623878656:3758096383]	104	1			T15	1		T191	1		T40	1
auto[3758096384:3892314111]	124	1			T3	1		T6	1		T15	1
auto[3892314112:4026531839]	123	1			T16	1		T100	2		T191	1
auto[4026531840:4160749567]	121	1			T32	1		T116	2		T40	2
auto[4160749568:4294967295]	128	1			T5	1		T15	1		T16	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2691	1			T1	1		T2	4		T3	1
auto[0:134217727]	auto[1]	10	1			T110	1		T356	1		T369	1
auto[134217728:268435455]	auto[0]	157	1			T17	1		T192	1		T116	1
auto[134217728:268435455]	auto[1]	12	1			T116	2		T387	1		T402	1
auto[268435456:402653183]	auto[0]	155	1			T17	2		T23	1		T39	1
auto[268435456:402653183]	auto[1]	9	1			T291	1		T281	1		T366	1
auto[402653184:536870911]	auto[0]	138	1			T2	1		T15	1		T17	1
auto[402653184:536870911]	auto[1]	11	1			T116	1		T110	1		T291	1
auto[536870912:671088639]	auto[0]	137	1			T21	1		T85	1		T189	1
auto[536870912:671088639]	auto[1]	10	1			T116	1		T291	1		T366	1
auto[671088640:805306367]	auto[0]	128	1			T16	1		T21	1		T192	1
auto[671088640:805306367]	auto[1]	7	1			T110	1		T303	1		T405	1
auto[805306368:939524095]	auto[0]	124	1			T5	1		T189	1		T22	2
auto[805306368:939524095]	auto[1]	13	1			T110	1		T366	1		T356	2
auto[939524096:1073741823]	auto[0]	104	1			T37	1		T38	1		T21	1
auto[939524096:1073741823]	auto[1]	10	1			T16	1		T108	1		T356	1
auto[1073741824:1207959551]	auto[0]	139	1			T196	1		T116	1		T191	1
auto[1073741824:1207959551]	auto[1]	3	1			T244	1		T406	1		T407	1
auto[1207959552:1342177279]	auto[0]	130	1			T38	1		T22	1		T55	1
auto[1207959552:1342177279]	auto[1]	10	1			T110	1		T201	1		T238	1
auto[1342177280:1476395007]	auto[0]	118	1			T15	1		T37	1		T22	1
auto[1342177280:1476395007]	auto[1]	9	1			T291	1		T356	1		T402	1
auto[1476395008:1610612735]	auto[0]	136	1			T38	1		T196	1		T192	1
auto[1476395008:1610612735]	auto[1]	4	1			T16	1		T244	1		T405	1
auto[1610612736:1744830463]	auto[0]	118	1			T6	1		T16	1		T17	1
auto[1610612736:1744830463]	auto[1]	10	1			T291	1		T256	1		T239	1
auto[1744830464:1879048191]	auto[0]	118	1			T6	1		T39	1		T85	1
auto[1744830464:1879048191]	auto[1]	13	1			T108	1		T291	1		T246	1
auto[1879048192:2013265919]	auto[0]	129	1			T23	1		T85	1		T192	1
auto[1879048192:2013265919]	auto[1]	10	1			T38	1		T108	1		T238	1
auto[2013265920:2147483647]	auto[0]	131	1			T5	1		T85	1		T32	1
auto[2013265920:2147483647]	auto[1]	7	1			T38	1		T291	1		T320	1
auto[2147483648:2281701375]	auto[0]	110	1			T16	2		T38	1		T190	1
auto[2147483648:2281701375]	auto[1]	15	1			T38	1		T110	1		T238	1
auto[2281701376:2415919103]	auto[0]	125	1			T23	1		T37	1		T22	1
auto[2281701376:2415919103]	auto[1]	11	1			T16	1		T356	1		T308	2
auto[2415919104:2550136831]	auto[0]	102	1			T15	1		T40	1		T56	1
auto[2415919104:2550136831]	auto[1]	11	1			T256	1		T408	1		T403	1
auto[2550136832:2684354559]	auto[0]	108	1			T16	1		T21	2		T85	1
auto[2550136832:2684354559]	auto[1]	8	1			T108	1		T366	1		T356	1
auto[2684354560:2818572287]	auto[0]	120	1			T15	1		T32	1		T51	1
auto[2684354560:2818572287]	auto[1]	8	1			T201	1		T366	1		T320	1
auto[2818572288:2952790015]	auto[0]	111	1			T15	1		T17	1		T38	1
auto[2818572288:2952790015]	auto[1]	13	1			T108	1		T244	2		T387	1
auto[2952790016:3087007743]	auto[0]	117	1			T15	1		T17	1		T38	1
auto[2952790016:3087007743]	auto[1]	9	1			T16	1		T281	1		T368	1
auto[3087007744:3221225471]	auto[0]	130	1			T15	1		T21	1		T192	1
auto[3087007744:3221225471]	auto[1]	7	1			T256	1		T303	1		T406	1
auto[3221225472:3355443199]	auto[0]	111	1			T1	1		T2	1		T16	1
auto[3221225472:3355443199]	auto[1]	6	1			T16	1		T356	1		T308	1
auto[3355443200:3489660927]	auto[0]	121	1			T15	1		T17	1		T21	1
auto[3355443200:3489660927]	auto[1]	11	1			T110	1		T366	1		T356	1
auto[3489660928:3623878655]	auto[0]	92	1			T15	1		T16	1		T17	1
auto[3489660928:3623878655]	auto[1]	16	1			T16	1		T291	1		T256	1
auto[3623878656:3758096383]	auto[0]	97	1			T15	1		T191	1		T40	1
auto[3623878656:3758096383]	auto[1]	7	1			T402	1		T405	1		T406	1
auto[3758096384:3892314111]	auto[0]	112	1			T3	1		T6	1		T15	1
auto[3758096384:3892314111]	auto[1]	12	1			T108	1		T201	2		T256	1
auto[3892314112:4026531839]	auto[0]	118	1			T16	1		T100	2		T191	1
auto[3892314112:4026531839]	auto[1]	5	1			T265	1		T239	1		T338	1
auto[4026531840:4160749567]	auto[0]	112	1			T32	1		T40	2		T76	1
auto[4026531840:4160749567]	auto[1]	9	1			T116	2		T108	1		T201	1
auto[4160749568:4294967295]	auto[0]	119	1			T5	1		T15	1		T85	1
auto[4160749568:4294967295]	auto[1]	9	1			T16	3		T38	1		T366	2