Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.84 99.07 97.99 98.67 100.00 99.11 98.41 91.63


Total test records in report: 1065
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T1004 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3963966981 Mar 10 01:05:22 PM PDT 24 Mar 10 01:05:28 PM PDT 24 137800205 ps
T1005 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3528407569 Mar 10 01:05:11 PM PDT 24 Mar 10 01:05:12 PM PDT 24 48137543 ps
T1006 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2337618968 Mar 10 01:04:56 PM PDT 24 Mar 10 01:05:00 PM PDT 24 68274715 ps
T1007 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2143394353 Mar 10 01:05:27 PM PDT 24 Mar 10 01:05:29 PM PDT 24 22539043 ps
T1008 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3339931273 Mar 10 01:05:44 PM PDT 24 Mar 10 01:05:46 PM PDT 24 31162535 ps
T1009 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.4186326770 Mar 10 01:05:08 PM PDT 24 Mar 10 01:05:12 PM PDT 24 1154066929 ps
T1010 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.4228490939 Mar 10 01:05:09 PM PDT 24 Mar 10 01:05:11 PM PDT 24 82076740 ps
T1011 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.468353472 Mar 10 01:05:47 PM PDT 24 Mar 10 01:05:48 PM PDT 24 42916540 ps
T1012 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1775141586 Mar 10 01:05:24 PM PDT 24 Mar 10 01:05:28 PM PDT 24 110364706 ps
T1013 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1919698261 Mar 10 01:05:18 PM PDT 24 Mar 10 01:05:22 PM PDT 24 149134019 ps
T1014 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1741782217 Mar 10 01:05:09 PM PDT 24 Mar 10 01:05:18 PM PDT 24 435293014 ps
T1015 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3576727008 Mar 10 01:05:34 PM PDT 24 Mar 10 01:05:34 PM PDT 24 33431025 ps
T1016 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.823384809 Mar 10 01:05:07 PM PDT 24 Mar 10 01:05:13 PM PDT 24 160684899 ps
T1017 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.133293342 Mar 10 01:05:29 PM PDT 24 Mar 10 01:05:33 PM PDT 24 222896493 ps
T1018 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.374854599 Mar 10 01:05:21 PM PDT 24 Mar 10 01:05:25 PM PDT 24 23519780 ps
T1019 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.80560296 Mar 10 01:05:35 PM PDT 24 Mar 10 01:05:37 PM PDT 24 51743615 ps
T1020 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.404099923 Mar 10 01:04:54 PM PDT 24 Mar 10 01:04:57 PM PDT 24 34574812 ps
T1021 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2650688022 Mar 10 01:05:09 PM PDT 24 Mar 10 01:05:18 PM PDT 24 246165456 ps
T1022 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2817642256 Mar 10 01:05:27 PM PDT 24 Mar 10 01:05:30 PM PDT 24 563180935 ps
T1023 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.104505965 Mar 10 01:05:35 PM PDT 24 Mar 10 01:05:39 PM PDT 24 235367840 ps
T1024 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1550867906 Mar 10 01:05:11 PM PDT 24 Mar 10 01:05:13 PM PDT 24 103077476 ps
T1025 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1212609108 Mar 10 01:05:39 PM PDT 24 Mar 10 01:05:41 PM PDT 24 19284698 ps
T1026 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.4192648515 Mar 10 01:05:35 PM PDT 24 Mar 10 01:05:35 PM PDT 24 42067303 ps
T1027 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1713601066 Mar 10 01:05:13 PM PDT 24 Mar 10 01:05:14 PM PDT 24 69982461 ps
T1028 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.713911349 Mar 10 01:04:56 PM PDT 24 Mar 10 01:04:57 PM PDT 24 27813646 ps
T1029 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2632272575 Mar 10 01:05:19 PM PDT 24 Mar 10 01:05:21 PM PDT 24 52226592 ps
T1030 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1360614648 Mar 10 01:05:08 PM PDT 24 Mar 10 01:05:13 PM PDT 24 158327379 ps
T1031 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.4043213568 Mar 10 01:05:20 PM PDT 24 Mar 10 01:05:22 PM PDT 24 30903043 ps
T1032 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2123799280 Mar 10 01:05:20 PM PDT 24 Mar 10 01:05:24 PM PDT 24 84845171 ps
T1033 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1930627517 Mar 10 01:05:24 PM PDT 24 Mar 10 01:05:27 PM PDT 24 47452106 ps
T1034 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1955575878 Mar 10 01:05:01 PM PDT 24 Mar 10 01:05:06 PM PDT 24 96815771 ps
T1035 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1533844201 Mar 10 01:04:57 PM PDT 24 Mar 10 01:04:58 PM PDT 24 23140594 ps
T1036 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3058106209 Mar 10 01:05:34 PM PDT 24 Mar 10 01:05:35 PM PDT 24 20846776 ps
T1037 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3427869411 Mar 10 01:05:47 PM PDT 24 Mar 10 01:05:48 PM PDT 24 13954101 ps
T1038 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3341869082 Mar 10 01:05:09 PM PDT 24 Mar 10 01:05:12 PM PDT 24 66073741 ps
T1039 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2484240129 Mar 10 01:05:22 PM PDT 24 Mar 10 01:05:26 PM PDT 24 57349778 ps
T1040 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.445120850 Mar 10 01:05:07 PM PDT 24 Mar 10 01:05:42 PM PDT 24 1050909388 ps
T1041 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1117248059 Mar 10 01:05:12 PM PDT 24 Mar 10 01:05:18 PM PDT 24 201808614 ps
T161 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.416969346 Mar 10 01:05:28 PM PDT 24 Mar 10 01:05:39 PM PDT 24 1023551191 ps
T1042 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2867189885 Mar 10 01:05:03 PM PDT 24 Mar 10 01:05:23 PM PDT 24 2040470067 ps
T1043 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2221737736 Mar 10 01:04:56 PM PDT 24 Mar 10 01:05:09 PM PDT 24 2871526646 ps
T1044 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3042371009 Mar 10 01:05:09 PM PDT 24 Mar 10 01:05:12 PM PDT 24 143857544 ps
T1045 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3393587339 Mar 10 01:05:22 PM PDT 24 Mar 10 01:05:28 PM PDT 24 628822974 ps
T1046 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1942541775 Mar 10 01:05:03 PM PDT 24 Mar 10 01:05:06 PM PDT 24 424137478 ps
T1047 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1128777219 Mar 10 01:05:01 PM PDT 24 Mar 10 01:05:07 PM PDT 24 1677352052 ps
T1048 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.623053462 Mar 10 01:05:44 PM PDT 24 Mar 10 01:05:46 PM PDT 24 25957811 ps
T155 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.695951892 Mar 10 01:05:02 PM PDT 24 Mar 10 01:05:10 PM PDT 24 112435799 ps
T1049 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2440782134 Mar 10 01:05:08 PM PDT 24 Mar 10 01:05:10 PM PDT 24 42170352 ps
T1050 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2818584351 Mar 10 01:05:29 PM PDT 24 Mar 10 01:05:30 PM PDT 24 12944480 ps
T1051 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2404962511 Mar 10 01:05:27 PM PDT 24 Mar 10 01:05:31 PM PDT 24 385890214 ps
T150 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3745073277 Mar 10 01:05:31 PM PDT 24 Mar 10 01:05:40 PM PDT 24 289575305 ps
T1052 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1545962825 Mar 10 01:05:12 PM PDT 24 Mar 10 01:05:14 PM PDT 24 20716127 ps
T1053 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3728339364 Mar 10 01:05:21 PM PDT 24 Mar 10 01:05:25 PM PDT 24 50231131 ps
T1054 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3266352089 Mar 10 01:05:37 PM PDT 24 Mar 10 01:05:41 PM PDT 24 109930598 ps
T1055 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.4116928850 Mar 10 01:05:34 PM PDT 24 Mar 10 01:05:35 PM PDT 24 30928983 ps
T1056 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1147586372 Mar 10 01:05:10 PM PDT 24 Mar 10 01:05:15 PM PDT 24 455147330 ps
T1057 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.939280210 Mar 10 01:05:09 PM PDT 24 Mar 10 01:05:12 PM PDT 24 55054419 ps
T1058 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1414392741 Mar 10 01:05:30 PM PDT 24 Mar 10 01:05:34 PM PDT 24 316253618 ps
T1059 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3296139527 Mar 10 01:05:22 PM PDT 24 Mar 10 01:05:29 PM PDT 24 74733061 ps
T1060 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3496792280 Mar 10 01:05:32 PM PDT 24 Mar 10 01:05:34 PM PDT 24 24942114 ps
T1061 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2624376582 Mar 10 01:05:30 PM PDT 24 Mar 10 01:05:33 PM PDT 24 60604590 ps
T1062 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3992843627 Mar 10 01:04:57 PM PDT 24 Mar 10 01:05:02 PM PDT 24 169393595 ps
T1063 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1506648657 Mar 10 01:05:38 PM PDT 24 Mar 10 01:05:41 PM PDT 24 26290151 ps
T1064 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3345473337 Mar 10 01:05:15 PM PDT 24 Mar 10 01:05:16 PM PDT 24 23578481 ps
T1065 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1145776327 Mar 10 01:05:46 PM PDT 24 Mar 10 01:05:47 PM PDT 24 42015852 ps

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2512450503
Short name T17
Test name
Test status
Simulation time 164945789 ps
CPU time 5.46 seconds
Started Mar 10 02:45:19 PM PDT 24
Finished Mar 10 02:45:25 PM PDT 24
Peak memory 214548 kb
Host smart-af7915b1-6337-4c34-963d-018053bd77ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512450503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2512450503
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1379803585
Short name T40
Test name
Test status
Simulation time 1137713783 ps
CPU time 40.5 seconds
Started Mar 10 02:45:32 PM PDT 24
Finished Mar 10 02:46:13 PM PDT 24
Peak memory 215992 kb
Host smart-04ed403a-d1c4-419c-a1d8-6b2c2f784a65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379803585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1379803585
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2325665916
Short name T16
Test name
Test status
Simulation time 132136775 ps
CPU time 4.91 seconds
Started Mar 10 02:42:08 PM PDT 24
Finished Mar 10 02:42:13 PM PDT 24
Peak memory 215784 kb
Host smart-9b6eceac-2ba6-40e0-969b-d7a2c27a8461
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2325665916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2325665916
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.2923234906
Short name T56
Test name
Test status
Simulation time 4421914080 ps
CPU time 26.84 seconds
Started Mar 10 02:45:19 PM PDT 24
Finished Mar 10 02:45:46 PM PDT 24
Peak memory 222748 kb
Host smart-be8c76bf-f4b1-4ede-a7dd-51c9d13adde5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923234906 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.2923234906
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.4157986178
Short name T11
Test name
Test status
Simulation time 303990666 ps
CPU time 10.68 seconds
Started Mar 10 02:41:52 PM PDT 24
Finished Mar 10 02:42:03 PM PDT 24
Peak memory 229652 kb
Host smart-89588ad9-b5c1-40c4-b932-256d23b1687e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157986178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.4157986178
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2529678049
Short name T50
Test name
Test status
Simulation time 430155153 ps
CPU time 18.55 seconds
Started Mar 10 02:43:04 PM PDT 24
Finished Mar 10 02:43:23 PM PDT 24
Peak memory 216408 kb
Host smart-c953f9b8-5953-4e8f-9ff6-b694f0c9ede2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529678049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2529678049
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.854526830
Short name T45
Test name
Test status
Simulation time 1105026834 ps
CPU time 40.02 seconds
Started Mar 10 02:43:55 PM PDT 24
Finished Mar 10 02:44:35 PM PDT 24
Peak memory 220292 kb
Host smart-a31714a2-0a12-4124-a187-b6dc15ae9d2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854526830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.854526830
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3715091788
Short name T8
Test name
Test status
Simulation time 177346285 ps
CPU time 3.13 seconds
Started Mar 10 02:44:06 PM PDT 24
Finished Mar 10 02:44:10 PM PDT 24
Peak memory 214792 kb
Host smart-7e462335-7828-474b-85ab-8f7d90f0193b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715091788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3715091788
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2297076325
Short name T38
Test name
Test status
Simulation time 128544854 ps
CPU time 4.71 seconds
Started Mar 10 02:43:57 PM PDT 24
Finished Mar 10 02:44:02 PM PDT 24
Peak memory 214992 kb
Host smart-8571b782-1ec2-4518-ad7c-8213202c33cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2297076325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2297076325
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2339316938
Short name T114
Test name
Test status
Simulation time 168865399 ps
CPU time 6.29 seconds
Started Mar 10 01:05:34 PM PDT 24
Finished Mar 10 01:05:41 PM PDT 24
Peak memory 214480 kb
Host smart-357f0d39-97c5-49d3-8182-b77f88840091
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339316938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2339316938
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.540701744
Short name T291
Test name
Test status
Simulation time 193427737 ps
CPU time 9.96 seconds
Started Mar 10 02:45:17 PM PDT 24
Finished Mar 10 02:45:27 PM PDT 24
Peak memory 214732 kb
Host smart-6f90d7a0-a2d5-43cd-9448-999186ee328e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=540701744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.540701744
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.4278554781
Short name T63
Test name
Test status
Simulation time 2365076134 ps
CPU time 45.9 seconds
Started Mar 10 02:45:50 PM PDT 24
Finished Mar 10 02:46:36 PM PDT 24
Peak memory 216972 kb
Host smart-abe072a9-83f3-4f6a-94d5-02811fb8aa4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278554781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.4278554781
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1369643432
Short name T77
Test name
Test status
Simulation time 1151232658 ps
CPU time 8.3 seconds
Started Mar 10 02:42:49 PM PDT 24
Finished Mar 10 02:42:57 PM PDT 24
Peak memory 214384 kb
Host smart-5d56b123-a645-4eae-b226-f9f663cf4844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369643432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1369643432
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2213196062
Short name T413
Test name
Test status
Simulation time 631221168 ps
CPU time 16.98 seconds
Started Mar 10 02:43:08 PM PDT 24
Finished Mar 10 02:43:25 PM PDT 24
Peak memory 215008 kb
Host smart-ed91dc1b-8399-48c0-827c-e28439af7c7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2213196062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2213196062
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3984134900
Short name T61
Test name
Test status
Simulation time 624987937 ps
CPU time 19.92 seconds
Started Mar 10 02:44:10 PM PDT 24
Finished Mar 10 02:44:31 PM PDT 24
Peak memory 222836 kb
Host smart-bae96eee-6a85-4047-a1b4-1d2f5afa0dd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984134900 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3984134900
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1950161222
Short name T116
Test name
Test status
Simulation time 97995274 ps
CPU time 5.46 seconds
Started Mar 10 02:44:53 PM PDT 24
Finished Mar 10 02:44:59 PM PDT 24
Peak memory 222596 kb
Host smart-0a5391c5-9e60-477f-9f79-66ed1cb34605
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1950161222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1950161222
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1828369733
Short name T356
Test name
Test status
Simulation time 149401258 ps
CPU time 8.65 seconds
Started Mar 10 02:45:57 PM PDT 24
Finished Mar 10 02:46:06 PM PDT 24
Peak memory 215092 kb
Host smart-365bdf78-7ccb-4c35-bf5b-243a868a7d32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1828369733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1828369733
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.238699469
Short name T145
Test name
Test status
Simulation time 102337546 ps
CPU time 5.54 seconds
Started Mar 10 01:05:29 PM PDT 24
Finished Mar 10 01:05:35 PM PDT 24
Peak memory 208876 kb
Host smart-deddc8b5-45bb-4273-b573-af9684ae6075
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238699469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.238699469
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3104618756
Short name T268
Test name
Test status
Simulation time 2195598656 ps
CPU time 73.09 seconds
Started Mar 10 02:44:17 PM PDT 24
Finished Mar 10 02:45:30 PM PDT 24
Peak memory 216724 kb
Host smart-d9c8ab4e-bbbe-489f-a175-7c977cca1e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104618756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3104618756
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.20559943
Short name T407
Test name
Test status
Simulation time 454341797 ps
CPU time 12.54 seconds
Started Mar 10 02:42:38 PM PDT 24
Finished Mar 10 02:42:50 PM PDT 24
Peak memory 214448 kb
Host smart-fdec9d22-e811-40e5-9518-03be99198d47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20559943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.20559943
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3715398306
Short name T122
Test name
Test status
Simulation time 1793683370 ps
CPU time 9.07 seconds
Started Mar 10 01:05:19 PM PDT 24
Finished Mar 10 01:05:28 PM PDT 24
Peak memory 214392 kb
Host smart-5543618d-7f01-46f7-b4d9-07eaae110788
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715398306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3715398306
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2654667421
Short name T72
Test name
Test status
Simulation time 1604946167 ps
CPU time 60.32 seconds
Started Mar 10 02:45:38 PM PDT 24
Finished Mar 10 02:46:38 PM PDT 24
Peak memory 220140 kb
Host smart-cb159c89-7de2-483c-8874-9b7c211868e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654667421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2654667421
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3515124373
Short name T35
Test name
Test status
Simulation time 3791610240 ps
CPU time 7.05 seconds
Started Mar 10 02:43:54 PM PDT 24
Finished Mar 10 02:44:02 PM PDT 24
Peak memory 221828 kb
Host smart-3bd11c72-095c-4f28-9728-b708f14fe430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515124373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3515124373
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1731665241
Short name T48
Test name
Test status
Simulation time 99153549 ps
CPU time 4.44 seconds
Started Mar 10 02:45:22 PM PDT 24
Finished Mar 10 02:45:26 PM PDT 24
Peak memory 218532 kb
Host smart-2c89dbec-95e9-46ab-ab6b-a101ef686b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731665241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1731665241
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.651030647
Short name T403
Test name
Test status
Simulation time 602284981 ps
CPU time 9.19 seconds
Started Mar 10 02:44:19 PM PDT 24
Finished Mar 10 02:44:28 PM PDT 24
Peak memory 214508 kb
Host smart-5cee6290-7eac-424c-8d62-bcc98aa28d6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=651030647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.651030647
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3028305814
Short name T29
Test name
Test status
Simulation time 90045071 ps
CPU time 3.9 seconds
Started Mar 10 02:45:49 PM PDT 24
Finished Mar 10 02:45:53 PM PDT 24
Peak memory 209752 kb
Host smart-a442d5e3-2523-4c4e-b28b-d4f92b6e9e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028305814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3028305814
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2898216770
Short name T85
Test name
Test status
Simulation time 196654328 ps
CPU time 5.11 seconds
Started Mar 10 02:45:08 PM PDT 24
Finished Mar 10 02:45:13 PM PDT 24
Peak memory 209548 kb
Host smart-e42ddaf6-2f2b-44d4-acf1-68c81054b74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898216770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2898216770
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.4262775132
Short name T205
Test name
Test status
Simulation time 330577484 ps
CPU time 7.37 seconds
Started Mar 10 02:42:40 PM PDT 24
Finished Mar 10 02:42:48 PM PDT 24
Peak memory 222564 kb
Host smart-e8074451-fc2d-49e4-bfe7-0cfb0d553da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262775132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.4262775132
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3760071131
Short name T91
Test name
Test status
Simulation time 88181554 ps
CPU time 4.21 seconds
Started Mar 10 02:43:39 PM PDT 24
Finished Mar 10 02:43:43 PM PDT 24
Peak memory 208872 kb
Host smart-9ba64f5e-915a-4408-86da-eaea0591510e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760071131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3760071131
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3750156607
Short name T873
Test name
Test status
Simulation time 1096160022 ps
CPU time 14.81 seconds
Started Mar 10 02:44:39 PM PDT 24
Finished Mar 10 02:44:54 PM PDT 24
Peak memory 215160 kb
Host smart-d651b728-dc81-45e3-932f-aaee2de0410d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3750156607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3750156607
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3778513998
Short name T47
Test name
Test status
Simulation time 1930079024 ps
CPU time 46.9 seconds
Started Mar 10 02:46:07 PM PDT 24
Finished Mar 10 02:46:54 PM PDT 24
Peak memory 215144 kb
Host smart-a6350862-898b-4d74-a92e-634efba00826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778513998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3778513998
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.4038604472
Short name T108
Test name
Test status
Simulation time 1720645963 ps
CPU time 89.48 seconds
Started Mar 10 02:44:50 PM PDT 24
Finished Mar 10 02:46:20 PM PDT 24
Peak memory 219348 kb
Host smart-3217dd24-5b61-487c-9916-0f642b102287
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4038604472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.4038604472
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2397356830
Short name T57
Test name
Test status
Simulation time 225503603 ps
CPU time 2.72 seconds
Started Mar 10 02:41:53 PM PDT 24
Finished Mar 10 02:41:56 PM PDT 24
Peak memory 210044 kb
Host smart-e6ec6da2-09e3-44d6-a6d9-1ad4e3fac732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397356830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2397356830
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1527218320
Short name T95
Test name
Test status
Simulation time 17692717512 ps
CPU time 45.35 seconds
Started Mar 10 02:42:57 PM PDT 24
Finished Mar 10 02:43:43 PM PDT 24
Peak memory 222724 kb
Host smart-74d02f53-d01f-4feb-b120-26de0ed64cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527218320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1527218320
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1232187556
Short name T97
Test name
Test status
Simulation time 45084449 ps
CPU time 0.72 seconds
Started Mar 10 02:43:18 PM PDT 24
Finished Mar 10 02:43:19 PM PDT 24
Peak memory 206076 kb
Host smart-ba2ebd52-c7b3-4c6a-95df-9913583b4310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232187556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1232187556
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3794298837
Short name T84
Test name
Test status
Simulation time 746381541 ps
CPU time 11.03 seconds
Started Mar 10 02:43:22 PM PDT 24
Finished Mar 10 02:43:33 PM PDT 24
Peak memory 208644 kb
Host smart-347c1ee3-7433-41e7-9584-301da6cf4f54
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794298837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3794298837
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.190039888
Short name T221
Test name
Test status
Simulation time 854581734 ps
CPU time 44.65 seconds
Started Mar 10 02:43:06 PM PDT 24
Finished Mar 10 02:43:51 PM PDT 24
Peak memory 215624 kb
Host smart-d6898b63-54bd-40fb-912e-eb0690eeb3fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190039888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.190039888
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.4133833279
Short name T310
Test name
Test status
Simulation time 1602943258 ps
CPU time 22.58 seconds
Started Mar 10 02:45:54 PM PDT 24
Finished Mar 10 02:46:17 PM PDT 24
Peak memory 220348 kb
Host smart-60c03054-be57-4da6-904b-7f180e17a110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133833279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.4133833279
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3571947599
Short name T849
Test name
Test status
Simulation time 128269799 ps
CPU time 5.68 seconds
Started Mar 10 02:43:02 PM PDT 24
Finished Mar 10 02:43:08 PM PDT 24
Peak memory 221544 kb
Host smart-06665ee8-99e7-49af-a6ef-ed07d4fdf76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571947599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3571947599
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3562730529
Short name T110
Test name
Test status
Simulation time 126285551 ps
CPU time 3.85 seconds
Started Mar 10 02:44:10 PM PDT 24
Finished Mar 10 02:44:14 PM PDT 24
Peak memory 214480 kb
Host smart-9033f2db-ec7a-4547-b154-602b16178cd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3562730529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3562730529
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.993773006
Short name T293
Test name
Test status
Simulation time 5598993746 ps
CPU time 57.54 seconds
Started Mar 10 02:44:32 PM PDT 24
Finished Mar 10 02:45:31 PM PDT 24
Peak memory 218592 kb
Host smart-8ca6a148-ae26-4703-a365-881a9c957baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993773006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.993773006
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.472595389
Short name T198
Test name
Test status
Simulation time 574010637 ps
CPU time 3.52 seconds
Started Mar 10 02:44:45 PM PDT 24
Finished Mar 10 02:44:48 PM PDT 24
Peak memory 210368 kb
Host smart-35e62fd3-0cfb-4e13-a641-e63c9f6395d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472595389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.472595389
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2822322681
Short name T406
Test name
Test status
Simulation time 2001527923 ps
CPU time 107.48 seconds
Started Mar 10 02:45:46 PM PDT 24
Finished Mar 10 02:47:35 PM PDT 24
Peak memory 215108 kb
Host smart-9b8e4827-23d4-4abc-9b4f-f563ddeefaa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2822322681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2822322681
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.523138515
Short name T25
Test name
Test status
Simulation time 316130685 ps
CPU time 6.59 seconds
Started Mar 10 02:44:11 PM PDT 24
Finished Mar 10 02:44:18 PM PDT 24
Peak memory 214772 kb
Host smart-57125075-a7c4-453d-888a-69dabe94c0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523138515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.523138515
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.235042769
Short name T234
Test name
Test status
Simulation time 60633881850 ps
CPU time 398.93 seconds
Started Mar 10 02:43:21 PM PDT 24
Finished Mar 10 02:50:00 PM PDT 24
Peak memory 222768 kb
Host smart-79960547-459c-40d4-8416-52a79bc39510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235042769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.235042769
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2675810577
Short name T316
Test name
Test status
Simulation time 7640330434 ps
CPU time 81.34 seconds
Started Mar 10 02:45:13 PM PDT 24
Finished Mar 10 02:46:34 PM PDT 24
Peak memory 220536 kb
Host smart-9734e5e2-4272-4859-915b-2870c8c1cd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675810577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2675810577
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2256583094
Short name T151
Test name
Test status
Simulation time 122595770 ps
CPU time 6.48 seconds
Started Mar 10 01:05:20 PM PDT 24
Finished Mar 10 01:05:27 PM PDT 24
Peak memory 209104 kb
Host smart-b13df19e-895d-43fe-b457-a69cb670101d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256583094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2256583094
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1395903472
Short name T90
Test name
Test status
Simulation time 191014710 ps
CPU time 3.43 seconds
Started Mar 10 02:44:41 PM PDT 24
Finished Mar 10 02:44:45 PM PDT 24
Peak memory 209576 kb
Host smart-160522b3-575c-4bed-94a2-75ef2ec57535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395903472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1395903472
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3879935835
Short name T170
Test name
Test status
Simulation time 68157467 ps
CPU time 4.02 seconds
Started Mar 10 02:45:32 PM PDT 24
Finished Mar 10 02:45:37 PM PDT 24
Peak memory 217892 kb
Host smart-ed359d51-3911-4b8f-930c-bd7c52e15642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879935835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3879935835
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.4219051379
Short name T172
Test name
Test status
Simulation time 169462321 ps
CPU time 4.9 seconds
Started Mar 10 02:44:51 PM PDT 24
Finished Mar 10 02:44:56 PM PDT 24
Peak memory 222996 kb
Host smart-6115787a-a50b-4712-8a0a-046b5973af2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219051379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.4219051379
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3799078747
Short name T169
Test name
Test status
Simulation time 58218938 ps
CPU time 2.91 seconds
Started Mar 10 02:45:56 PM PDT 24
Finished Mar 10 02:46:00 PM PDT 24
Peak memory 222928 kb
Host smart-feb1c3a6-9f63-4858-95c1-8526aa7fb94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799078747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3799078747
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.42901335
Short name T160
Test name
Test status
Simulation time 103609263 ps
CPU time 3.87 seconds
Started Mar 10 02:45:23 PM PDT 24
Finished Mar 10 02:45:27 PM PDT 24
Peak memory 210148 kb
Host smart-863ae29a-f9d3-4259-b5d6-01e09297635f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42901335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.42901335
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1719975301
Short name T117
Test name
Test status
Simulation time 728563658 ps
CPU time 5.28 seconds
Started Mar 10 01:04:55 PM PDT 24
Finished Mar 10 01:05:01 PM PDT 24
Peak memory 214372 kb
Host smart-7eaa6035-bd31-489c-b7f5-c96d4ad8fecc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719975301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1719975301
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3745073277
Short name T150
Test name
Test status
Simulation time 289575305 ps
CPU time 8.5 seconds
Started Mar 10 01:05:31 PM PDT 24
Finished Mar 10 01:05:40 PM PDT 24
Peak memory 208956 kb
Host smart-a5480fbc-4e34-4120-8122-4f594a8084f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745073277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3745073277
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.695951892
Short name T155
Test name
Test status
Simulation time 112435799 ps
CPU time 4.89 seconds
Started Mar 10 01:05:02 PM PDT 24
Finished Mar 10 01:05:10 PM PDT 24
Peak memory 208960 kb
Host smart-72e4be4b-b29b-433a-9cdd-a238bb13bd1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695951892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.
695951892
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3838830640
Short name T168
Test name
Test status
Simulation time 130080179 ps
CPU time 5.7 seconds
Started Mar 10 02:45:20 PM PDT 24
Finished Mar 10 02:45:26 PM PDT 24
Peak memory 217836 kb
Host smart-6a6ab86e-8950-44cf-a318-78952d4d5dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838830640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3838830640
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2395254035
Short name T298
Test name
Test status
Simulation time 673120570 ps
CPU time 18.11 seconds
Started Mar 10 02:43:36 PM PDT 24
Finished Mar 10 02:43:55 PM PDT 24
Peak memory 209116 kb
Host smart-785d1513-83de-4016-8ac1-2184608ea3ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395254035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2395254035
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2340950983
Short name T209
Test name
Test status
Simulation time 131164155 ps
CPU time 6.03 seconds
Started Mar 10 02:43:51 PM PDT 24
Finished Mar 10 02:43:57 PM PDT 24
Peak memory 222160 kb
Host smart-dad3169a-872c-45ed-bf5c-1de9b6221385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340950983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2340950983
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2957027
Short name T156
Test name
Test status
Simulation time 231791738 ps
CPU time 6.61 seconds
Started Mar 10 01:05:20 PM PDT 24
Finished Mar 10 01:05:27 PM PDT 24
Peak memory 208932 kb
Host smart-1e5618f4-116f-407c-bb17-704c0fdad8b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.2957027
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.107007573
Short name T171
Test name
Test status
Simulation time 75811480 ps
CPU time 3.91 seconds
Started Mar 10 02:45:10 PM PDT 24
Finished Mar 10 02:45:14 PM PDT 24
Peak memory 218384 kb
Host smart-e7f658aa-76a6-4817-add1-53c69b645b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107007573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.107007573
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3948193478
Short name T15
Test name
Test status
Simulation time 257435994 ps
CPU time 9.54 seconds
Started Mar 10 02:44:54 PM PDT 24
Finished Mar 10 02:45:03 PM PDT 24
Peak memory 209784 kb
Host smart-7dbaec37-1c52-4f47-9a02-1cdec143e753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948193478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3948193478
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1605075013
Short name T54
Test name
Test status
Simulation time 120104391 ps
CPU time 4.3 seconds
Started Mar 10 02:41:52 PM PDT 24
Finished Mar 10 02:41:56 PM PDT 24
Peak memory 222916 kb
Host smart-b1e39388-f30a-403f-a72b-67efc7c3f34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605075013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1605075013
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3130772846
Short name T167
Test name
Test status
Simulation time 55755329 ps
CPU time 3.41 seconds
Started Mar 10 02:43:28 PM PDT 24
Finished Mar 10 02:43:32 PM PDT 24
Peak memory 214416 kb
Host smart-6e667ca5-b77c-4ea0-9808-9d1e016d9cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130772846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3130772846
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3061266281
Short name T130
Test name
Test status
Simulation time 92159955 ps
CPU time 2.4 seconds
Started Mar 10 02:45:33 PM PDT 24
Finished Mar 10 02:45:36 PM PDT 24
Peak memory 217272 kb
Host smart-52773075-b1d0-4756-b0b2-3996870785fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061266281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3061266281
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1565439851
Short name T173
Test name
Test status
Simulation time 282624010 ps
CPU time 4.81 seconds
Started Mar 10 02:45:37 PM PDT 24
Finished Mar 10 02:45:42 PM PDT 24
Peak memory 218020 kb
Host smart-6739cf3d-0fd3-454a-a113-d07d00daf338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565439851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1565439851
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2898190831
Short name T335
Test name
Test status
Simulation time 86374659 ps
CPU time 2.48 seconds
Started Mar 10 02:41:49 PM PDT 24
Finished Mar 10 02:41:51 PM PDT 24
Peak memory 214396 kb
Host smart-9087179e-5cde-4733-a4ef-c1fe7ad36a8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2898190831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2898190831
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2296947129
Short name T320
Test name
Test status
Simulation time 6287760755 ps
CPU time 81.04 seconds
Started Mar 10 02:41:58 PM PDT 24
Finished Mar 10 02:43:20 PM PDT 24
Peak memory 214628 kb
Host smart-e8ffd51d-ed2c-4dad-9413-a5d113d16e6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2296947129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2296947129
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1335541119
Short name T251
Test name
Test status
Simulation time 38848670 ps
CPU time 2.71 seconds
Started Mar 10 02:43:07 PM PDT 24
Finished Mar 10 02:43:10 PM PDT 24
Peak memory 211128 kb
Host smart-fa6405a3-bd90-44ee-b50a-5dd12050c01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335541119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1335541119
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1765526408
Short name T176
Test name
Test status
Simulation time 468420243 ps
CPU time 4.87 seconds
Started Mar 10 02:43:23 PM PDT 24
Finished Mar 10 02:43:28 PM PDT 24
Peak memory 210264 kb
Host smart-7bab01cc-9855-4fc5-9a57-2232d56afd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765526408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1765526408
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.564424610
Short name T306
Test name
Test status
Simulation time 36930726681 ps
CPU time 202.52 seconds
Started Mar 10 02:43:27 PM PDT 24
Finished Mar 10 02:46:50 PM PDT 24
Peak memory 222808 kb
Host smart-3f34566a-3a5d-4ae7-9049-5017218f232c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564424610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.564424610
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2815391875
Short name T216
Test name
Test status
Simulation time 48302608 ps
CPU time 2.59 seconds
Started Mar 10 02:43:27 PM PDT 24
Finished Mar 10 02:43:29 PM PDT 24
Peak memory 207936 kb
Host smart-e58d1e65-84d7-4d13-ae33-4938ac6f7d96
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815391875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2815391875
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1748887106
Short name T296
Test name
Test status
Simulation time 373163542 ps
CPU time 4.88 seconds
Started Mar 10 02:43:55 PM PDT 24
Finished Mar 10 02:44:00 PM PDT 24
Peak memory 214488 kb
Host smart-9da46dee-13f7-438f-85c4-cde8b6cf36e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748887106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1748887106
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1414593520
Short name T88
Test name
Test status
Simulation time 684966236 ps
CPU time 6.52 seconds
Started Mar 10 02:42:13 PM PDT 24
Finished Mar 10 02:42:20 PM PDT 24
Peak memory 211472 kb
Host smart-c1d743d5-961e-4979-a83b-fea27e921354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414593520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1414593520
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.271569486
Short name T277
Test name
Test status
Simulation time 172378592 ps
CPU time 5.19 seconds
Started Mar 10 02:44:30 PM PDT 24
Finished Mar 10 02:44:37 PM PDT 24
Peak memory 214460 kb
Host smart-0cef0c46-2518-4bd7-bd9e-22aaf3d8bae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271569486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.271569486
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1150155362
Short name T415
Test name
Test status
Simulation time 9685623991 ps
CPU time 144.06 seconds
Started Mar 10 02:45:24 PM PDT 24
Finished Mar 10 02:47:48 PM PDT 24
Peak memory 221996 kb
Host smart-a710e88b-1626-4604-a97c-3b41ee38e8a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1150155362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1150155362
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.4118292177
Short name T285
Test name
Test status
Simulation time 135361995 ps
CPU time 5.31 seconds
Started Mar 10 02:42:27 PM PDT 24
Finished Mar 10 02:42:33 PM PDT 24
Peak memory 211092 kb
Host smart-a901d939-040b-45d0-8f0a-a47cb80b64f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118292177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.4118292177
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3899726785
Short name T237
Test name
Test status
Simulation time 570037003 ps
CPU time 27.08 seconds
Started Mar 10 02:45:31 PM PDT 24
Finished Mar 10 02:45:58 PM PDT 24
Peak memory 216152 kb
Host smart-45377ee2-362c-409f-80c3-10869ec91069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899726785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3899726785
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.3856049995
Short name T127
Test name
Test status
Simulation time 734858444 ps
CPU time 24.2 seconds
Started Mar 10 02:45:53 PM PDT 24
Finished Mar 10 02:46:17 PM PDT 24
Peak memory 222796 kb
Host smart-f40de587-eb7b-43b8-aa71-f680b59dc866
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856049995 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.3856049995
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.838152985
Short name T154
Test name
Test status
Simulation time 357731139 ps
CPU time 7.46 seconds
Started Mar 10 01:05:00 PM PDT 24
Finished Mar 10 01:05:08 PM PDT 24
Peak memory 208896 kb
Host smart-b3eefea4-44be-4c47-be0f-970ca97ee77a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838152985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
838152985
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1505460480
Short name T166
Test name
Test status
Simulation time 453929503 ps
CPU time 4.67 seconds
Started Mar 10 01:05:19 PM PDT 24
Finished Mar 10 01:05:24 PM PDT 24
Peak memory 209136 kb
Host smart-67010ace-feed-4c7a-a29b-2890db895de4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505460480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1505460480
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.416969346
Short name T161
Test name
Test status
Simulation time 1023551191 ps
CPU time 10.81 seconds
Started Mar 10 01:05:28 PM PDT 24
Finished Mar 10 01:05:39 PM PDT 24
Peak memory 209380 kb
Host smart-85a22d4c-126d-45a0-8d55-8804127362bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416969346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.416969346
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.4149412781
Short name T164
Test name
Test status
Simulation time 2222762522 ps
CPU time 11.09 seconds
Started Mar 10 01:05:34 PM PDT 24
Finished Mar 10 01:05:45 PM PDT 24
Peak memory 209492 kb
Host smart-9fd02866-8fb7-44cc-9764-939e1be19483
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149412781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.4149412781
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3792608645
Short name T157
Test name
Test status
Simulation time 332914480 ps
CPU time 3.71 seconds
Started Mar 10 01:05:34 PM PDT 24
Finished Mar 10 01:05:38 PM PDT 24
Peak memory 209388 kb
Host smart-1c27fc90-7bcd-40f8-b9a4-296c5c35f5cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792608645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3792608645
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.243714643
Short name T165
Test name
Test status
Simulation time 656597783 ps
CPU time 2.67 seconds
Started Mar 10 02:44:41 PM PDT 24
Finished Mar 10 02:44:43 PM PDT 24
Peak memory 209856 kb
Host smart-471af330-6c7c-4cc2-8733-06ae5e2afd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243714643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.243714643
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3660912366
Short name T174
Test name
Test status
Simulation time 94074134 ps
CPU time 4.05 seconds
Started Mar 10 02:42:22 PM PDT 24
Finished Mar 10 02:42:26 PM PDT 24
Peak memory 218444 kb
Host smart-09d291f7-af1e-4677-ba3c-4e01a4bfa195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660912366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3660912366
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3187969757
Short name T51
Test name
Test status
Simulation time 864273803 ps
CPU time 3.9 seconds
Started Mar 10 02:44:54 PM PDT 24
Finished Mar 10 02:44:58 PM PDT 24
Peak memory 214420 kb
Host smart-762a24b0-6387-491a-9236-4bb4203a89d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187969757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3187969757
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.547964142
Short name T233
Test name
Test status
Simulation time 234030994 ps
CPU time 3.8 seconds
Started Mar 10 02:42:02 PM PDT 24
Finished Mar 10 02:42:06 PM PDT 24
Peak memory 220296 kb
Host smart-8b9285db-3cbe-4020-90b5-e0c69e9089cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547964142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.547964142
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2285287314
Short name T240
Test name
Test status
Simulation time 150458416 ps
CPU time 3.05 seconds
Started Mar 10 02:43:12 PM PDT 24
Finished Mar 10 02:43:15 PM PDT 24
Peak memory 214552 kb
Host smart-db3f474a-b65d-4da0-925c-3e0693536139
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2285287314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2285287314
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1964439347
Short name T214
Test name
Test status
Simulation time 747179727 ps
CPU time 9.17 seconds
Started Mar 10 02:43:26 PM PDT 24
Finished Mar 10 02:43:36 PM PDT 24
Peak memory 208028 kb
Host smart-1c087f71-3723-4bd9-b086-f3779966b7e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964439347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1964439347
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1363156264
Short name T369
Test name
Test status
Simulation time 103150022 ps
CPU time 3.89 seconds
Started Mar 10 02:43:34 PM PDT 24
Finished Mar 10 02:43:38 PM PDT 24
Peak memory 214460 kb
Host smart-d09fa940-969f-48a3-9303-655955d37b40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1363156264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1363156264
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2150929510
Short name T263
Test name
Test status
Simulation time 85312080 ps
CPU time 3.69 seconds
Started Mar 10 02:43:44 PM PDT 24
Finished Mar 10 02:43:48 PM PDT 24
Peak memory 208496 kb
Host smart-ad1d27ff-1b44-4f5b-a458-d47c43edb32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150929510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2150929510
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.1828890768
Short name T283
Test name
Test status
Simulation time 154277301 ps
CPU time 3.36 seconds
Started Mar 10 02:44:01 PM PDT 24
Finished Mar 10 02:44:05 PM PDT 24
Peak memory 211648 kb
Host smart-f7b0792a-b163-40c0-aec4-f285e8132f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828890768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.1828890768
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1095211820
Short name T317
Test name
Test status
Simulation time 124280485 ps
CPU time 2.6 seconds
Started Mar 10 02:44:14 PM PDT 24
Finished Mar 10 02:44:17 PM PDT 24
Peak memory 211184 kb
Host smart-618da4f9-501c-4361-922b-4f2fd2902248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095211820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1095211820
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1885889737
Short name T227
Test name
Test status
Simulation time 410732351 ps
CPU time 6.13 seconds
Started Mar 10 02:44:18 PM PDT 24
Finished Mar 10 02:44:24 PM PDT 24
Peak memory 220184 kb
Host smart-1aab8c10-32e1-43a0-9bb1-dc77c3143926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885889737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1885889737
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3792741321
Short name T323
Test name
Test status
Simulation time 550832596 ps
CPU time 2.97 seconds
Started Mar 10 02:44:23 PM PDT 24
Finished Mar 10 02:44:27 PM PDT 24
Peak memory 222796 kb
Host smart-19b9f280-b10c-4d63-921f-109c9d77fa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792741321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3792741321
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.522583534
Short name T319
Test name
Test status
Simulation time 405750869 ps
CPU time 4.83 seconds
Started Mar 10 02:44:50 PM PDT 24
Finished Mar 10 02:44:55 PM PDT 24
Peak memory 214488 kb
Host smart-4026f7e9-2b84-4b86-b13f-2a3c3b9b5d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522583534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.522583534
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2648674123
Short name T344
Test name
Test status
Simulation time 840006971 ps
CPU time 5.25 seconds
Started Mar 10 02:44:51 PM PDT 24
Finished Mar 10 02:44:57 PM PDT 24
Peak memory 211324 kb
Host smart-138a1dd6-29e4-42d0-9517-5605d85ed6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648674123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2648674123
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2978558078
Short name T235
Test name
Test status
Simulation time 92435956 ps
CPU time 3.25 seconds
Started Mar 10 02:45:06 PM PDT 24
Finished Mar 10 02:45:09 PM PDT 24
Peak memory 214600 kb
Host smart-f403a047-3bba-4305-a040-be96493870a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978558078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2978558078
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3314750515
Short name T109
Test name
Test status
Simulation time 420235746 ps
CPU time 2.99 seconds
Started Mar 10 02:45:06 PM PDT 24
Finished Mar 10 02:45:09 PM PDT 24
Peak memory 214532 kb
Host smart-51a793e5-c5e9-4ec8-a6c7-9e715a7c86e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3314750515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3314750515
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3126616483
Short name T376
Test name
Test status
Simulation time 800761744 ps
CPU time 5.86 seconds
Started Mar 10 02:42:27 PM PDT 24
Finished Mar 10 02:42:34 PM PDT 24
Peak memory 220840 kb
Host smart-ee1d6da9-894b-4d2a-8fec-1a884c8aa8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126616483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3126616483
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.183255104
Short name T64
Test name
Test status
Simulation time 47067138 ps
CPU time 3.08 seconds
Started Mar 10 02:45:44 PM PDT 24
Finished Mar 10 02:45:47 PM PDT 24
Peak memory 207684 kb
Host smart-91ad3cfb-57be-4c39-b039-18b021dcda77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183255104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.183255104
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2912020809
Short name T318
Test name
Test status
Simulation time 31305886 ps
CPU time 2.15 seconds
Started Mar 10 02:45:56 PM PDT 24
Finished Mar 10 02:45:58 PM PDT 24
Peak memory 209160 kb
Host smart-671bc8b7-9faf-4b8c-b738-b70c44652584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912020809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2912020809
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1809810085
Short name T101
Test name
Test status
Simulation time 3417806545 ps
CPU time 12.23 seconds
Started Mar 10 02:42:06 PM PDT 24
Finished Mar 10 02:42:18 PM PDT 24
Peak memory 232300 kb
Host smart-c095d862-8156-4921-8c23-ff62cb93ba6c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809810085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1809810085
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2713369792
Short name T175
Test name
Test status
Simulation time 191378909 ps
CPU time 7.34 seconds
Started Mar 10 02:43:22 PM PDT 24
Finished Mar 10 02:43:29 PM PDT 24
Peak memory 222980 kb
Host smart-668f297b-ee39-47f0-9233-61fb38783a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713369792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2713369792
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2337618968
Short name T1006
Test name
Test status
Simulation time 68274715 ps
CPU time 4.1 seconds
Started Mar 10 01:04:56 PM PDT 24
Finished Mar 10 01:05:00 PM PDT 24
Peak memory 205960 kb
Host smart-c1ffb7ec-6c4c-4dbc-b972-0d9acfdcd303
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337618968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
337618968
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2221737736
Short name T1043
Test name
Test status
Simulation time 2871526646 ps
CPU time 12.91 seconds
Started Mar 10 01:04:56 PM PDT 24
Finished Mar 10 01:05:09 PM PDT 24
Peak memory 206020 kb
Host smart-22114296-43f2-405e-9556-c65ae74fed00
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221737736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
221737736
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.713911349
Short name T1028
Test name
Test status
Simulation time 27813646 ps
CPU time 1.16 seconds
Started Mar 10 01:04:56 PM PDT 24
Finished Mar 10 01:04:57 PM PDT 24
Peak memory 205896 kb
Host smart-d2af64bc-2f26-4e59-ae58-64c2dfa76c16
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713911349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.713911349
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.404099923
Short name T1020
Test name
Test status
Simulation time 34574812 ps
CPU time 1.57 seconds
Started Mar 10 01:04:54 PM PDT 24
Finished Mar 10 01:04:57 PM PDT 24
Peak memory 214228 kb
Host smart-d9dedb0d-0dc6-4c35-8694-7647eadcc147
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404099923 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.404099923
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1533844201
Short name T1035
Test name
Test status
Simulation time 23140594 ps
CPU time 0.98 seconds
Started Mar 10 01:04:57 PM PDT 24
Finished Mar 10 01:04:58 PM PDT 24
Peak memory 205732 kb
Host smart-b79febdb-4174-495f-b53d-dad4918cfff1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533844201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1533844201
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3627339728
Short name T952
Test name
Test status
Simulation time 60056132 ps
CPU time 0.71 seconds
Started Mar 10 01:04:57 PM PDT 24
Finished Mar 10 01:04:57 PM PDT 24
Peak memory 205588 kb
Host smart-9b45cee1-3040-4beb-9366-ee8225d1b353
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627339728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3627339728
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.120721089
Short name T924
Test name
Test status
Simulation time 97819508 ps
CPU time 1.46 seconds
Started Mar 10 01:04:56 PM PDT 24
Finished Mar 10 01:04:57 PM PDT 24
Peak memory 205796 kb
Host smart-c9a2a167-a9f3-40e6-a0b8-806bfb8ec7f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120721089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.120721089
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.923591058
Short name T976
Test name
Test status
Simulation time 1370918047 ps
CPU time 13.39 seconds
Started Mar 10 01:04:57 PM PDT 24
Finished Mar 10 01:05:11 PM PDT 24
Peak memory 214576 kb
Host smart-d0300c74-4513-43e6-bd54-9e09347c6669
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923591058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.923591058
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2545809873
Short name T956
Test name
Test status
Simulation time 373341316 ps
CPU time 3.57 seconds
Started Mar 10 01:04:56 PM PDT 24
Finished Mar 10 01:05:00 PM PDT 24
Peak memory 215164 kb
Host smart-06a9d846-9088-45c6-9cab-468f27e4c913
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545809873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2545809873
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3290653843
Short name T986
Test name
Test status
Simulation time 162188336 ps
CPU time 3.18 seconds
Started Mar 10 01:04:54 PM PDT 24
Finished Mar 10 01:04:58 PM PDT 24
Peak memory 209436 kb
Host smart-a7f6d8dd-1703-41e2-890f-814927630e38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290653843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3290653843
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2867189885
Short name T1042
Test name
Test status
Simulation time 2040470067 ps
CPU time 17.9 seconds
Started Mar 10 01:05:03 PM PDT 24
Finished Mar 10 01:05:23 PM PDT 24
Peak memory 205996 kb
Host smart-09f25e6f-d792-41e1-9a72-ffac13d31b15
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867189885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
867189885
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.4052105061
Short name T958
Test name
Test status
Simulation time 1138665984 ps
CPU time 29.38 seconds
Started Mar 10 01:05:01 PM PDT 24
Finished Mar 10 01:05:34 PM PDT 24
Peak memory 205896 kb
Host smart-743d3f2d-8b6f-4cdc-832d-796021f9ec9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052105061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.4
052105061
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1417826814
Short name T933
Test name
Test status
Simulation time 17932432 ps
CPU time 1.37 seconds
Started Mar 10 01:05:02 PM PDT 24
Finished Mar 10 01:05:06 PM PDT 24
Peak memory 205968 kb
Host smart-f61af3a9-ca37-421b-be87-03add4ff286d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417826814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
417826814
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1955575878
Short name T1034
Test name
Test status
Simulation time 96815771 ps
CPU time 1.39 seconds
Started Mar 10 01:05:01 PM PDT 24
Finished Mar 10 01:05:06 PM PDT 24
Peak memory 206068 kb
Host smart-4725fa2a-5a90-462c-ac66-a57dd816fc74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955575878 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1955575878
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.737964858
Short name T138
Test name
Test status
Simulation time 47891265 ps
CPU time 1.41 seconds
Started Mar 10 01:05:02 PM PDT 24
Finished Mar 10 01:05:06 PM PDT 24
Peak memory 205932 kb
Host smart-4cd9cde6-7ea4-4bb8-8c50-04c00685cd87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737964858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.737964858
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.922482145
Short name T905
Test name
Test status
Simulation time 18044484 ps
CPU time 0.83 seconds
Started Mar 10 01:05:02 PM PDT 24
Finished Mar 10 01:05:06 PM PDT 24
Peak memory 205680 kb
Host smart-a88b7b2d-dfb3-4969-a29f-d0bbc760abdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922482145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.922482145
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.565461805
Short name T137
Test name
Test status
Simulation time 70353251 ps
CPU time 2.19 seconds
Started Mar 10 01:05:03 PM PDT 24
Finished Mar 10 01:05:07 PM PDT 24
Peak memory 205952 kb
Host smart-68de2c53-dbe1-42f3-9e15-2c5639db5a5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565461805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.565461805
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3992843627
Short name T1062
Test name
Test status
Simulation time 169393595 ps
CPU time 4.37 seconds
Started Mar 10 01:04:57 PM PDT 24
Finished Mar 10 01:05:02 PM PDT 24
Peak memory 214476 kb
Host smart-9dc9245b-ab10-4a4e-8ade-911a070e26f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992843627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3992843627
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.639343085
Short name T999
Test name
Test status
Simulation time 1222716808 ps
CPU time 8.76 seconds
Started Mar 10 01:04:58 PM PDT 24
Finished Mar 10 01:05:09 PM PDT 24
Peak memory 214380 kb
Host smart-f755bf15-7e7b-4aaf-93b3-4db69eadec4f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639343085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.639343085
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3511322062
Short name T918
Test name
Test status
Simulation time 50794370 ps
CPU time 2.19 seconds
Started Mar 10 01:05:03 PM PDT 24
Finished Mar 10 01:05:08 PM PDT 24
Peak memory 214172 kb
Host smart-aa9920e8-9749-439d-b209-dee5bc5fbb34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511322062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3511322062
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3788913011
Short name T980
Test name
Test status
Simulation time 53900392 ps
CPU time 1.22 seconds
Started Mar 10 01:05:22 PM PDT 24
Finished Mar 10 01:05:28 PM PDT 24
Peak memory 205680 kb
Host smart-0f9306dc-d372-47b8-80fb-2f16358205bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788913011 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3788913011
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3963966981
Short name T1004
Test name
Test status
Simulation time 137800205 ps
CPU time 1.25 seconds
Started Mar 10 01:05:22 PM PDT 24
Finished Mar 10 01:05:28 PM PDT 24
Peak memory 205980 kb
Host smart-85fd9511-8d65-4a5a-ae51-cd60005f7d1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963966981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3963966981
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3059153801
Short name T917
Test name
Test status
Simulation time 38803675 ps
CPU time 0.72 seconds
Started Mar 10 01:05:23 PM PDT 24
Finished Mar 10 01:05:27 PM PDT 24
Peak memory 205676 kb
Host smart-96d8b833-968f-428a-88be-8d927c9be6ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059153801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3059153801
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3728339364
Short name T1053
Test name
Test status
Simulation time 50231131 ps
CPU time 1.48 seconds
Started Mar 10 01:05:21 PM PDT 24
Finished Mar 10 01:05:25 PM PDT 24
Peak memory 205900 kb
Host smart-59395f64-11df-4b79-bf63-106e74837ca7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728339364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3728339364
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1919698261
Short name T1013
Test name
Test status
Simulation time 149134019 ps
CPU time 3.79 seconds
Started Mar 10 01:05:18 PM PDT 24
Finished Mar 10 01:05:22 PM PDT 24
Peak memory 214460 kb
Host smart-8173a0b6-80a3-408c-8f25-b6d030f04799
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919698261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1919698261
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3393587339
Short name T1045
Test name
Test status
Simulation time 628822974 ps
CPU time 1.8 seconds
Started Mar 10 01:05:22 PM PDT 24
Finished Mar 10 01:05:28 PM PDT 24
Peak memory 214204 kb
Host smart-9115100b-e0b8-4ef6-a067-45e9b3a0d82f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393587339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3393587339
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2632272575
Short name T1029
Test name
Test status
Simulation time 52226592 ps
CPU time 1.71 seconds
Started Mar 10 01:05:19 PM PDT 24
Finished Mar 10 01:05:21 PM PDT 24
Peak memory 214200 kb
Host smart-f30edd3e-d8bf-441d-9d54-5c846db0441f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632272575 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2632272575
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2734562385
Short name T136
Test name
Test status
Simulation time 17181458 ps
CPU time 0.94 seconds
Started Mar 10 01:05:23 PM PDT 24
Finished Mar 10 01:05:27 PM PDT 24
Peak memory 205540 kb
Host smart-c97a13a2-a9d6-47d2-9735-0774c005d716
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734562385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2734562385
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1810627555
Short name T916
Test name
Test status
Simulation time 66220491 ps
CPU time 0.81 seconds
Started Mar 10 01:05:20 PM PDT 24
Finished Mar 10 01:05:21 PM PDT 24
Peak memory 205576 kb
Host smart-5d5da20e-7949-4657-9e38-407ad32b6a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810627555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1810627555
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1570825698
Short name T984
Test name
Test status
Simulation time 44299684 ps
CPU time 2.09 seconds
Started Mar 10 01:05:23 PM PDT 24
Finished Mar 10 01:05:29 PM PDT 24
Peak memory 205884 kb
Host smart-8924c645-c567-482b-bbd7-0c7734e7eab4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570825698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1570825698
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3193222224
Short name T919
Test name
Test status
Simulation time 269597778 ps
CPU time 2.25 seconds
Started Mar 10 01:05:19 PM PDT 24
Finished Mar 10 01:05:22 PM PDT 24
Peak memory 214508 kb
Host smart-3837c435-e826-48f0-826f-c1394fc35ab6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193222224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3193222224
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2123799280
Short name T1032
Test name
Test status
Simulation time 84845171 ps
CPU time 3.72 seconds
Started Mar 10 01:05:20 PM PDT 24
Finished Mar 10 01:05:24 PM PDT 24
Peak memory 214628 kb
Host smart-3b255064-d0c5-4ed8-aa24-3b205652a294
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123799280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2123799280
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1872121089
Short name T901
Test name
Test status
Simulation time 126690807 ps
CPU time 3.39 seconds
Started Mar 10 01:05:23 PM PDT 24
Finished Mar 10 01:05:29 PM PDT 24
Peak memory 215348 kb
Host smart-8b64829a-adb4-4b10-a665-03db93ffb676
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872121089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1872121089
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2817642256
Short name T1022
Test name
Test status
Simulation time 563180935 ps
CPU time 2.31 seconds
Started Mar 10 01:05:27 PM PDT 24
Finished Mar 10 01:05:30 PM PDT 24
Peak memory 206068 kb
Host smart-0908b20a-929f-43d2-b882-a877203f2424
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817642256 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2817642256
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1581848219
Short name T140
Test name
Test status
Simulation time 58609485 ps
CPU time 1.06 seconds
Started Mar 10 01:05:21 PM PDT 24
Finished Mar 10 01:05:26 PM PDT 24
Peak memory 205964 kb
Host smart-1ba966d1-c32d-4399-9948-d302a81729f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581848219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1581848219
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2484240129
Short name T1039
Test name
Test status
Simulation time 57349778 ps
CPU time 0.74 seconds
Started Mar 10 01:05:22 PM PDT 24
Finished Mar 10 01:05:26 PM PDT 24
Peak memory 205644 kb
Host smart-e9e5a7f4-ff89-40fa-947c-352080606468
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484240129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2484240129
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.903194820
Short name T979
Test name
Test status
Simulation time 100297065 ps
CPU time 2.57 seconds
Started Mar 10 01:05:23 PM PDT 24
Finished Mar 10 01:05:29 PM PDT 24
Peak memory 205820 kb
Host smart-0ddcb6b6-2044-4c31-8a3c-9e4d0b03f51f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903194820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.903194820
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.4024287653
Short name T921
Test name
Test status
Simulation time 358977283 ps
CPU time 7.02 seconds
Started Mar 10 01:05:20 PM PDT 24
Finished Mar 10 01:05:27 PM PDT 24
Peak memory 214548 kb
Host smart-b6e4b2d0-4548-43a8-a048-69193a201c69
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024287653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.4024287653
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1855899867
Short name T915
Test name
Test status
Simulation time 613566809 ps
CPU time 4.67 seconds
Started Mar 10 01:05:18 PM PDT 24
Finished Mar 10 01:05:23 PM PDT 24
Peak memory 214660 kb
Host smart-7015cd2e-952d-4399-808c-00b013e9df8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855899867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1855899867
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1775141586
Short name T1012
Test name
Test status
Simulation time 110364706 ps
CPU time 2.27 seconds
Started Mar 10 01:05:24 PM PDT 24
Finished Mar 10 01:05:28 PM PDT 24
Peak memory 217256 kb
Host smart-827a153d-0e59-4a1f-8bf8-f1b09c07a183
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775141586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1775141586
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1479854166
Short name T149
Test name
Test status
Simulation time 219504572 ps
CPU time 5.08 seconds
Started Mar 10 01:05:18 PM PDT 24
Finished Mar 10 01:05:23 PM PDT 24
Peak memory 208800 kb
Host smart-94ab41a3-933e-437f-8a71-11a13a20a0e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479854166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1479854166
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3477977843
Short name T969
Test name
Test status
Simulation time 46585186 ps
CPU time 1.6 seconds
Started Mar 10 01:05:29 PM PDT 24
Finished Mar 10 01:05:31 PM PDT 24
Peak memory 214228 kb
Host smart-faa9dba6-04d4-49db-a2c7-57f7ceac4117
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477977843 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3477977843
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.925943005
Short name T942
Test name
Test status
Simulation time 260187422 ps
CPU time 1.53 seconds
Started Mar 10 01:05:29 PM PDT 24
Finished Mar 10 01:05:31 PM PDT 24
Peak memory 205956 kb
Host smart-2841027a-de9d-4004-9858-ffadca9e7156
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925943005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.925943005
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3362762757
Short name T951
Test name
Test status
Simulation time 15358400 ps
CPU time 0.82 seconds
Started Mar 10 01:05:28 PM PDT 24
Finished Mar 10 01:05:29 PM PDT 24
Peak memory 205760 kb
Host smart-5b112e69-0f0d-477a-9835-6ff1e56784e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362762757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3362762757
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2354168284
Short name T139
Test name
Test status
Simulation time 106471854 ps
CPU time 1.46 seconds
Started Mar 10 01:05:33 PM PDT 24
Finished Mar 10 01:05:35 PM PDT 24
Peak memory 205992 kb
Host smart-931e89c7-d779-4883-9db3-db3558c52eb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354168284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2354168284
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1689481967
Short name T1002
Test name
Test status
Simulation time 1810636911 ps
CPU time 7.59 seconds
Started Mar 10 01:05:27 PM PDT 24
Finished Mar 10 01:05:35 PM PDT 24
Peak memory 214532 kb
Host smart-64b310ed-afcd-4b93-8f6d-ec01d730b7e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689481967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1689481967
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.336606960
Short name T1003
Test name
Test status
Simulation time 712580342 ps
CPU time 8.02 seconds
Started Mar 10 01:05:29 PM PDT 24
Finished Mar 10 01:05:38 PM PDT 24
Peak memory 214376 kb
Host smart-5dd6ff45-b4eb-4ac2-af7a-74837863722f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336606960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_shadow_reg_errors_with_csr_rw.336606960
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3401259976
Short name T927
Test name
Test status
Simulation time 1070311813 ps
CPU time 2.94 seconds
Started Mar 10 01:05:27 PM PDT 24
Finished Mar 10 01:05:31 PM PDT 24
Peak memory 214168 kb
Host smart-d0801b27-de9e-4096-8379-50e46f17f509
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401259976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3401259976
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.133293342
Short name T1017
Test name
Test status
Simulation time 222896493 ps
CPU time 3.63 seconds
Started Mar 10 01:05:29 PM PDT 24
Finished Mar 10 01:05:33 PM PDT 24
Peak memory 208992 kb
Host smart-40bcb785-2c8a-4482-8452-afceeae6e4b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133293342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.133293342
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1378942421
Short name T966
Test name
Test status
Simulation time 44184607 ps
CPU time 2.02 seconds
Started Mar 10 01:05:26 PM PDT 24
Finished Mar 10 01:05:29 PM PDT 24
Peak memory 214312 kb
Host smart-86af211e-31a9-4c82-a63b-50eeb3616ae9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378942421 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1378942421
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.413426762
Short name T142
Test name
Test status
Simulation time 63937525 ps
CPU time 1.26 seconds
Started Mar 10 01:05:25 PM PDT 24
Finished Mar 10 01:05:28 PM PDT 24
Peak memory 206028 kb
Host smart-b4cc45fe-5b0c-46ca-89df-38c3dddfb6df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413426762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.413426762
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3596201642
Short name T939
Test name
Test status
Simulation time 16598204 ps
CPU time 0.8 seconds
Started Mar 10 01:05:29 PM PDT 24
Finished Mar 10 01:05:30 PM PDT 24
Peak memory 205580 kb
Host smart-0c062dab-c765-476a-a2d5-7f0edbac678d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596201642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3596201642
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2143394353
Short name T1007
Test name
Test status
Simulation time 22539043 ps
CPU time 1.49 seconds
Started Mar 10 01:05:27 PM PDT 24
Finished Mar 10 01:05:29 PM PDT 24
Peak memory 205940 kb
Host smart-0c1fa45a-eb9e-4a80-a2aa-7de4d58b4720
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143394353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2143394353
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3606498721
Short name T913
Test name
Test status
Simulation time 313722093 ps
CPU time 2.86 seconds
Started Mar 10 01:05:26 PM PDT 24
Finished Mar 10 01:05:30 PM PDT 24
Peak memory 214440 kb
Host smart-92387d15-fda6-4b33-8d0e-9a599feeb469
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606498721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3606498721
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3107229929
Short name T121
Test name
Test status
Simulation time 619631528 ps
CPU time 8.6 seconds
Started Mar 10 01:05:29 PM PDT 24
Finished Mar 10 01:05:38 PM PDT 24
Peak memory 214376 kb
Host smart-3ec660ab-2687-4348-9026-fc1b69efcb10
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107229929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3107229929
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2933247446
Short name T928
Test name
Test status
Simulation time 247430933 ps
CPU time 4.42 seconds
Started Mar 10 01:05:29 PM PDT 24
Finished Mar 10 01:05:34 PM PDT 24
Peak memory 216396 kb
Host smart-c9b979d8-12b3-4ceb-b131-fc26d316e6b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933247446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2933247446
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2786812687
Short name T968
Test name
Test status
Simulation time 34822776 ps
CPU time 1.07 seconds
Started Mar 10 01:05:28 PM PDT 24
Finished Mar 10 01:05:30 PM PDT 24
Peak memory 205740 kb
Host smart-4874000a-fd10-499f-902b-e8f6f2429cf1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786812687 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2786812687
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2818584351
Short name T1050
Test name
Test status
Simulation time 12944480 ps
CPU time 1.18 seconds
Started Mar 10 01:05:29 PM PDT 24
Finished Mar 10 01:05:30 PM PDT 24
Peak memory 205944 kb
Host smart-8893f13d-30f5-44ab-922d-c00ed58014c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818584351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2818584351
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3236227818
Short name T904
Test name
Test status
Simulation time 10770647 ps
CPU time 0.8 seconds
Started Mar 10 01:05:27 PM PDT 24
Finished Mar 10 01:05:29 PM PDT 24
Peak memory 205596 kb
Host smart-71186a53-3f33-411f-a59f-c5f00e0843bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236227818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3236227818
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2729796385
Short name T143
Test name
Test status
Simulation time 115155776 ps
CPU time 2 seconds
Started Mar 10 01:05:28 PM PDT 24
Finished Mar 10 01:05:30 PM PDT 24
Peak memory 205904 kb
Host smart-6a6e858c-7c54-47cc-a7a8-2679bedc1b0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729796385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2729796385
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.4077062105
Short name T974
Test name
Test status
Simulation time 768476492 ps
CPU time 5.81 seconds
Started Mar 10 01:05:29 PM PDT 24
Finished Mar 10 01:05:35 PM PDT 24
Peak memory 222616 kb
Host smart-cd7c45c3-c9ff-4df9-9bd6-b96c0435e392
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077062105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.4077062105
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3770446722
Short name T988
Test name
Test status
Simulation time 654831231 ps
CPU time 5.4 seconds
Started Mar 10 01:05:28 PM PDT 24
Finished Mar 10 01:05:33 PM PDT 24
Peak memory 214452 kb
Host smart-dc107dac-61e4-4382-afc2-0d3f79fd2e54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770446722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3770446722
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2624376582
Short name T1061
Test name
Test status
Simulation time 60604590 ps
CPU time 2.42 seconds
Started Mar 10 01:05:30 PM PDT 24
Finished Mar 10 01:05:33 PM PDT 24
Peak memory 214072 kb
Host smart-3a5280b8-08f9-49b4-80f4-ed17ecb19893
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624376582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2624376582
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3170332626
Short name T959
Test name
Test status
Simulation time 40520825 ps
CPU time 1.51 seconds
Started Mar 10 01:05:33 PM PDT 24
Finished Mar 10 01:05:35 PM PDT 24
Peak memory 214368 kb
Host smart-5de0ea25-a203-4971-8841-65a9e540441e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170332626 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3170332626
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3496792280
Short name T1060
Test name
Test status
Simulation time 24942114 ps
CPU time 1.09 seconds
Started Mar 10 01:05:32 PM PDT 24
Finished Mar 10 01:05:34 PM PDT 24
Peak memory 205912 kb
Host smart-aef70c2b-e0d0-48ed-bbd9-304ced155741
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496792280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3496792280
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3808805415
Short name T993
Test name
Test status
Simulation time 11461838 ps
CPU time 0.73 seconds
Started Mar 10 01:05:29 PM PDT 24
Finished Mar 10 01:05:30 PM PDT 24
Peak memory 205668 kb
Host smart-92f0dbc6-2050-4e2a-8416-53420872c5ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808805415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3808805415
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2281614821
Short name T141
Test name
Test status
Simulation time 319149094 ps
CPU time 3.1 seconds
Started Mar 10 01:05:34 PM PDT 24
Finished Mar 10 01:05:37 PM PDT 24
Peak memory 206068 kb
Host smart-53475617-eab8-4e50-95ef-8dd69dd18111
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281614821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2281614821
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3048318154
Short name T960
Test name
Test status
Simulation time 42579569 ps
CPU time 1.47 seconds
Started Mar 10 01:05:26 PM PDT 24
Finished Mar 10 01:05:29 PM PDT 24
Peak memory 214496 kb
Host smart-1b297fdf-b5ef-4b19-b963-c80ce33927ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048318154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3048318154
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1414392741
Short name T1058
Test name
Test status
Simulation time 316253618 ps
CPU time 4.14 seconds
Started Mar 10 01:05:30 PM PDT 24
Finished Mar 10 01:05:34 PM PDT 24
Peak memory 214460 kb
Host smart-8144a813-8756-4bef-b6e9-1f0a450bedb7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414392741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1414392741
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2404962511
Short name T1051
Test name
Test status
Simulation time 385890214 ps
CPU time 3.34 seconds
Started Mar 10 01:05:27 PM PDT 24
Finished Mar 10 01:05:31 PM PDT 24
Peak memory 216292 kb
Host smart-6e560964-a4d1-4610-8411-13c1d9bf4344
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404962511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2404962511
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2323050290
Short name T964
Test name
Test status
Simulation time 619898002 ps
CPU time 1.62 seconds
Started Mar 10 01:05:34 PM PDT 24
Finished Mar 10 01:05:36 PM PDT 24
Peak memory 214176 kb
Host smart-69f7e178-d3a0-4eb5-8953-e62bae5b8116
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323050290 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2323050290
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.443489582
Short name T965
Test name
Test status
Simulation time 19865372 ps
CPU time 0.96 seconds
Started Mar 10 01:05:33 PM PDT 24
Finished Mar 10 01:05:35 PM PDT 24
Peak memory 205820 kb
Host smart-fa49d946-d063-4ab3-b517-62364b77dc10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443489582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.443489582
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.4192648515
Short name T1026
Test name
Test status
Simulation time 42067303 ps
CPU time 0.87 seconds
Started Mar 10 01:05:35 PM PDT 24
Finished Mar 10 01:05:35 PM PDT 24
Peak memory 205512 kb
Host smart-26a5fd2f-545e-4e4e-aea3-43473c32c9b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192648515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.4192648515
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1807195507
Short name T943
Test name
Test status
Simulation time 33710277 ps
CPU time 2.49 seconds
Started Mar 10 01:05:38 PM PDT 24
Finished Mar 10 01:05:42 PM PDT 24
Peak memory 205928 kb
Host smart-8cd2141e-04c9-45c2-8006-a403a1cefdf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807195507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1807195507
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2064321272
Short name T123
Test name
Test status
Simulation time 391309754 ps
CPU time 9.67 seconds
Started Mar 10 01:05:37 PM PDT 24
Finished Mar 10 01:05:47 PM PDT 24
Peak memory 214460 kb
Host smart-11d7d532-845c-4b27-8bba-517161234bc7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064321272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2064321272
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3266352089
Short name T1054
Test name
Test status
Simulation time 109930598 ps
CPU time 3.55 seconds
Started Mar 10 01:05:37 PM PDT 24
Finished Mar 10 01:05:41 PM PDT 24
Peak memory 214384 kb
Host smart-9e731a44-ce2c-4b0a-8144-4800aad8882b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266352089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3266352089
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.104505965
Short name T1023
Test name
Test status
Simulation time 235367840 ps
CPU time 4.01 seconds
Started Mar 10 01:05:35 PM PDT 24
Finished Mar 10 01:05:39 PM PDT 24
Peak memory 216212 kb
Host smart-7dc49f20-04fa-4b4f-9f10-3a5bd46e3bbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104505965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.104505965
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3872648118
Short name T152
Test name
Test status
Simulation time 483990706 ps
CPU time 13.05 seconds
Started Mar 10 01:05:32 PM PDT 24
Finished Mar 10 01:05:45 PM PDT 24
Peak memory 214148 kb
Host smart-46851b46-fc46-4321-8f25-c9ea9c5197c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872648118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3872648118
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.4116928850
Short name T1055
Test name
Test status
Simulation time 30928983 ps
CPU time 1.22 seconds
Started Mar 10 01:05:34 PM PDT 24
Finished Mar 10 01:05:35 PM PDT 24
Peak memory 214260 kb
Host smart-e3c75b0c-5391-4b4a-8c1e-ec29e3d26994
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116928850 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.4116928850
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1506648657
Short name T1063
Test name
Test status
Simulation time 26290151 ps
CPU time 1.19 seconds
Started Mar 10 01:05:38 PM PDT 24
Finished Mar 10 01:05:41 PM PDT 24
Peak memory 205984 kb
Host smart-a6dd09a0-3804-41f0-bb56-49cecce0d441
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506648657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1506648657
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3207865632
Short name T949
Test name
Test status
Simulation time 25308909 ps
CPU time 0.72 seconds
Started Mar 10 01:05:37 PM PDT 24
Finished Mar 10 01:05:38 PM PDT 24
Peak memory 205644 kb
Host smart-854e8c2c-3683-4236-ba74-c4983261accb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207865632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3207865632
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2598561018
Short name T985
Test name
Test status
Simulation time 63716980 ps
CPU time 2.65 seconds
Started Mar 10 01:05:34 PM PDT 24
Finished Mar 10 01:05:37 PM PDT 24
Peak memory 205944 kb
Host smart-6e5915a0-082c-4562-82e9-08d58470f131
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598561018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2598561018
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.876859968
Short name T112
Test name
Test status
Simulation time 1800676138 ps
CPU time 4.07 seconds
Started Mar 10 01:05:35 PM PDT 24
Finished Mar 10 01:05:39 PM PDT 24
Peak memory 214340 kb
Host smart-9876c123-c668-4398-a2d8-d113c35c0dda
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876859968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.876859968
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.4164377047
Short name T946
Test name
Test status
Simulation time 848032054 ps
CPU time 7.66 seconds
Started Mar 10 01:05:37 PM PDT 24
Finished Mar 10 01:05:46 PM PDT 24
Peak memory 220200 kb
Host smart-00a898ea-e139-465b-a6a2-299f5e512092
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164377047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.4164377047
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1771238557
Short name T929
Test name
Test status
Simulation time 128534310 ps
CPU time 3.27 seconds
Started Mar 10 01:05:34 PM PDT 24
Finished Mar 10 01:05:38 PM PDT 24
Peak memory 214396 kb
Host smart-8581207f-1a65-4dc8-bf35-9ed3c3551789
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771238557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1771238557
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.80560296
Short name T1019
Test name
Test status
Simulation time 51743615 ps
CPU time 2.44 seconds
Started Mar 10 01:05:35 PM PDT 24
Finished Mar 10 01:05:37 PM PDT 24
Peak memory 214220 kb
Host smart-498f1e28-a4f4-4ba7-8ca7-db290b2ce124
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80560296 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.80560296
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3058106209
Short name T1036
Test name
Test status
Simulation time 20846776 ps
CPU time 0.94 seconds
Started Mar 10 01:05:34 PM PDT 24
Finished Mar 10 01:05:35 PM PDT 24
Peak memory 205792 kb
Host smart-cb08fa22-3d87-4dfd-81d0-83286ca96e73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058106209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3058106209
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1016172716
Short name T1000
Test name
Test status
Simulation time 26267582 ps
CPU time 0.8 seconds
Started Mar 10 01:05:35 PM PDT 24
Finished Mar 10 01:05:36 PM PDT 24
Peak memory 205672 kb
Host smart-de9f820a-33e6-43c6-866b-f823c5adc3ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016172716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1016172716
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.702509079
Short name T967
Test name
Test status
Simulation time 144675645 ps
CPU time 2.19 seconds
Started Mar 10 01:05:36 PM PDT 24
Finished Mar 10 01:05:38 PM PDT 24
Peak memory 205972 kb
Host smart-e6d32b67-b31d-46cf-ba93-19d192f412c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702509079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.702509079
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2059023973
Short name T115
Test name
Test status
Simulation time 239422388 ps
CPU time 2.28 seconds
Started Mar 10 01:05:34 PM PDT 24
Finished Mar 10 01:05:37 PM PDT 24
Peak memory 214456 kb
Host smart-e7e08e0e-7f76-4601-82b2-6343fbfab3f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059023973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2059023973
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2379480979
Short name T995
Test name
Test status
Simulation time 79917301 ps
CPU time 2.27 seconds
Started Mar 10 01:05:34 PM PDT 24
Finished Mar 10 01:05:36 PM PDT 24
Peak memory 214160 kb
Host smart-251f3e99-0eb0-4050-ae45-04981294d5d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379480979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2379480979
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2340288339
Short name T994
Test name
Test status
Simulation time 1963005108 ps
CPU time 17.5 seconds
Started Mar 10 01:05:07 PM PDT 24
Finished Mar 10 01:05:26 PM PDT 24
Peak memory 205948 kb
Host smart-0cf50872-359c-43f7-8d2d-a8b45e052a32
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340288339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
340288339
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3578114399
Short name T146
Test name
Test status
Simulation time 267664295 ps
CPU time 13.65 seconds
Started Mar 10 01:05:08 PM PDT 24
Finished Mar 10 01:05:23 PM PDT 24
Peak memory 206052 kb
Host smart-abe13fc5-3e3f-4583-ae4b-d5e08305ca3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578114399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
578114399
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1942541775
Short name T1046
Test name
Test status
Simulation time 424137478 ps
CPU time 1.21 seconds
Started Mar 10 01:05:03 PM PDT 24
Finished Mar 10 01:05:06 PM PDT 24
Peak memory 206028 kb
Host smart-9dc5b870-b5b6-41e5-b32d-a16f4c205f6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942541775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
942541775
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2704682792
Short name T953
Test name
Test status
Simulation time 61698148 ps
CPU time 1.58 seconds
Started Mar 10 01:05:09 PM PDT 24
Finished Mar 10 01:05:11 PM PDT 24
Peak memory 214188 kb
Host smart-5b8bffbf-531b-4c3b-9494-420af673faee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704682792 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2704682792
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1066285845
Short name T931
Test name
Test status
Simulation time 19459802 ps
CPU time 0.9 seconds
Started Mar 10 01:05:06 PM PDT 24
Finished Mar 10 01:05:08 PM PDT 24
Peak memory 205716 kb
Host smart-a744f6c5-244f-463d-9013-9dab6967c63c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066285845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1066285845
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.546474031
Short name T938
Test name
Test status
Simulation time 13437392 ps
CPU time 0.71 seconds
Started Mar 10 01:05:00 PM PDT 24
Finished Mar 10 01:05:01 PM PDT 24
Peak memory 205648 kb
Host smart-eb2de68c-2d5f-4db7-80d4-edce009be50d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546474031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.546474031
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2013880512
Short name T977
Test name
Test status
Simulation time 83732476 ps
CPU time 1.68 seconds
Started Mar 10 01:05:07 PM PDT 24
Finished Mar 10 01:05:10 PM PDT 24
Peak memory 205892 kb
Host smart-c6a94069-ce17-4340-bbf4-b73186b29443
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013880512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2013880512
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1128777219
Short name T1047
Test name
Test status
Simulation time 1677352052 ps
CPU time 2.46 seconds
Started Mar 10 01:05:01 PM PDT 24
Finished Mar 10 01:05:07 PM PDT 24
Peak memory 214452 kb
Host smart-31e33cf9-fa76-4c03-a2d4-c88f1bcf03a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128777219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1128777219
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2985452497
Short name T926
Test name
Test status
Simulation time 1177709350 ps
CPU time 9.95 seconds
Started Mar 10 01:05:01 PM PDT 24
Finished Mar 10 01:05:15 PM PDT 24
Peak memory 214368 kb
Host smart-5febd88f-d006-4b5c-b1c0-0f41d945bdf1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985452497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2985452497
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3677046191
Short name T954
Test name
Test status
Simulation time 35870527 ps
CPU time 2.59 seconds
Started Mar 10 01:05:02 PM PDT 24
Finished Mar 10 01:05:08 PM PDT 24
Peak memory 217360 kb
Host smart-e2c1d7b0-39a1-4fed-ab64-690e9f33a330
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677046191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3677046191
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3580808316
Short name T992
Test name
Test status
Simulation time 33264872 ps
CPU time 0.7 seconds
Started Mar 10 01:05:34 PM PDT 24
Finished Mar 10 01:05:35 PM PDT 24
Peak memory 205588 kb
Host smart-5b102157-99bf-4611-b3a7-a6e39c9f2c2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580808316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3580808316
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1212609108
Short name T1025
Test name
Test status
Simulation time 19284698 ps
CPU time 0.81 seconds
Started Mar 10 01:05:39 PM PDT 24
Finished Mar 10 01:05:41 PM PDT 24
Peak memory 205636 kb
Host smart-cfebe8c3-692f-4c4f-afbc-041c75c1698a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212609108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1212609108
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.509287167
Short name T909
Test name
Test status
Simulation time 50159593 ps
CPU time 0.84 seconds
Started Mar 10 01:05:31 PM PDT 24
Finished Mar 10 01:05:32 PM PDT 24
Peak memory 205736 kb
Host smart-08b8d99b-b6bd-4843-9772-9b15f4b57995
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509287167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.509287167
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3576727008
Short name T1015
Test name
Test status
Simulation time 33431025 ps
CPU time 0.72 seconds
Started Mar 10 01:05:34 PM PDT 24
Finished Mar 10 01:05:34 PM PDT 24
Peak memory 205712 kb
Host smart-457235d6-98dd-4ecf-bca3-e71d30918462
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576727008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3576727008
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2716734796
Short name T930
Test name
Test status
Simulation time 19654672 ps
CPU time 0.76 seconds
Started Mar 10 01:05:36 PM PDT 24
Finished Mar 10 01:05:37 PM PDT 24
Peak memory 205664 kb
Host smart-a56d09c0-8e6f-4b51-b55b-bbf47c40ccef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716734796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2716734796
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1344113721
Short name T906
Test name
Test status
Simulation time 13097868 ps
CPU time 0.74 seconds
Started Mar 10 01:05:35 PM PDT 24
Finished Mar 10 01:05:36 PM PDT 24
Peak memory 205696 kb
Host smart-11e3f585-ccfb-47b3-92c3-7973da0a6745
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344113721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1344113721
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.623053462
Short name T1048
Test name
Test status
Simulation time 25957811 ps
CPU time 0.81 seconds
Started Mar 10 01:05:44 PM PDT 24
Finished Mar 10 01:05:46 PM PDT 24
Peak memory 205564 kb
Host smart-8d43c840-d67f-4e12-9f1e-ad8509655440
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623053462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.623053462
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3512708101
Short name T903
Test name
Test status
Simulation time 11176871 ps
CPU time 0.8 seconds
Started Mar 10 01:05:44 PM PDT 24
Finished Mar 10 01:05:46 PM PDT 24
Peak memory 205616 kb
Host smart-30f82973-03ce-4901-a121-c96b02f78d26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512708101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3512708101
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3227819336
Short name T957
Test name
Test status
Simulation time 16292393 ps
CPU time 0.94 seconds
Started Mar 10 01:05:44 PM PDT 24
Finished Mar 10 01:05:46 PM PDT 24
Peak memory 205816 kb
Host smart-3ae76f3c-17dd-41e8-803a-f52e39fd0ec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227819336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3227819336
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3955068929
Short name T944
Test name
Test status
Simulation time 45239298 ps
CPU time 0.71 seconds
Started Mar 10 01:05:44 PM PDT 24
Finished Mar 10 01:05:46 PM PDT 24
Peak memory 205656 kb
Host smart-35450b19-d08f-4c11-85b0-c51de988ceb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955068929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3955068929
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.38462889
Short name T920
Test name
Test status
Simulation time 545128217 ps
CPU time 7.29 seconds
Started Mar 10 01:05:07 PM PDT 24
Finished Mar 10 01:05:14 PM PDT 24
Peak memory 205996 kb
Host smart-f97545b2-6fb1-4224-8fea-2b375e895922
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38462889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.38462889
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1741782217
Short name T1014
Test name
Test status
Simulation time 435293014 ps
CPU time 8.45 seconds
Started Mar 10 01:05:09 PM PDT 24
Finished Mar 10 01:05:18 PM PDT 24
Peak memory 205992 kb
Host smart-baeb49e4-644f-45ad-8a4f-f2ae0ca3fe11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741782217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
741782217
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2440782134
Short name T1049
Test name
Test status
Simulation time 42170352 ps
CPU time 0.95 seconds
Started Mar 10 01:05:08 PM PDT 24
Finished Mar 10 01:05:10 PM PDT 24
Peak memory 205816 kb
Host smart-9a89a5b6-3fa3-4455-8508-b45d276777a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440782134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
440782134
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.632179472
Short name T945
Test name
Test status
Simulation time 150955842 ps
CPU time 1.44 seconds
Started Mar 10 01:05:07 PM PDT 24
Finished Mar 10 01:05:10 PM PDT 24
Peak memory 214288 kb
Host smart-1b02da5a-00d9-40cc-bb1e-2a6c62b83d4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632179472 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.632179472
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1377325874
Short name T936
Test name
Test status
Simulation time 21158677 ps
CPU time 0.94 seconds
Started Mar 10 01:05:08 PM PDT 24
Finished Mar 10 01:05:10 PM PDT 24
Peak memory 205764 kb
Host smart-f2653328-005f-414d-9539-f86b498353c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377325874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1377325874
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3216323263
Short name T908
Test name
Test status
Simulation time 44671554 ps
CPU time 0.73 seconds
Started Mar 10 01:05:09 PM PDT 24
Finished Mar 10 01:05:10 PM PDT 24
Peak memory 205588 kb
Host smart-f2fbd21b-b7ac-44f1-b30f-ba2e976b47d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216323263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3216323263
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.4228490939
Short name T1010
Test name
Test status
Simulation time 82076740 ps
CPU time 1.59 seconds
Started Mar 10 01:05:09 PM PDT 24
Finished Mar 10 01:05:11 PM PDT 24
Peak memory 205940 kb
Host smart-c04c579e-f44d-4739-8415-354fdae52117
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228490939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.4228490939
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3042371009
Short name T1044
Test name
Test status
Simulation time 143857544 ps
CPU time 1.92 seconds
Started Mar 10 01:05:09 PM PDT 24
Finished Mar 10 01:05:12 PM PDT 24
Peak memory 222556 kb
Host smart-a7a1e6de-6877-44df-9659-e0166400264b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042371009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3042371009
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1534758088
Short name T987
Test name
Test status
Simulation time 301872928 ps
CPU time 3.74 seconds
Started Mar 10 01:05:10 PM PDT 24
Finished Mar 10 01:05:15 PM PDT 24
Peak memory 214500 kb
Host smart-49cc7724-c6fb-41ba-945e-90a0d5ebe785
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534758088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1534758088
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3220582152
Short name T996
Test name
Test status
Simulation time 90369255 ps
CPU time 1.98 seconds
Started Mar 10 01:05:07 PM PDT 24
Finished Mar 10 01:05:11 PM PDT 24
Peak memory 214244 kb
Host smart-660bc6b7-ebe9-4649-9148-ef16f558bb43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220582152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3220582152
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.4234989724
Short name T159
Test name
Test status
Simulation time 236682376 ps
CPU time 9.6 seconds
Started Mar 10 01:05:07 PM PDT 24
Finished Mar 10 01:05:18 PM PDT 24
Peak memory 209372 kb
Host smart-0336ebf1-8c9a-4a3f-8dcc-9c7d2c017ea8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234989724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.4234989724
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.55353044
Short name T948
Test name
Test status
Simulation time 53566069 ps
CPU time 0.72 seconds
Started Mar 10 01:05:40 PM PDT 24
Finished Mar 10 01:05:42 PM PDT 24
Peak memory 205572 kb
Host smart-342c3ee7-7ea4-4a90-bea8-46b24616444f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55353044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.55353044
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3981000717
Short name T991
Test name
Test status
Simulation time 18257408 ps
CPU time 0.71 seconds
Started Mar 10 01:05:43 PM PDT 24
Finished Mar 10 01:05:46 PM PDT 24
Peak memory 205648 kb
Host smart-7a26d0d7-cbc0-490b-aed0-5de4b5a7724d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981000717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3981000717
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1430162283
Short name T922
Test name
Test status
Simulation time 8968566 ps
CPU time 0.79 seconds
Started Mar 10 01:05:41 PM PDT 24
Finished Mar 10 01:05:43 PM PDT 24
Peak memory 205580 kb
Host smart-bcc34f41-e40a-4a74-8322-06e28373481c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430162283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1430162283
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.75783270
Short name T982
Test name
Test status
Simulation time 37005407 ps
CPU time 0.79 seconds
Started Mar 10 01:05:40 PM PDT 24
Finished Mar 10 01:05:42 PM PDT 24
Peak memory 205688 kb
Host smart-251c05bc-5c2a-4c9d-8c66-7b874d0bea41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75783270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.75783270
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.4099452161
Short name T937
Test name
Test status
Simulation time 7395066 ps
CPU time 0.71 seconds
Started Mar 10 01:05:44 PM PDT 24
Finished Mar 10 01:05:46 PM PDT 24
Peak memory 205664 kb
Host smart-a8a44c38-8beb-4a96-83de-61117c016f55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099452161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.4099452161
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3958785363
Short name T899
Test name
Test status
Simulation time 29490042 ps
CPU time 0.82 seconds
Started Mar 10 01:05:44 PM PDT 24
Finished Mar 10 01:05:46 PM PDT 24
Peak memory 205588 kb
Host smart-b914841e-06ee-48f7-ac47-7265cf51b340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958785363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3958785363
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3339931273
Short name T1008
Test name
Test status
Simulation time 31162535 ps
CPU time 0.79 seconds
Started Mar 10 01:05:44 PM PDT 24
Finished Mar 10 01:05:46 PM PDT 24
Peak memory 205656 kb
Host smart-ad5ad3be-3cb0-4aa1-9b7c-d4bd308aaf8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339931273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3339931273
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.51520454
Short name T900
Test name
Test status
Simulation time 10627097 ps
CPU time 0.72 seconds
Started Mar 10 01:05:49 PM PDT 24
Finished Mar 10 01:05:50 PM PDT 24
Peak memory 205588 kb
Host smart-5c669730-4a55-436b-929f-1cf93e32ab96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51520454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.51520454
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3501443605
Short name T990
Test name
Test status
Simulation time 49339174 ps
CPU time 0.87 seconds
Started Mar 10 01:05:48 PM PDT 24
Finished Mar 10 01:05:49 PM PDT 24
Peak memory 205584 kb
Host smart-ce191e6d-2861-4f98-9c4e-a5c5aa3ff6c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501443605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3501443605
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3427869411
Short name T1037
Test name
Test status
Simulation time 13954101 ps
CPU time 0.71 seconds
Started Mar 10 01:05:47 PM PDT 24
Finished Mar 10 01:05:48 PM PDT 24
Peak memory 205744 kb
Host smart-8f3ada4e-549b-4591-bf79-1021f883fce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427869411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3427869411
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2650688022
Short name T1021
Test name
Test status
Simulation time 246165456 ps
CPU time 7.77 seconds
Started Mar 10 01:05:09 PM PDT 24
Finished Mar 10 01:05:18 PM PDT 24
Peak memory 205988 kb
Host smart-07928035-2aa0-496f-a5bd-3439ff8257fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650688022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
650688022
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.469229114
Short name T955
Test name
Test status
Simulation time 5337058452 ps
CPU time 31.04 seconds
Started Mar 10 01:05:07 PM PDT 24
Finished Mar 10 01:05:40 PM PDT 24
Peak memory 206084 kb
Host smart-b9b72480-e725-4a34-8469-03275716f560
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469229114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.469229114
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3033872315
Short name T973
Test name
Test status
Simulation time 39190676 ps
CPU time 1 seconds
Started Mar 10 01:05:08 PM PDT 24
Finished Mar 10 01:05:10 PM PDT 24
Peak memory 205804 kb
Host smart-2ba561b4-dbc9-4580-a4e5-ea652690b7e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033872315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
033872315
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.939280210
Short name T1057
Test name
Test status
Simulation time 55054419 ps
CPU time 2.29 seconds
Started Mar 10 01:05:09 PM PDT 24
Finished Mar 10 01:05:12 PM PDT 24
Peak memory 214312 kb
Host smart-b6088414-79af-4f16-b7a2-7acecde75aea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939280210 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.939280210
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1123815909
Short name T914
Test name
Test status
Simulation time 109350609 ps
CPU time 1.23 seconds
Started Mar 10 01:05:08 PM PDT 24
Finished Mar 10 01:05:10 PM PDT 24
Peak memory 206036 kb
Host smart-1bbd1aa3-8b2e-47bf-86c1-016a90e73d7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123815909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1123815909
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3780721217
Short name T972
Test name
Test status
Simulation time 11899629 ps
CPU time 0.84 seconds
Started Mar 10 01:05:10 PM PDT 24
Finished Mar 10 01:05:11 PM PDT 24
Peak memory 205680 kb
Host smart-c210d7e3-9ab5-42ec-a0fb-c905b1f36019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780721217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3780721217
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1147586372
Short name T1056
Test name
Test status
Simulation time 455147330 ps
CPU time 4.51 seconds
Started Mar 10 01:05:10 PM PDT 24
Finished Mar 10 01:05:15 PM PDT 24
Peak memory 205956 kb
Host smart-3f19bbc6-0a50-422f-93a4-77599f26c034
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147586372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1147586372
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.93334597
Short name T989
Test name
Test status
Simulation time 386842306 ps
CPU time 11.93 seconds
Started Mar 10 01:05:08 PM PDT 24
Finished Mar 10 01:05:21 PM PDT 24
Peak memory 214492 kb
Host smart-3defcb8a-5884-4623-8f40-9c7a9de7251d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93334597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_
reg_errors.93334597
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3265323543
Short name T120
Test name
Test status
Simulation time 234713193 ps
CPU time 8.18 seconds
Started Mar 10 01:05:08 PM PDT 24
Finished Mar 10 01:05:17 PM PDT 24
Peak memory 214404 kb
Host smart-1563ef27-1ec5-42ec-b916-9695db804b08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265323543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3265323543
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2586653606
Short name T902
Test name
Test status
Simulation time 45073894 ps
CPU time 2.51 seconds
Started Mar 10 01:05:07 PM PDT 24
Finished Mar 10 01:05:11 PM PDT 24
Peak memory 214152 kb
Host smart-b477f5c7-1f0f-4575-b0ad-4e5d38fa38c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586653606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2586653606
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2114794963
Short name T181
Test name
Test status
Simulation time 137828538 ps
CPU time 5.81 seconds
Started Mar 10 01:05:09 PM PDT 24
Finished Mar 10 01:05:15 PM PDT 24
Peak memory 209380 kb
Host smart-0d37004e-043d-41e6-bee4-e266dce0f165
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114794963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2114794963
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2141718694
Short name T947
Test name
Test status
Simulation time 9204004 ps
CPU time 0.78 seconds
Started Mar 10 01:05:46 PM PDT 24
Finished Mar 10 01:05:47 PM PDT 24
Peak memory 205660 kb
Host smart-2f0775cd-e8c2-4fec-add3-b7d2dcdacb10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141718694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2141718694
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.80827484
Short name T935
Test name
Test status
Simulation time 33758960 ps
CPU time 0.71 seconds
Started Mar 10 01:05:47 PM PDT 24
Finished Mar 10 01:05:49 PM PDT 24
Peak memory 205588 kb
Host smart-b3d9d83b-27b7-4817-8e0d-eb689f60076a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80827484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.80827484
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2127165515
Short name T962
Test name
Test status
Simulation time 39268418 ps
CPU time 0.74 seconds
Started Mar 10 01:05:48 PM PDT 24
Finished Mar 10 01:05:49 PM PDT 24
Peak memory 205596 kb
Host smart-d1d74934-14b7-43a9-b2a9-14032be01396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127165515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2127165515
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1145776327
Short name T1065
Test name
Test status
Simulation time 42015852 ps
CPU time 0.84 seconds
Started Mar 10 01:05:46 PM PDT 24
Finished Mar 10 01:05:47 PM PDT 24
Peak memory 205660 kb
Host smart-b4f04693-b157-40f7-9a0a-7fcf1bb070e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145776327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1145776327
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.993989621
Short name T981
Test name
Test status
Simulation time 50723407 ps
CPU time 0.79 seconds
Started Mar 10 01:05:46 PM PDT 24
Finished Mar 10 01:05:47 PM PDT 24
Peak memory 205732 kb
Host smart-88ef0b09-f8ac-45c6-a5b2-8b0b8923ac0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993989621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.993989621
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3646993418
Short name T912
Test name
Test status
Simulation time 13059171 ps
CPU time 0.8 seconds
Started Mar 10 01:05:45 PM PDT 24
Finished Mar 10 01:05:46 PM PDT 24
Peak memory 205640 kb
Host smart-80d9610e-48a5-4c68-98b4-b821950866b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646993418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3646993418
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2111346071
Short name T1001
Test name
Test status
Simulation time 24879390 ps
CPU time 0.74 seconds
Started Mar 10 01:05:50 PM PDT 24
Finished Mar 10 01:05:50 PM PDT 24
Peak memory 205648 kb
Host smart-1a942c84-d8c3-4319-ab7b-c9e91a43eded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111346071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2111346071
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.468353472
Short name T1011
Test name
Test status
Simulation time 42916540 ps
CPU time 0.82 seconds
Started Mar 10 01:05:47 PM PDT 24
Finished Mar 10 01:05:48 PM PDT 24
Peak memory 205664 kb
Host smart-606a8a07-3f1c-44f5-b1f3-d64763b35e65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468353472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.468353472
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2592575660
Short name T907
Test name
Test status
Simulation time 16924191 ps
CPU time 0.75 seconds
Started Mar 10 01:05:47 PM PDT 24
Finished Mar 10 01:05:48 PM PDT 24
Peak memory 205684 kb
Host smart-b4774ccc-ec01-42cc-9278-1fdd2d55ac4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592575660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2592575660
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.326695100
Short name T950
Test name
Test status
Simulation time 44383899 ps
CPU time 0.88 seconds
Started Mar 10 01:05:48 PM PDT 24
Finished Mar 10 01:05:49 PM PDT 24
Peak memory 205588 kb
Host smart-744b99bc-7f48-4a5c-b5d3-15cb292250bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326695100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.326695100
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.777113642
Short name T910
Test name
Test status
Simulation time 84358154 ps
CPU time 1.39 seconds
Started Mar 10 01:05:09 PM PDT 24
Finished Mar 10 01:05:12 PM PDT 24
Peak memory 214084 kb
Host smart-40bef6a1-d478-40b2-acda-f97206fa6794
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777113642 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.777113642
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.810203979
Short name T997
Test name
Test status
Simulation time 14956782 ps
CPU time 1.25 seconds
Started Mar 10 01:05:09 PM PDT 24
Finished Mar 10 01:05:11 PM PDT 24
Peak memory 205972 kb
Host smart-5a0cfc4c-18a5-4dca-a2df-1af3e2a9cd17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810203979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.810203979
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.4225028185
Short name T934
Test name
Test status
Simulation time 19986604 ps
CPU time 0.76 seconds
Started Mar 10 01:05:08 PM PDT 24
Finished Mar 10 01:05:10 PM PDT 24
Peak memory 205552 kb
Host smart-868974b3-ada4-4540-9d65-049e878cfd6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225028185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.4225028185
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1546792991
Short name T923
Test name
Test status
Simulation time 421060654 ps
CPU time 3.84 seconds
Started Mar 10 01:05:07 PM PDT 24
Finished Mar 10 01:05:12 PM PDT 24
Peak memory 205928 kb
Host smart-af9ac910-488b-452b-a902-85fe98ec98e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546792991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1546792991
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.445120850
Short name T1040
Test name
Test status
Simulation time 1050909388 ps
CPU time 33.02 seconds
Started Mar 10 01:05:07 PM PDT 24
Finished Mar 10 01:05:42 PM PDT 24
Peak memory 219436 kb
Host smart-2ada5980-1af9-4a18-a2a1-9c3c687a5483
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445120850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.445120850
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.252814027
Short name T941
Test name
Test status
Simulation time 623471041 ps
CPU time 8.57 seconds
Started Mar 10 01:05:07 PM PDT 24
Finished Mar 10 01:05:17 PM PDT 24
Peak memory 214460 kb
Host smart-f21c7ab8-ba31-4f6c-bf35-aeef9bd76525
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252814027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.252814027
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3341869082
Short name T1038
Test name
Test status
Simulation time 66073741 ps
CPU time 2.23 seconds
Started Mar 10 01:05:09 PM PDT 24
Finished Mar 10 01:05:12 PM PDT 24
Peak memory 214204 kb
Host smart-6ffd482b-3fa7-46f6-9b8d-0f85695e6792
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341869082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3341869082
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1309840543
Short name T162
Test name
Test status
Simulation time 123452889 ps
CPU time 3.38 seconds
Started Mar 10 01:05:08 PM PDT 24
Finished Mar 10 01:05:12 PM PDT 24
Peak memory 209040 kb
Host smart-a950351f-fdb0-4c48-9f46-5bab314bdafe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309840543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1309840543
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1550867906
Short name T1024
Test name
Test status
Simulation time 103077476 ps
CPU time 2.05 seconds
Started Mar 10 01:05:11 PM PDT 24
Finished Mar 10 01:05:13 PM PDT 24
Peak memory 214336 kb
Host smart-a0ffdb55-6d41-4ad9-8d61-572f4501030c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550867906 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1550867906
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2993695144
Short name T144
Test name
Test status
Simulation time 41281253 ps
CPU time 1.1 seconds
Started Mar 10 01:05:15 PM PDT 24
Finished Mar 10 01:05:16 PM PDT 24
Peak memory 205976 kb
Host smart-05146b8e-3c12-4e23-af9b-d1e75cc94e38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993695144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2993695144
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3528407569
Short name T1005
Test name
Test status
Simulation time 48137543 ps
CPU time 0.77 seconds
Started Mar 10 01:05:11 PM PDT 24
Finished Mar 10 01:05:12 PM PDT 24
Peak memory 205620 kb
Host smart-f07d269a-e3d9-46e7-83d2-9b1850c9c277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528407569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3528407569
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2224866111
Short name T925
Test name
Test status
Simulation time 120477522 ps
CPU time 2.27 seconds
Started Mar 10 01:05:12 PM PDT 24
Finished Mar 10 01:05:14 PM PDT 24
Peak memory 206052 kb
Host smart-3d3c654c-7d6b-4860-8270-9c35f81bb0dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224866111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2224866111
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1360614648
Short name T1030
Test name
Test status
Simulation time 158327379 ps
CPU time 3.76 seconds
Started Mar 10 01:05:08 PM PDT 24
Finished Mar 10 01:05:13 PM PDT 24
Peak memory 214452 kb
Host smart-2c18f8c8-de81-4b30-9219-3fe57a633d73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360614648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1360614648
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.823384809
Short name T1016
Test name
Test status
Simulation time 160684899 ps
CPU time 4.12 seconds
Started Mar 10 01:05:07 PM PDT 24
Finished Mar 10 01:05:13 PM PDT 24
Peak memory 214504 kb
Host smart-b8c89671-2654-4fb2-8b52-39eccc96d162
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823384809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.823384809
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.4186326770
Short name T1009
Test name
Test status
Simulation time 1154066929 ps
CPU time 3.06 seconds
Started Mar 10 01:05:08 PM PDT 24
Finished Mar 10 01:05:12 PM PDT 24
Peak memory 214276 kb
Host smart-4bc06c2d-8a6a-486b-aba1-67e9ef187ab2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186326770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.4186326770
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3705491042
Short name T983
Test name
Test status
Simulation time 210015557 ps
CPU time 5.73 seconds
Started Mar 10 01:05:08 PM PDT 24
Finished Mar 10 01:05:15 PM PDT 24
Peak memory 209280 kb
Host smart-c88fce68-adda-4cba-ab67-2c16845ad904
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705491042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3705491042
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2467118123
Short name T971
Test name
Test status
Simulation time 64278846 ps
CPU time 1.08 seconds
Started Mar 10 01:05:12 PM PDT 24
Finished Mar 10 01:05:14 PM PDT 24
Peak memory 205828 kb
Host smart-100d0c45-6cff-417c-aeaf-479978a5887a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467118123 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2467118123
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3707709701
Short name T911
Test name
Test status
Simulation time 27517800 ps
CPU time 1.57 seconds
Started Mar 10 01:05:15 PM PDT 24
Finished Mar 10 01:05:17 PM PDT 24
Peak memory 206020 kb
Host smart-30b60b1d-83d6-4179-a266-68d88caacc7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707709701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3707709701
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3345473337
Short name T1064
Test name
Test status
Simulation time 23578481 ps
CPU time 0.9 seconds
Started Mar 10 01:05:15 PM PDT 24
Finished Mar 10 01:05:16 PM PDT 24
Peak memory 205700 kb
Host smart-fa4ea6c8-f693-499f-8be6-61099658b082
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345473337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3345473337
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1825856708
Short name T961
Test name
Test status
Simulation time 127794199 ps
CPU time 2.18 seconds
Started Mar 10 01:05:15 PM PDT 24
Finished Mar 10 01:05:18 PM PDT 24
Peak memory 206004 kb
Host smart-4f5b063a-3932-471f-8189-3660263f5f42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825856708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1825856708
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.4288541837
Short name T118
Test name
Test status
Simulation time 750997446 ps
CPU time 2.41 seconds
Started Mar 10 01:05:11 PM PDT 24
Finished Mar 10 01:05:14 PM PDT 24
Peak memory 214548 kb
Host smart-0945dc42-bef3-4077-9cf1-2b8b35876a33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288541837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.4288541837
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.825011821
Short name T940
Test name
Test status
Simulation time 670095292 ps
CPU time 7.86 seconds
Started Mar 10 01:05:13 PM PDT 24
Finished Mar 10 01:05:21 PM PDT 24
Peak memory 214488 kb
Host smart-62ec524c-67f4-4d6f-8f00-5b08b6d62d0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825011821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.825011821
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.4076461183
Short name T970
Test name
Test status
Simulation time 162731717 ps
CPU time 2.6 seconds
Started Mar 10 01:05:18 PM PDT 24
Finished Mar 10 01:05:21 PM PDT 24
Peak memory 214236 kb
Host smart-75dfc260-2b9c-4e4e-bc5f-d0486f695082
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076461183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.4076461183
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1668861048
Short name T163
Test name
Test status
Simulation time 120262356 ps
CPU time 3.46 seconds
Started Mar 10 01:05:12 PM PDT 24
Finished Mar 10 01:05:15 PM PDT 24
Peak memory 209300 kb
Host smart-41798205-f7d8-4f0f-9b65-63e067736767
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668861048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1668861048
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1713601066
Short name T1027
Test name
Test status
Simulation time 69982461 ps
CPU time 1.6 seconds
Started Mar 10 01:05:13 PM PDT 24
Finished Mar 10 01:05:14 PM PDT 24
Peak memory 214204 kb
Host smart-1911ba70-77a4-4f7e-b7d8-b89522251077
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713601066 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1713601066
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1779663300
Short name T975
Test name
Test status
Simulation time 17518577 ps
CPU time 1.3 seconds
Started Mar 10 01:05:14 PM PDT 24
Finished Mar 10 01:05:15 PM PDT 24
Peak memory 205872 kb
Host smart-f5cbb3e9-b755-4eaa-9507-fdb24fdd1e92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779663300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1779663300
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3105745114
Short name T932
Test name
Test status
Simulation time 72833905 ps
CPU time 0.81 seconds
Started Mar 10 01:05:13 PM PDT 24
Finished Mar 10 01:05:14 PM PDT 24
Peak memory 205592 kb
Host smart-44e483af-8659-4c79-aa1a-b8097df5eb4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105745114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3105745114
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1545962825
Short name T1052
Test name
Test status
Simulation time 20716127 ps
CPU time 1.55 seconds
Started Mar 10 01:05:12 PM PDT 24
Finished Mar 10 01:05:14 PM PDT 24
Peak memory 205968 kb
Host smart-e24cdb51-0d42-49af-bd22-16e41218402e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545962825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1545962825
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1117248059
Short name T1041
Test name
Test status
Simulation time 201808614 ps
CPU time 5.69 seconds
Started Mar 10 01:05:12 PM PDT 24
Finished Mar 10 01:05:18 PM PDT 24
Peak memory 214420 kb
Host smart-c2995b5c-73ac-442f-830e-eee54e87463e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117248059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1117248059
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2440011696
Short name T119
Test name
Test status
Simulation time 681313243 ps
CPU time 7.89 seconds
Started Mar 10 01:05:13 PM PDT 24
Finished Mar 10 01:05:21 PM PDT 24
Peak memory 214520 kb
Host smart-9d70e1e1-95e4-4902-8a51-c20e430bbc65
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440011696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2440011696
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3743576570
Short name T978
Test name
Test status
Simulation time 1465768432 ps
CPU time 3.88 seconds
Started Mar 10 01:05:12 PM PDT 24
Finished Mar 10 01:05:17 PM PDT 24
Peak memory 214164 kb
Host smart-a41371f2-1e4b-4a3a-b35d-d524fb99f1ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743576570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3743576570
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3297697414
Short name T153
Test name
Test status
Simulation time 61281418 ps
CPU time 3.39 seconds
Started Mar 10 01:05:19 PM PDT 24
Finished Mar 10 01:05:23 PM PDT 24
Peak memory 209424 kb
Host smart-337fc37f-52c7-462c-a954-eda3622a8932
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297697414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3297697414
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.4043213568
Short name T1031
Test name
Test status
Simulation time 30903043 ps
CPU time 1.2 seconds
Started Mar 10 01:05:20 PM PDT 24
Finished Mar 10 01:05:22 PM PDT 24
Peak memory 206036 kb
Host smart-620339ec-b059-452d-9a75-57f1056a5b22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043213568 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.4043213568
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.374854599
Short name T1018
Test name
Test status
Simulation time 23519780 ps
CPU time 1.23 seconds
Started Mar 10 01:05:21 PM PDT 24
Finished Mar 10 01:05:25 PM PDT 24
Peak memory 205972 kb
Host smart-fcf5d185-7224-42ab-b5ff-a709b0d5a04c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374854599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.374854599
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1930627517
Short name T1033
Test name
Test status
Simulation time 47452106 ps
CPU time 0.67 seconds
Started Mar 10 01:05:24 PM PDT 24
Finished Mar 10 01:05:27 PM PDT 24
Peak memory 205676 kb
Host smart-5683c4c2-9784-4eab-94df-e67b52bf9a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930627517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1930627517
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1089921658
Short name T998
Test name
Test status
Simulation time 96361042 ps
CPU time 1.62 seconds
Started Mar 10 01:05:18 PM PDT 24
Finished Mar 10 01:05:20 PM PDT 24
Peak memory 205964 kb
Host smart-2c8a6454-f916-44cb-b02b-13693c16a8f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089921658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1089921658
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2637989137
Short name T963
Test name
Test status
Simulation time 562139584 ps
CPU time 3.69 seconds
Started Mar 10 01:05:14 PM PDT 24
Finished Mar 10 01:05:17 PM PDT 24
Peak memory 214532 kb
Host smart-16ed76ff-fa4d-4c6b-b8b2-8ce38e155d25
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637989137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2637989137
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3493294874
Short name T113
Test name
Test status
Simulation time 169925724 ps
CPU time 4.08 seconds
Started Mar 10 01:05:20 PM PDT 24
Finished Mar 10 01:05:24 PM PDT 24
Peak memory 214520 kb
Host smart-a88d322b-4c45-45fc-a856-60f3847534ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493294874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3493294874
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3296139527
Short name T1059
Test name
Test status
Simulation time 74733061 ps
CPU time 2.13 seconds
Started Mar 10 01:05:22 PM PDT 24
Finished Mar 10 01:05:29 PM PDT 24
Peak memory 214212 kb
Host smart-e223a0d5-83e8-46aa-a1d4-3eb1d3b5b0c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296139527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3296139527
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1463271800
Short name T772
Test name
Test status
Simulation time 11601372 ps
CPU time 0.73 seconds
Started Mar 10 02:41:54 PM PDT 24
Finished Mar 10 02:41:54 PM PDT 24
Peak memory 206188 kb
Host smart-ffbd30c8-7c6a-4d9f-9b29-41e6575edeb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463271800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1463271800
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2810455184
Short name T331
Test name
Test status
Simulation time 71933009 ps
CPU time 1.6 seconds
Started Mar 10 02:41:47 PM PDT 24
Finished Mar 10 02:41:49 PM PDT 24
Peak memory 208752 kb
Host smart-8315c839-e5bb-4863-babf-7f7abcb5815c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810455184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2810455184
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1067757142
Short name T94
Test name
Test status
Simulation time 77643828 ps
CPU time 3.91 seconds
Started Mar 10 02:41:53 PM PDT 24
Finished Mar 10 02:41:57 PM PDT 24
Peak memory 220692 kb
Host smart-d5a78d6e-c947-4cc1-80f6-76b403d4015f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067757142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1067757142
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.996248128
Short name T343
Test name
Test status
Simulation time 4415926070 ps
CPU time 37.63 seconds
Started Mar 10 02:41:52 PM PDT 24
Finished Mar 10 02:42:30 PM PDT 24
Peak memory 212912 kb
Host smart-f11ee425-32b7-45c9-b619-40e1984a1a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996248128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.996248128
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1729858449
Short name T49
Test name
Test status
Simulation time 263405835 ps
CPU time 3.05 seconds
Started Mar 10 02:41:48 PM PDT 24
Finished Mar 10 02:41:52 PM PDT 24
Peak memory 216144 kb
Host smart-d3784683-a374-4c65-a2c2-c0333fef7e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729858449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1729858449
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2411954700
Short name T37
Test name
Test status
Simulation time 1522020639 ps
CPU time 5.64 seconds
Started Mar 10 02:41:48 PM PDT 24
Finished Mar 10 02:41:53 PM PDT 24
Peak memory 207396 kb
Host smart-c26d11bf-97cd-4dd9-a3ea-5bc28ebd164f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411954700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2411954700
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3137603222
Short name T391
Test name
Test status
Simulation time 32812683 ps
CPU time 1.93 seconds
Started Mar 10 02:41:44 PM PDT 24
Finished Mar 10 02:41:46 PM PDT 24
Peak memory 207896 kb
Host smart-3477fb43-3061-43ad-afe4-b52c75013d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137603222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3137603222
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3120008484
Short name T782
Test name
Test status
Simulation time 1264927072 ps
CPU time 37.57 seconds
Started Mar 10 02:41:47 PM PDT 24
Finished Mar 10 02:42:25 PM PDT 24
Peak memory 208652 kb
Host smart-b023215e-2a7e-42a3-bc0d-d819c82f6f8f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120008484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3120008484
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1988598468
Short name T745
Test name
Test status
Simulation time 121213255 ps
CPU time 2.35 seconds
Started Mar 10 02:41:48 PM PDT 24
Finished Mar 10 02:41:50 PM PDT 24
Peak memory 206892 kb
Host smart-30d4dfde-a072-4069-bab9-147e5262a84c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988598468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1988598468
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1600095490
Short name T484
Test name
Test status
Simulation time 586492206 ps
CPU time 4.86 seconds
Started Mar 10 02:41:47 PM PDT 24
Finished Mar 10 02:41:53 PM PDT 24
Peak memory 206688 kb
Host smart-82b7fd96-10dc-48b2-ba5a-3151f47633fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600095490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1600095490
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3427194556
Short name T587
Test name
Test status
Simulation time 4402735250 ps
CPU time 8.28 seconds
Started Mar 10 02:41:52 PM PDT 24
Finished Mar 10 02:42:00 PM PDT 24
Peak memory 208732 kb
Host smart-ea1fa5a3-58a6-4db6-abc8-78942ae2c95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427194556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3427194556
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2096503318
Short name T646
Test name
Test status
Simulation time 173349849 ps
CPU time 3.53 seconds
Started Mar 10 02:41:42 PM PDT 24
Finished Mar 10 02:41:46 PM PDT 24
Peak memory 208452 kb
Host smart-51ae9f3e-5ab4-400b-9e2c-dc726edef66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096503318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2096503318
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.243391511
Short name T231
Test name
Test status
Simulation time 366833400 ps
CPU time 18.61 seconds
Started Mar 10 02:41:54 PM PDT 24
Finished Mar 10 02:42:12 PM PDT 24
Peak memory 215036 kb
Host smart-0e769e8b-bc0e-49e9-89d2-5ee1ec339be3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243391511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.243391511
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3824061400
Short name T360
Test name
Test status
Simulation time 311631710 ps
CPU time 5.4 seconds
Started Mar 10 02:41:54 PM PDT 24
Finished Mar 10 02:41:59 PM PDT 24
Peak memory 209164 kb
Host smart-b0cf36a5-89ad-4337-b16a-c9c0141522c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824061400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3824061400
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2679170137
Short name T803
Test name
Test status
Simulation time 16319850 ps
CPU time 0.77 seconds
Started Mar 10 02:42:07 PM PDT 24
Finished Mar 10 02:42:08 PM PDT 24
Peak memory 206136 kb
Host smart-b4dee154-9dba-4b86-857a-c64fc31180c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679170137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2679170137
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1746182587
Short name T450
Test name
Test status
Simulation time 436305259 ps
CPU time 5.33 seconds
Started Mar 10 02:42:01 PM PDT 24
Finished Mar 10 02:42:07 PM PDT 24
Peak memory 214772 kb
Host smart-8ac9d1fd-fe25-4035-8824-efbcd8e29126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746182587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1746182587
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.172163365
Short name T67
Test name
Test status
Simulation time 20702338 ps
CPU time 1.69 seconds
Started Mar 10 02:41:57 PM PDT 24
Finished Mar 10 02:41:59 PM PDT 24
Peak memory 210044 kb
Host smart-9f1d897e-38c0-4e4d-8b94-7a7d965e4f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172163365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.172163365
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2959171326
Short name T749
Test name
Test status
Simulation time 359919728 ps
CPU time 4.38 seconds
Started Mar 10 02:42:01 PM PDT 24
Finished Mar 10 02:42:06 PM PDT 24
Peak memory 209608 kb
Host smart-a61a2745-74d4-43fb-be8f-7e728ecd8438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959171326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2959171326
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2426876063
Short name T373
Test name
Test status
Simulation time 118340495 ps
CPU time 3.98 seconds
Started Mar 10 02:42:03 PM PDT 24
Finished Mar 10 02:42:07 PM PDT 24
Peak memory 222604 kb
Host smart-d3adbdd5-e66e-4ca0-a7d3-98eafc1c645a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426876063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2426876063
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_random.2654108705
Short name T699
Test name
Test status
Simulation time 408621103 ps
CPU time 3.22 seconds
Started Mar 10 02:41:58 PM PDT 24
Finished Mar 10 02:42:01 PM PDT 24
Peak memory 207324 kb
Host smart-1dfebead-5415-4b4e-a6af-630e46108a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654108705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2654108705
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.4104532970
Short name T339
Test name
Test status
Simulation time 53031632 ps
CPU time 2.63 seconds
Started Mar 10 02:41:56 PM PDT 24
Finished Mar 10 02:41:59 PM PDT 24
Peak memory 207112 kb
Host smart-595c84a1-9954-441d-ba18-74b100ed44c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104532970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.4104532970
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1833060882
Short name T488
Test name
Test status
Simulation time 67765428 ps
CPU time 2.31 seconds
Started Mar 10 02:41:58 PM PDT 24
Finished Mar 10 02:42:00 PM PDT 24
Peak memory 206800 kb
Host smart-8b528f14-da2d-4c2d-abce-5e2da7c8c564
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833060882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1833060882
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3165342940
Short name T443
Test name
Test status
Simulation time 138808061 ps
CPU time 4.44 seconds
Started Mar 10 02:41:58 PM PDT 24
Finished Mar 10 02:42:03 PM PDT 24
Peak memory 208508 kb
Host smart-071d583d-4a42-4f94-b0e9-e0fa22aebdb4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165342940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3165342940
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3698785457
Short name T527
Test name
Test status
Simulation time 51323341 ps
CPU time 3.09 seconds
Started Mar 10 02:41:57 PM PDT 24
Finished Mar 10 02:42:00 PM PDT 24
Peak memory 208460 kb
Host smart-1e54f747-42fd-40f4-9097-19e0c33b88e5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698785457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3698785457
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1275358838
Short name T481
Test name
Test status
Simulation time 130749626 ps
CPU time 1.85 seconds
Started Mar 10 02:42:02 PM PDT 24
Finished Mar 10 02:42:04 PM PDT 24
Peak memory 209284 kb
Host smart-8603c238-f7e3-47b3-bb83-167382ff9714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275358838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1275358838
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3919304579
Short name T131
Test name
Test status
Simulation time 55598403 ps
CPU time 2.97 seconds
Started Mar 10 02:41:58 PM PDT 24
Finished Mar 10 02:42:01 PM PDT 24
Peak memory 206788 kb
Host smart-17907dc9-87b2-4509-9937-b4cab0d02a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919304579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3919304579
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.765704023
Short name T260
Test name
Test status
Simulation time 2032557854 ps
CPU time 66.03 seconds
Started Mar 10 02:42:02 PM PDT 24
Finished Mar 10 02:43:08 PM PDT 24
Peak memory 217168 kb
Host smart-acb97c70-acd9-48e6-829e-d10294561742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765704023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.765704023
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1324822061
Short name T297
Test name
Test status
Simulation time 332787089 ps
CPU time 12.06 seconds
Started Mar 10 02:42:02 PM PDT 24
Finished Mar 10 02:42:14 PM PDT 24
Peak memory 214548 kb
Host smart-3de93626-af72-4080-b7b4-ded8c773f388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324822061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1324822061
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2354878678
Short name T867
Test name
Test status
Simulation time 120599165 ps
CPU time 2.23 seconds
Started Mar 10 02:42:04 PM PDT 24
Finished Mar 10 02:42:06 PM PDT 24
Peak memory 210008 kb
Host smart-79aef7d1-e9d2-437c-88e0-9b374b213415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354878678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2354878678
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.4204353293
Short name T563
Test name
Test status
Simulation time 24805366 ps
CPU time 0.79 seconds
Started Mar 10 02:43:13 PM PDT 24
Finished Mar 10 02:43:14 PM PDT 24
Peak memory 206028 kb
Host smart-376397a5-6620-4ac8-bf76-84186a4971a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204353293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.4204353293
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3175834696
Short name T18
Test name
Test status
Simulation time 192515655 ps
CPU time 4.49 seconds
Started Mar 10 02:43:10 PM PDT 24
Finished Mar 10 02:43:14 PM PDT 24
Peak memory 222972 kb
Host smart-68850e96-2b32-460b-be43-770c576ca5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175834696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3175834696
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3953549993
Short name T68
Test name
Test status
Simulation time 128747745 ps
CPU time 2.51 seconds
Started Mar 10 02:43:07 PM PDT 24
Finished Mar 10 02:43:10 PM PDT 24
Peak memory 208348 kb
Host smart-2b4248ba-f3bd-48a4-a99c-82f2125e3bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953549993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3953549993
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1543288188
Short name T21
Test name
Test status
Simulation time 114803997 ps
CPU time 5.04 seconds
Started Mar 10 02:43:07 PM PDT 24
Finished Mar 10 02:43:12 PM PDT 24
Peak memory 214520 kb
Host smart-12c368a7-6bda-4164-ad57-a5e8d9ae992a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543288188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1543288188
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2376611221
Short name T225
Test name
Test status
Simulation time 176769507 ps
CPU time 1.82 seconds
Started Mar 10 02:43:08 PM PDT 24
Finished Mar 10 02:43:10 PM PDT 24
Peak memory 207692 kb
Host smart-8ded74d7-16b5-4c4b-b308-5fb5f5058f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376611221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2376611221
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3473562541
Short name T321
Test name
Test status
Simulation time 406549099 ps
CPU time 4.22 seconds
Started Mar 10 02:43:10 PM PDT 24
Finished Mar 10 02:43:15 PM PDT 24
Peak memory 214464 kb
Host smart-ad5d5120-2019-4053-a855-a2247f14a3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473562541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3473562541
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3838303424
Short name T480
Test name
Test status
Simulation time 2577076312 ps
CPU time 16.93 seconds
Started Mar 10 02:43:11 PM PDT 24
Finished Mar 10 02:43:28 PM PDT 24
Peak memory 208144 kb
Host smart-b353b4d5-726c-41c6-ba7c-6c2e89e99c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838303424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3838303424
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.312698848
Short name T448
Test name
Test status
Simulation time 78253090 ps
CPU time 1.87 seconds
Started Mar 10 02:43:09 PM PDT 24
Finished Mar 10 02:43:11 PM PDT 24
Peak memory 206704 kb
Host smart-d48dffba-7f87-43a3-b763-c353bcaa53c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312698848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.312698848
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2174617146
Short name T601
Test name
Test status
Simulation time 36671759 ps
CPU time 2.48 seconds
Started Mar 10 02:43:10 PM PDT 24
Finished Mar 10 02:43:13 PM PDT 24
Peak memory 206732 kb
Host smart-f89839e2-7c3b-4378-a932-45d1b993326c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174617146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2174617146
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2458385781
Short name T670
Test name
Test status
Simulation time 1583753880 ps
CPU time 33.43 seconds
Started Mar 10 02:43:07 PM PDT 24
Finished Mar 10 02:43:41 PM PDT 24
Peak memory 208792 kb
Host smart-17889940-362a-4a00-8235-1bea7dd7b73e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458385781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2458385781
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3257808229
Short name T302
Test name
Test status
Simulation time 1166778366 ps
CPU time 11.97 seconds
Started Mar 10 02:43:09 PM PDT 24
Finished Mar 10 02:43:21 PM PDT 24
Peak memory 209300 kb
Host smart-ff473b5e-3f3e-45f1-bf6e-b274bcab0d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257808229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3257808229
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1552731738
Short name T470
Test name
Test status
Simulation time 20815583 ps
CPU time 1.78 seconds
Started Mar 10 02:43:10 PM PDT 24
Finished Mar 10 02:43:11 PM PDT 24
Peak memory 207212 kb
Host smart-61744afe-ab4c-4582-af45-4c980fe37e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552731738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1552731738
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.3858822127
Short name T124
Test name
Test status
Simulation time 101522503 ps
CPU time 4.73 seconds
Started Mar 10 02:43:09 PM PDT 24
Finished Mar 10 02:43:14 PM PDT 24
Peak memory 218984 kb
Host smart-dd3d7a6f-646d-438b-94d3-e9a294dcbecf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858822127 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.3858822127
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2970122461
Short name T627
Test name
Test status
Simulation time 1022458628 ps
CPU time 7.74 seconds
Started Mar 10 02:43:09 PM PDT 24
Finished Mar 10 02:43:16 PM PDT 24
Peak memory 209716 kb
Host smart-4d995d9b-c2e7-498e-bd01-e9f625a20525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970122461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2970122461
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2971016361
Short name T797
Test name
Test status
Simulation time 2974671694 ps
CPU time 15.77 seconds
Started Mar 10 02:43:07 PM PDT 24
Finished Mar 10 02:43:23 PM PDT 24
Peak memory 211240 kb
Host smart-7e3a4a36-c9e8-41a7-a1d5-068b84a581b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971016361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2971016361
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.345632507
Short name T828
Test name
Test status
Simulation time 272392838 ps
CPU time 5.39 seconds
Started Mar 10 02:43:12 PM PDT 24
Finished Mar 10 02:43:18 PM PDT 24
Peak memory 208264 kb
Host smart-7d09f9f0-7afb-4286-815d-d0f2bce71b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345632507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.345632507
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1858064404
Short name T839
Test name
Test status
Simulation time 135652192 ps
CPU time 5.99 seconds
Started Mar 10 02:43:13 PM PDT 24
Finished Mar 10 02:43:19 PM PDT 24
Peak memory 209220 kb
Host smart-3da62ecb-856a-44c5-a64c-fe8fd3803d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858064404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1858064404
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3344625908
Short name T374
Test name
Test status
Simulation time 467867239 ps
CPU time 6.14 seconds
Started Mar 10 02:43:18 PM PDT 24
Finished Mar 10 02:43:24 PM PDT 24
Peak memory 210884 kb
Host smart-d1d1b88e-7d97-4084-a60d-5882de562a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344625908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3344625908
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2897976021
Short name T41
Test name
Test status
Simulation time 94173418 ps
CPU time 3.25 seconds
Started Mar 10 02:43:11 PM PDT 24
Finished Mar 10 02:43:14 PM PDT 24
Peak memory 214392 kb
Host smart-4a653b4f-a484-4edf-a737-62a944599676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897976021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2897976021
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2144847588
Short name T562
Test name
Test status
Simulation time 2239723860 ps
CPU time 57.74 seconds
Started Mar 10 02:43:12 PM PDT 24
Finished Mar 10 02:44:10 PM PDT 24
Peak memory 214484 kb
Host smart-9b99dcc8-7877-46f9-bd68-16318f12f938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144847588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2144847588
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3183346259
Short name T662
Test name
Test status
Simulation time 172559322 ps
CPU time 4.21 seconds
Started Mar 10 02:43:15 PM PDT 24
Finished Mar 10 02:43:19 PM PDT 24
Peak memory 208420 kb
Host smart-53d1708f-8794-4fa6-99f0-38455b6ece86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183346259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3183346259
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.234224605
Short name T355
Test name
Test status
Simulation time 293439697 ps
CPU time 2.19 seconds
Started Mar 10 02:43:15 PM PDT 24
Finished Mar 10 02:43:17 PM PDT 24
Peak memory 208944 kb
Host smart-9d69adcf-a759-4484-a0e5-6c06759b7209
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234224605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.234224605
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.151112935
Short name T830
Test name
Test status
Simulation time 2024507461 ps
CPU time 7.01 seconds
Started Mar 10 02:43:12 PM PDT 24
Finished Mar 10 02:43:19 PM PDT 24
Peak memory 208424 kb
Host smart-6966cc2f-01c0-46f3-aa5c-160b46e85095
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151112935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.151112935
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2876056297
Short name T564
Test name
Test status
Simulation time 237304960 ps
CPU time 3.27 seconds
Started Mar 10 02:43:13 PM PDT 24
Finished Mar 10 02:43:17 PM PDT 24
Peak memory 206864 kb
Host smart-2c6e627f-d05d-45ae-8829-713f19b547cf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876056297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2876056297
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2396640609
Short name T439
Test name
Test status
Simulation time 56690444 ps
CPU time 2.43 seconds
Started Mar 10 02:43:17 PM PDT 24
Finished Mar 10 02:43:19 PM PDT 24
Peak memory 209156 kb
Host smart-aa07d77d-85c3-4bc3-9f3c-b016511572dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396640609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2396640609
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2807348743
Short name T862
Test name
Test status
Simulation time 341573830 ps
CPU time 2.64 seconds
Started Mar 10 02:43:12 PM PDT 24
Finished Mar 10 02:43:15 PM PDT 24
Peak memory 206744 kb
Host smart-70238f31-99e4-437d-bd9d-1727d1a0d44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807348743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2807348743
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1361826089
Short name T886
Test name
Test status
Simulation time 508432520 ps
CPU time 8.28 seconds
Started Mar 10 02:43:18 PM PDT 24
Finished Mar 10 02:43:26 PM PDT 24
Peak memory 214908 kb
Host smart-27320e1e-8df6-4907-8331-a55d6f920f2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361826089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1361826089
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1236404645
Short name T363
Test name
Test status
Simulation time 107713061 ps
CPU time 4.05 seconds
Started Mar 10 02:43:14 PM PDT 24
Finished Mar 10 02:43:19 PM PDT 24
Peak memory 209292 kb
Host smart-9f1809a7-0d50-46e4-9414-44e3bc3a3841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236404645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1236404645
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.4141379694
Short name T147
Test name
Test status
Simulation time 624448770 ps
CPU time 4.66 seconds
Started Mar 10 02:43:22 PM PDT 24
Finished Mar 10 02:43:26 PM PDT 24
Peak memory 210856 kb
Host smart-3fd03ebd-e02c-46d2-a770-5d721dda30c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141379694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.4141379694
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.897284764
Short name T787
Test name
Test status
Simulation time 12728204 ps
CPU time 0.72 seconds
Started Mar 10 02:43:22 PM PDT 24
Finished Mar 10 02:43:23 PM PDT 24
Peak memory 206156 kb
Host smart-74c43356-2337-4441-af30-84ef63a5b921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897284764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.897284764
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.829483007
Short name T366
Test name
Test status
Simulation time 3078175813 ps
CPU time 170.42 seconds
Started Mar 10 02:43:23 PM PDT 24
Finished Mar 10 02:46:14 PM PDT 24
Peak memory 215924 kb
Host smart-c33770ac-3e27-42bf-90d8-f0259550f6f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829483007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.829483007
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.4155470431
Short name T813
Test name
Test status
Simulation time 244652018 ps
CPU time 4.31 seconds
Started Mar 10 02:43:28 PM PDT 24
Finished Mar 10 02:43:33 PM PDT 24
Peak memory 222952 kb
Host smart-3d18f19e-0bea-436d-814a-5cf03b00e5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155470431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.4155470431
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.4000655664
Short name T843
Test name
Test status
Simulation time 147177061 ps
CPU time 4.07 seconds
Started Mar 10 02:43:21 PM PDT 24
Finished Mar 10 02:43:25 PM PDT 24
Peak memory 208136 kb
Host smart-2a387da8-456b-4987-935f-d70f40c30fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000655664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.4000655664
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.193503023
Short name T531
Test name
Test status
Simulation time 1038928999 ps
CPU time 7.12 seconds
Started Mar 10 02:43:21 PM PDT 24
Finished Mar 10 02:43:28 PM PDT 24
Peak memory 209692 kb
Host smart-3f048383-e6c3-46e0-a625-2461e1fc01b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193503023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.193503023
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.192228254
Short name T742
Test name
Test status
Simulation time 152257332 ps
CPU time 8.06 seconds
Started Mar 10 02:43:21 PM PDT 24
Finished Mar 10 02:43:30 PM PDT 24
Peak memory 222608 kb
Host smart-71a6fa62-5262-480d-9cff-f58e99f2e97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192228254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.192228254
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.553156814
Short name T361
Test name
Test status
Simulation time 1721200979 ps
CPU time 22.52 seconds
Started Mar 10 02:43:24 PM PDT 24
Finished Mar 10 02:43:46 PM PDT 24
Peak memory 208884 kb
Host smart-fc540f56-41ee-45a9-8f47-4d4edf54f356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553156814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.553156814
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3211997707
Short name T752
Test name
Test status
Simulation time 553460743 ps
CPU time 6.27 seconds
Started Mar 10 02:43:17 PM PDT 24
Finished Mar 10 02:43:24 PM PDT 24
Peak memory 208680 kb
Host smart-efc44d64-4c0d-4b34-b360-ddd57c0360b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211997707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3211997707
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.4278014661
Short name T731
Test name
Test status
Simulation time 327104434 ps
CPU time 4.53 seconds
Started Mar 10 02:43:21 PM PDT 24
Finished Mar 10 02:43:26 PM PDT 24
Peak memory 206872 kb
Host smart-bc240bcf-4eec-4196-815f-92fcb1b742c6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278014661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.4278014661
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.4120674048
Short name T597
Test name
Test status
Simulation time 61197837 ps
CPU time 3.08 seconds
Started Mar 10 02:43:19 PM PDT 24
Finished Mar 10 02:43:23 PM PDT 24
Peak memory 208660 kb
Host smart-b8f2f47e-23af-4543-a137-12f4fa4b949a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120674048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.4120674048
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2288319730
Short name T274
Test name
Test status
Simulation time 421588801 ps
CPU time 4.86 seconds
Started Mar 10 02:43:22 PM PDT 24
Finished Mar 10 02:43:27 PM PDT 24
Peak memory 218468 kb
Host smart-4bbc7eb2-3d76-44b9-8a5f-5b0613fc39e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288319730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2288319730
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.329695308
Short name T686
Test name
Test status
Simulation time 43483681 ps
CPU time 2.75 seconds
Started Mar 10 02:43:18 PM PDT 24
Finished Mar 10 02:43:21 PM PDT 24
Peak memory 208688 kb
Host smart-b3fd7cab-8522-4c26-88da-e12db58e0a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329695308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.329695308
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.472245870
Short name T125
Test name
Test status
Simulation time 210186417 ps
CPU time 8.22 seconds
Started Mar 10 02:43:23 PM PDT 24
Finished Mar 10 02:43:32 PM PDT 24
Peak memory 222868 kb
Host smart-cbcd66bb-64f7-4ba0-9f58-a6b9f7046fef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472245870 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.472245870
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3346722156
Short name T827
Test name
Test status
Simulation time 536459654 ps
CPU time 4.56 seconds
Started Mar 10 02:43:21 PM PDT 24
Finished Mar 10 02:43:26 PM PDT 24
Peak memory 209028 kb
Host smart-2ad7184e-c182-4825-8a8a-87e47f7c0a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346722156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3346722156
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.795662413
Short name T808
Test name
Test status
Simulation time 15214932 ps
CPU time 0.79 seconds
Started Mar 10 02:43:27 PM PDT 24
Finished Mar 10 02:43:28 PM PDT 24
Peak memory 206096 kb
Host smart-b6bfae0f-163b-4045-890e-524ff46aaf31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795662413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.795662413
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2728795826
Short name T414
Test name
Test status
Simulation time 220758702 ps
CPU time 11.39 seconds
Started Mar 10 02:43:27 PM PDT 24
Finished Mar 10 02:43:38 PM PDT 24
Peak memory 214464 kb
Host smart-925870c0-5eef-4d28-b6d7-d344d5b8bd0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2728795826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2728795826
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2908777459
Short name T715
Test name
Test status
Simulation time 115437710 ps
CPU time 4.05 seconds
Started Mar 10 02:43:27 PM PDT 24
Finished Mar 10 02:43:32 PM PDT 24
Peak memory 210180 kb
Host smart-485fc0df-25ba-43c8-961b-64080c1d5988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908777459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2908777459
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2575208023
Short name T345
Test name
Test status
Simulation time 115656117 ps
CPU time 5.03 seconds
Started Mar 10 02:43:27 PM PDT 24
Finished Mar 10 02:43:32 PM PDT 24
Peak memory 220752 kb
Host smart-75458ce5-783e-4db0-bd20-085e758b8141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575208023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2575208023
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.860797294
Short name T279
Test name
Test status
Simulation time 84159747 ps
CPU time 3.99 seconds
Started Mar 10 02:43:26 PM PDT 24
Finished Mar 10 02:43:30 PM PDT 24
Peak memory 220768 kb
Host smart-b0db96fc-9cb3-4981-86de-e9ab51d28065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860797294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.860797294
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3321867432
Short name T353
Test name
Test status
Simulation time 260305503 ps
CPU time 7.79 seconds
Started Mar 10 02:43:29 PM PDT 24
Finished Mar 10 02:43:37 PM PDT 24
Peak memory 208268 kb
Host smart-0834ea1b-90d9-4758-b1a2-948c72c179fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321867432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3321867432
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2605622172
Short name T786
Test name
Test status
Simulation time 489286860 ps
CPU time 11.93 seconds
Started Mar 10 02:43:21 PM PDT 24
Finished Mar 10 02:43:33 PM PDT 24
Peak memory 208068 kb
Host smart-f2587255-ff90-44a3-8531-cfb9662b468b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605622172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2605622172
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1616448297
Short name T702
Test name
Test status
Simulation time 4036131574 ps
CPU time 24.27 seconds
Started Mar 10 02:43:28 PM PDT 24
Finished Mar 10 02:43:53 PM PDT 24
Peak memory 208636 kb
Host smart-08140d9c-ed28-4b9e-94ba-ceb648d30b77
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616448297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1616448297
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3470556342
Short name T603
Test name
Test status
Simulation time 407055365 ps
CPU time 6.28 seconds
Started Mar 10 02:43:23 PM PDT 24
Finished Mar 10 02:43:29 PM PDT 24
Peak memory 207892 kb
Host smart-76faeed2-fe08-4eb3-b5b6-bf9d6e531079
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470556342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3470556342
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1945555027
Short name T853
Test name
Test status
Simulation time 213058183 ps
CPU time 4.71 seconds
Started Mar 10 02:43:28 PM PDT 24
Finished Mar 10 02:43:32 PM PDT 24
Peak memory 208240 kb
Host smart-a6d4fc58-53e6-405f-b0d3-c5f7f4e18658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945555027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1945555027
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1983188807
Short name T898
Test name
Test status
Simulation time 49906927 ps
CPU time 2.58 seconds
Started Mar 10 02:43:22 PM PDT 24
Finished Mar 10 02:43:25 PM PDT 24
Peak memory 208452 kb
Host smart-ad43ae84-d6e9-432b-bce9-5e01c8758249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983188807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1983188807
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1355974843
Short name T70
Test name
Test status
Simulation time 266779303 ps
CPU time 10.08 seconds
Started Mar 10 02:43:27 PM PDT 24
Finished Mar 10 02:43:37 PM PDT 24
Peak memory 222856 kb
Host smart-fc33e4a5-22a4-4b0b-8cdf-77fe4b3fa27f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355974843 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1355974843
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.716337520
Short name T758
Test name
Test status
Simulation time 115598717 ps
CPU time 3.1 seconds
Started Mar 10 02:43:27 PM PDT 24
Finished Mar 10 02:43:30 PM PDT 24
Peak memory 207676 kb
Host smart-06a549c8-3367-4fe5-98fd-62d77b07d273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716337520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.716337520
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2122965240
Short name T543
Test name
Test status
Simulation time 1609984586 ps
CPU time 10.57 seconds
Started Mar 10 02:43:25 PM PDT 24
Finished Mar 10 02:43:36 PM PDT 24
Peak memory 210492 kb
Host smart-3f1da36b-3641-4d1b-8a0d-cdb0a73a51aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122965240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2122965240
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.699960907
Short name T491
Test name
Test status
Simulation time 43394602 ps
CPU time 0.79 seconds
Started Mar 10 02:43:31 PM PDT 24
Finished Mar 10 02:43:32 PM PDT 24
Peak memory 206108 kb
Host smart-fdf5b166-0778-496e-be9b-1c339794ebd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699960907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.699960907
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.996640702
Short name T767
Test name
Test status
Simulation time 359267537 ps
CPU time 10.86 seconds
Started Mar 10 02:43:33 PM PDT 24
Finished Mar 10 02:43:44 PM PDT 24
Peak memory 214428 kb
Host smart-4e265f7e-fac5-4354-8b14-9a22a2ab886e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996640702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.996640702
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3390077658
Short name T452
Test name
Test status
Simulation time 82295453 ps
CPU time 2.59 seconds
Started Mar 10 02:43:35 PM PDT 24
Finished Mar 10 02:43:37 PM PDT 24
Peak memory 206928 kb
Host smart-b3cd5922-6f69-4856-90d6-f784717597a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390077658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3390077658
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1984093069
Short name T350
Test name
Test status
Simulation time 734994334 ps
CPU time 6.19 seconds
Started Mar 10 02:43:32 PM PDT 24
Finished Mar 10 02:43:38 PM PDT 24
Peak memory 220784 kb
Host smart-75bb4f7d-4fb7-44f2-9a6c-f17728180eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984093069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1984093069
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3454786200
Short name T78
Test name
Test status
Simulation time 142391802 ps
CPU time 4.04 seconds
Started Mar 10 02:43:33 PM PDT 24
Finished Mar 10 02:43:37 PM PDT 24
Peak memory 210576 kb
Host smart-9bb59a26-71b0-4ada-a6d4-796fc0127141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454786200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3454786200
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1724934826
Short name T432
Test name
Test status
Simulation time 66614370 ps
CPU time 2.71 seconds
Started Mar 10 02:43:32 PM PDT 24
Finished Mar 10 02:43:35 PM PDT 24
Peak memory 219192 kb
Host smart-63f4d731-42f5-41d3-9e21-5f3768aece44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724934826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1724934826
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1366058662
Short name T785
Test name
Test status
Simulation time 893775771 ps
CPU time 23.53 seconds
Started Mar 10 02:43:27 PM PDT 24
Finished Mar 10 02:43:50 PM PDT 24
Peak memory 208324 kb
Host smart-645c1a36-8f2a-4f06-bd12-5e1b59681247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366058662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1366058662
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1510063339
Short name T322
Test name
Test status
Simulation time 41020798 ps
CPU time 2.65 seconds
Started Mar 10 02:43:27 PM PDT 24
Finished Mar 10 02:43:30 PM PDT 24
Peak memory 208760 kb
Host smart-d4231d87-be0a-420f-b9da-5c5c84c6909f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510063339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1510063339
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.520375292
Short name T632
Test name
Test status
Simulation time 647162051 ps
CPU time 26.04 seconds
Started Mar 10 02:43:28 PM PDT 24
Finished Mar 10 02:43:54 PM PDT 24
Peak memory 209060 kb
Host smart-bd518e9a-c524-49c4-9629-1c9af876c8ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520375292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.520375292
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2233971483
Short name T557
Test name
Test status
Simulation time 294173366 ps
CPU time 4.06 seconds
Started Mar 10 02:43:28 PM PDT 24
Finished Mar 10 02:43:32 PM PDT 24
Peak memory 206856 kb
Host smart-f29b12ad-19ca-40ae-8477-f58abdc01638
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233971483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2233971483
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2442795953
Short name T446
Test name
Test status
Simulation time 718995980 ps
CPU time 7.07 seconds
Started Mar 10 02:43:30 PM PDT 24
Finished Mar 10 02:43:37 PM PDT 24
Peak memory 209420 kb
Host smart-b7890f35-e16b-4326-a316-32580e4f873a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442795953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2442795953
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.296829965
Short name T426
Test name
Test status
Simulation time 23744447 ps
CPU time 1.99 seconds
Started Mar 10 02:43:25 PM PDT 24
Finished Mar 10 02:43:27 PM PDT 24
Peak memory 208528 kb
Host smart-1e22de61-8379-4e81-bf5e-3038fcad3861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296829965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.296829965
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1844236552
Short name T897
Test name
Test status
Simulation time 921651432 ps
CPU time 38.17 seconds
Started Mar 10 02:43:33 PM PDT 24
Finished Mar 10 02:44:11 PM PDT 24
Peak memory 222648 kb
Host smart-ff80fa06-7233-45fa-984f-afee9dad8245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844236552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1844236552
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3155755891
Short name T486
Test name
Test status
Simulation time 289108984 ps
CPU time 8.21 seconds
Started Mar 10 02:43:32 PM PDT 24
Finished Mar 10 02:43:40 PM PDT 24
Peak memory 208368 kb
Host smart-3af171a8-6977-4575-b804-1d78de2776d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155755891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3155755891
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1497560074
Short name T594
Test name
Test status
Simulation time 314823031 ps
CPU time 2.52 seconds
Started Mar 10 02:43:31 PM PDT 24
Finished Mar 10 02:43:34 PM PDT 24
Peak memory 210156 kb
Host smart-2e608632-c0d9-4551-8e00-30daf157fb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497560074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1497560074
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1122003341
Short name T574
Test name
Test status
Simulation time 12555684 ps
CPU time 0.74 seconds
Started Mar 10 02:43:36 PM PDT 24
Finished Mar 10 02:43:37 PM PDT 24
Peak memory 206172 kb
Host smart-4c60b965-f446-4393-9f55-6e7dbd826f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122003341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1122003341
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3421492328
Short name T888
Test name
Test status
Simulation time 33823429 ps
CPU time 2.61 seconds
Started Mar 10 02:43:31 PM PDT 24
Finished Mar 10 02:43:34 PM PDT 24
Peak memory 214324 kb
Host smart-eb7cbaf6-440a-4e0d-bee5-f86959853412
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3421492328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3421492328
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.4033074332
Short name T26
Test name
Test status
Simulation time 192405845 ps
CPU time 3.76 seconds
Started Mar 10 02:43:38 PM PDT 24
Finished Mar 10 02:43:42 PM PDT 24
Peak memory 221792 kb
Host smart-3bbb4ddf-a5ba-4b3e-a590-0dd1e58205cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033074332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.4033074332
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1422019050
Short name T649
Test name
Test status
Simulation time 298560943 ps
CPU time 2.82 seconds
Started Mar 10 02:43:33 PM PDT 24
Finished Mar 10 02:43:36 PM PDT 24
Peak memory 208288 kb
Host smart-f33e80e0-cc65-4b11-83a9-b6b8ae3c1748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422019050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1422019050
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.663778549
Short name T271
Test name
Test status
Simulation time 360481935 ps
CPU time 11.12 seconds
Started Mar 10 02:43:38 PM PDT 24
Finished Mar 10 02:43:49 PM PDT 24
Peak memory 222524 kb
Host smart-e8d10c98-c839-4ed5-a503-c70e7ddd9d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663778549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.663778549
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.819367795
Short name T806
Test name
Test status
Simulation time 51354567 ps
CPU time 2.48 seconds
Started Mar 10 02:43:33 PM PDT 24
Finished Mar 10 02:43:35 PM PDT 24
Peak memory 208876 kb
Host smart-87756daa-8e4d-4a05-862b-480299f8eb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819367795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.819367795
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2576254727
Short name T295
Test name
Test status
Simulation time 387965486 ps
CPU time 5.17 seconds
Started Mar 10 02:43:31 PM PDT 24
Finished Mar 10 02:43:36 PM PDT 24
Peak memory 208188 kb
Host smart-4f8c9f99-db1e-4e60-986c-7619f9c042ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576254727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2576254727
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.610778856
Short name T889
Test name
Test status
Simulation time 676216332 ps
CPU time 4.3 seconds
Started Mar 10 02:43:33 PM PDT 24
Finished Mar 10 02:43:37 PM PDT 24
Peak memory 208816 kb
Host smart-43856c1d-c91e-4c9c-a3e3-11a19d2c4bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610778856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.610778856
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3491331776
Short name T807
Test name
Test status
Simulation time 509964907 ps
CPU time 3.17 seconds
Started Mar 10 02:43:32 PM PDT 24
Finished Mar 10 02:43:35 PM PDT 24
Peak memory 206888 kb
Host smart-b8140c68-3383-497b-bf3d-81d524aaca34
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491331776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3491331776
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.478220146
Short name T266
Test name
Test status
Simulation time 158279305 ps
CPU time 4.5 seconds
Started Mar 10 02:43:32 PM PDT 24
Finished Mar 10 02:43:37 PM PDT 24
Peak memory 207864 kb
Host smart-823f4ec6-d56c-48e6-ab3d-46c39b476aa8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478220146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.478220146
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.133863604
Short name T478
Test name
Test status
Simulation time 97987369 ps
CPU time 2.97 seconds
Started Mar 10 02:43:35 PM PDT 24
Finished Mar 10 02:43:38 PM PDT 24
Peak memory 207924 kb
Host smart-cae5f92d-c37c-4c17-acd8-51752a371c8c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133863604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.133863604
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3940974457
Short name T207
Test name
Test status
Simulation time 198159508 ps
CPU time 2.58 seconds
Started Mar 10 02:43:37 PM PDT 24
Finished Mar 10 02:43:39 PM PDT 24
Peak memory 209384 kb
Host smart-5573f111-93d8-4304-b0ff-2b745c6fd2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940974457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3940974457
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2912665711
Short name T791
Test name
Test status
Simulation time 71213211 ps
CPU time 2.35 seconds
Started Mar 10 02:43:30 PM PDT 24
Finished Mar 10 02:43:32 PM PDT 24
Peak memory 208360 kb
Host smart-3044ed0a-336a-40cd-9de3-968518e78c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912665711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2912665711
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1466220329
Short name T881
Test name
Test status
Simulation time 70755110 ps
CPU time 4.35 seconds
Started Mar 10 02:43:34 PM PDT 24
Finished Mar 10 02:43:38 PM PDT 24
Peak memory 210088 kb
Host smart-6f373d2e-f6a5-42ae-a0fb-ef18ba2a70df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466220329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1466220329
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3084398234
Short name T799
Test name
Test status
Simulation time 50211257 ps
CPU time 1.35 seconds
Started Mar 10 02:43:37 PM PDT 24
Finished Mar 10 02:43:38 PM PDT 24
Peak memory 209824 kb
Host smart-17c25d54-f2ef-4356-a3e3-85e38367f78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084398234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3084398234
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1495555746
Short name T795
Test name
Test status
Simulation time 41005648 ps
CPU time 0.88 seconds
Started Mar 10 02:43:43 PM PDT 24
Finished Mar 10 02:43:44 PM PDT 24
Peak memory 206176 kb
Host smart-6155be9d-23a0-46d2-b045-fe2961f49ac4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495555746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1495555746
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.315933197
Short name T246
Test name
Test status
Simulation time 103496715 ps
CPU time 2.42 seconds
Started Mar 10 02:43:43 PM PDT 24
Finished Mar 10 02:43:45 PM PDT 24
Peak memory 214512 kb
Host smart-a702e71a-91c9-4b50-b89f-5eb24072ff53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=315933197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.315933197
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1266083793
Short name T766
Test name
Test status
Simulation time 118260602 ps
CPU time 1.56 seconds
Started Mar 10 02:43:45 PM PDT 24
Finished Mar 10 02:43:48 PM PDT 24
Peak memory 219940 kb
Host smart-2396e788-1db9-4e83-bb29-63f266463a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266083793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1266083793
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.147974830
Short name T716
Test name
Test status
Simulation time 55326981 ps
CPU time 2.98 seconds
Started Mar 10 02:43:42 PM PDT 24
Finished Mar 10 02:43:45 PM PDT 24
Peak memory 208700 kb
Host smart-95da10af-96c1-4e85-8f1f-952e67c1ae1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147974830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.147974830
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2946138952
Short name T748
Test name
Test status
Simulation time 300386672 ps
CPU time 4.24 seconds
Started Mar 10 02:43:42 PM PDT 24
Finished Mar 10 02:43:47 PM PDT 24
Peak memory 209828 kb
Host smart-706c4b16-8354-47b2-b50b-92ca03abf343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946138952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2946138952
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2262859162
Short name T46
Test name
Test status
Simulation time 441715021 ps
CPU time 3.1 seconds
Started Mar 10 02:43:43 PM PDT 24
Finished Mar 10 02:43:46 PM PDT 24
Peak memory 208760 kb
Host smart-7ecf44f3-0fab-4da5-8a7c-ade62d37a9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262859162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2262859162
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.4076814764
Short name T693
Test name
Test status
Simulation time 203064067 ps
CPU time 6.08 seconds
Started Mar 10 02:43:44 PM PDT 24
Finished Mar 10 02:43:50 PM PDT 24
Peak memory 207440 kb
Host smart-93e0a888-416e-4267-8ab7-c0a95224976d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076814764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.4076814764
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.503962995
Short name T583
Test name
Test status
Simulation time 3290596269 ps
CPU time 15.12 seconds
Started Mar 10 02:43:38 PM PDT 24
Finished Mar 10 02:43:53 PM PDT 24
Peak memory 208116 kb
Host smart-0f7fba0e-7d5e-4539-a74f-cd36fec41066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503962995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.503962995
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.4252969060
Short name T841
Test name
Test status
Simulation time 38696087 ps
CPU time 2.7 seconds
Started Mar 10 02:43:36 PM PDT 24
Finished Mar 10 02:43:39 PM PDT 24
Peak memory 208400 kb
Host smart-f329bc77-5bbf-4e1d-8912-ac15a0d25c16
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252969060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.4252969060
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2641341637
Short name T367
Test name
Test status
Simulation time 680303825 ps
CPU time 4.75 seconds
Started Mar 10 02:43:38 PM PDT 24
Finished Mar 10 02:43:43 PM PDT 24
Peak memory 206764 kb
Host smart-f6025a0c-0654-43b4-b890-fc3ec6cac461
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641341637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2641341637
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.936726865
Short name T634
Test name
Test status
Simulation time 244559343 ps
CPU time 7.91 seconds
Started Mar 10 02:43:37 PM PDT 24
Finished Mar 10 02:43:45 PM PDT 24
Peak memory 208084 kb
Host smart-01a4680f-2f99-467f-8433-56a807c29223
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936726865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.936726865
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2295443621
Short name T289
Test name
Test status
Simulation time 71302526 ps
CPU time 3.42 seconds
Started Mar 10 02:43:42 PM PDT 24
Finished Mar 10 02:43:46 PM PDT 24
Peak memory 218416 kb
Host smart-2d502da7-55c1-40da-8be1-4025e4114566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295443621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2295443621
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3090418373
Short name T869
Test name
Test status
Simulation time 8811215089 ps
CPU time 41.68 seconds
Started Mar 10 02:43:36 PM PDT 24
Finished Mar 10 02:44:18 PM PDT 24
Peak memory 209080 kb
Host smart-27668bc3-4f9c-4f4e-aa26-391be5c8caca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090418373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3090418373
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1213196169
Short name T620
Test name
Test status
Simulation time 1155977228 ps
CPU time 12.13 seconds
Started Mar 10 02:43:44 PM PDT 24
Finished Mar 10 02:43:56 PM PDT 24
Peak memory 218816 kb
Host smart-dfe5a9c1-cd90-40ad-bd32-3ddba6353d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213196169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1213196169
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1255617670
Short name T763
Test name
Test status
Simulation time 67499041 ps
CPU time 2.65 seconds
Started Mar 10 02:43:43 PM PDT 24
Finished Mar 10 02:43:45 PM PDT 24
Peak memory 209900 kb
Host smart-25487b3d-cc4f-4f64-912d-a09ff1257aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255617670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1255617670
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3706131735
Short name T761
Test name
Test status
Simulation time 59514632 ps
CPU time 0.92 seconds
Started Mar 10 02:43:47 PM PDT 24
Finished Mar 10 02:43:48 PM PDT 24
Peak memory 206256 kb
Host smart-6765043b-16b8-436c-8cad-36171ca176a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706131735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3706131735
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2698024650
Short name T781
Test name
Test status
Simulation time 88722394 ps
CPU time 3.49 seconds
Started Mar 10 02:43:49 PM PDT 24
Finished Mar 10 02:43:53 PM PDT 24
Peak memory 214448 kb
Host smart-4b7242f1-2648-4720-87b2-b9dec7bf1721
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2698024650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2698024650
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2568970154
Short name T6
Test name
Test status
Simulation time 93630550 ps
CPU time 3.22 seconds
Started Mar 10 02:43:46 PM PDT 24
Finished Mar 10 02:43:49 PM PDT 24
Peak memory 221500 kb
Host smart-60e4a097-8014-466d-a21d-43eb2c1b5489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568970154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2568970154
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2541720133
Short name T397
Test name
Test status
Simulation time 2262015414 ps
CPU time 5 seconds
Started Mar 10 02:43:48 PM PDT 24
Finished Mar 10 02:43:53 PM PDT 24
Peak memory 214584 kb
Host smart-e4853196-158c-487e-beaf-782243542286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541720133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2541720133
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2572805540
Short name T865
Test name
Test status
Simulation time 1217012283 ps
CPU time 8.47 seconds
Started Mar 10 02:43:49 PM PDT 24
Finished Mar 10 02:43:57 PM PDT 24
Peak memory 221340 kb
Host smart-d1547c20-c2c9-467c-830e-33bbf5a3a0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572805540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2572805540
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.505279840
Short name T573
Test name
Test status
Simulation time 104327966 ps
CPU time 4.65 seconds
Started Mar 10 02:43:48 PM PDT 24
Finished Mar 10 02:43:53 PM PDT 24
Peak memory 220384 kb
Host smart-9d09ea3b-c023-4388-99e6-2c78e31d5ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505279840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.505279840
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3631491805
Short name T882
Test name
Test status
Simulation time 325256989 ps
CPU time 3.46 seconds
Started Mar 10 02:43:46 PM PDT 24
Finished Mar 10 02:43:50 PM PDT 24
Peak memory 214492 kb
Host smart-145f40bc-41be-483c-a50e-6cf9f0ff2073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631491805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3631491805
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3004979235
Short name T533
Test name
Test status
Simulation time 117945386 ps
CPU time 3.48 seconds
Started Mar 10 02:43:50 PM PDT 24
Finished Mar 10 02:43:54 PM PDT 24
Peak memory 208612 kb
Host smart-4af5939f-17e7-494d-bb93-c148f201e927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004979235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3004979235
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.705975301
Short name T659
Test name
Test status
Simulation time 24411991 ps
CPU time 1.94 seconds
Started Mar 10 02:43:45 PM PDT 24
Finished Mar 10 02:43:47 PM PDT 24
Peak memory 206744 kb
Host smart-1393b8ed-2e62-40b3-a0cb-0923eec208dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705975301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.705975301
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1054953031
Short name T850
Test name
Test status
Simulation time 70882002 ps
CPU time 2.59 seconds
Started Mar 10 02:43:51 PM PDT 24
Finished Mar 10 02:43:54 PM PDT 24
Peak memory 208532 kb
Host smart-b86d82dc-953e-4b91-b1ca-bd78b16b2272
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054953031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1054953031
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1176596598
Short name T106
Test name
Test status
Simulation time 498025822 ps
CPU time 7.53 seconds
Started Mar 10 02:43:47 PM PDT 24
Finished Mar 10 02:43:55 PM PDT 24
Peak memory 208696 kb
Host smart-3e26a263-b93a-4350-ac84-b008ff29b0b5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176596598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1176596598
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2845787146
Short name T544
Test name
Test status
Simulation time 1509811612 ps
CPU time 18.18 seconds
Started Mar 10 02:43:47 PM PDT 24
Finished Mar 10 02:44:06 PM PDT 24
Peak memory 208556 kb
Host smart-f0ea7935-bc03-4e33-9760-bfff0346a583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845787146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2845787146
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3478867856
Short name T428
Test name
Test status
Simulation time 286801980 ps
CPU time 4.02 seconds
Started Mar 10 02:43:44 PM PDT 24
Finished Mar 10 02:43:48 PM PDT 24
Peak memory 206684 kb
Host smart-49ee50cc-64c3-4ba9-bdb4-0edacebe8642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478867856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3478867856
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3511164717
Short name T39
Test name
Test status
Simulation time 128358565 ps
CPU time 4.26 seconds
Started Mar 10 02:43:49 PM PDT 24
Finished Mar 10 02:43:53 PM PDT 24
Peak memory 222584 kb
Host smart-03634059-b302-479f-b62c-5c29d8d15e15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511164717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3511164717
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.1774110714
Short name T638
Test name
Test status
Simulation time 2748387714 ps
CPU time 10.29 seconds
Started Mar 10 02:43:45 PM PDT 24
Finished Mar 10 02:43:55 PM PDT 24
Peak memory 222992 kb
Host smart-d67f9e0e-b343-4074-9fab-cea8208a90c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774110714 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.1774110714
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3277127809
Short name T672
Test name
Test status
Simulation time 1962152986 ps
CPU time 13.16 seconds
Started Mar 10 02:43:47 PM PDT 24
Finished Mar 10 02:44:00 PM PDT 24
Peak memory 218616 kb
Host smart-6e79f373-48a2-4b02-a628-78578e2d3b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277127809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3277127809
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1919355561
Short name T148
Test name
Test status
Simulation time 59510299 ps
CPU time 2.15 seconds
Started Mar 10 02:43:48 PM PDT 24
Finished Mar 10 02:43:51 PM PDT 24
Peak memory 209988 kb
Host smart-106ca157-30e7-4727-8fb8-cb19d80c970e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919355561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1919355561
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1965102077
Short name T469
Test name
Test status
Simulation time 44876450 ps
CPU time 0.72 seconds
Started Mar 10 02:43:51 PM PDT 24
Finished Mar 10 02:43:52 PM PDT 24
Peak memory 206124 kb
Host smart-c5a2d874-52b5-4a5b-837e-6a9adb6735e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965102077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1965102077
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1400506392
Short name T368
Test name
Test status
Simulation time 73646695 ps
CPU time 3.13 seconds
Started Mar 10 02:43:51 PM PDT 24
Finished Mar 10 02:43:55 PM PDT 24
Peak memory 215096 kb
Host smart-aa50799f-fef9-4667-b8f9-c6281c55c729
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1400506392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1400506392
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.4137439860
Short name T880
Test name
Test status
Simulation time 186813068 ps
CPU time 4.8 seconds
Started Mar 10 02:43:55 PM PDT 24
Finished Mar 10 02:44:00 PM PDT 24
Peak memory 208944 kb
Host smart-187abe2b-3dc4-4108-8e59-50f653c3171e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137439860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.4137439860
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1931167002
Short name T248
Test name
Test status
Simulation time 109819169 ps
CPU time 4.92 seconds
Started Mar 10 02:43:51 PM PDT 24
Finished Mar 10 02:43:56 PM PDT 24
Peak memory 214556 kb
Host smart-8c0a8fcd-42dd-4294-89bb-50829071bd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931167002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1931167002
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1169773021
Short name T810
Test name
Test status
Simulation time 138726517 ps
CPU time 6.01 seconds
Started Mar 10 02:43:54 PM PDT 24
Finished Mar 10 02:44:00 PM PDT 24
Peak memory 214536 kb
Host smart-07ab0b39-9380-4319-aae8-a90784edfa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169773021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1169773021
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2208471975
Short name T859
Test name
Test status
Simulation time 117643602 ps
CPU time 3.96 seconds
Started Mar 10 02:43:55 PM PDT 24
Finished Mar 10 02:43:59 PM PDT 24
Peak memory 209952 kb
Host smart-e5cb1036-ab90-4b87-abf0-c830aa6a7872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208471975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2208471975
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2869939115
Short name T504
Test name
Test status
Simulation time 1119495229 ps
CPU time 7.41 seconds
Started Mar 10 02:43:46 PM PDT 24
Finished Mar 10 02:43:54 PM PDT 24
Peak memory 207820 kb
Host smart-761ea329-d357-460a-8328-5c08ae8c7d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869939115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2869939115
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1383139939
Short name T276
Test name
Test status
Simulation time 78775956 ps
CPU time 3.63 seconds
Started Mar 10 02:43:46 PM PDT 24
Finished Mar 10 02:43:50 PM PDT 24
Peak memory 206908 kb
Host smart-dcbb84f0-d2ef-4664-994c-d1f1fc1b4516
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383139939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1383139939
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1490655496
Short name T489
Test name
Test status
Simulation time 132582717 ps
CPU time 3.19 seconds
Started Mar 10 02:43:45 PM PDT 24
Finished Mar 10 02:43:48 PM PDT 24
Peak memory 206816 kb
Host smart-8abb4581-8044-4a3e-805c-c1e19ad05c33
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490655496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1490655496
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1689804016
Short name T129
Test name
Test status
Simulation time 57498695 ps
CPU time 3.23 seconds
Started Mar 10 02:43:51 PM PDT 24
Finished Mar 10 02:43:54 PM PDT 24
Peak memory 207456 kb
Host smart-9ede4f9f-a5cd-4138-918a-a450065a6f3e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689804016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1689804016
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.295726585
Short name T864
Test name
Test status
Simulation time 164259202 ps
CPU time 4.59 seconds
Started Mar 10 02:43:51 PM PDT 24
Finished Mar 10 02:43:56 PM PDT 24
Peak memory 209976 kb
Host smart-e7c56a96-13ed-4470-abe6-ae74d5bd78d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295726585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.295726585
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3824272234
Short name T395
Test name
Test status
Simulation time 874952892 ps
CPU time 2.66 seconds
Started Mar 10 02:43:45 PM PDT 24
Finished Mar 10 02:43:48 PM PDT 24
Peak memory 206776 kb
Host smart-56e56400-d445-4ee5-9cc7-383ffab545ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824272234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3824272234
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.962599770
Short name T254
Test name
Test status
Simulation time 4807939754 ps
CPU time 31.71 seconds
Started Mar 10 02:43:52 PM PDT 24
Finished Mar 10 02:44:24 PM PDT 24
Peak memory 222216 kb
Host smart-fa361ba4-b767-4415-b342-52fa453eddbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962599770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.962599770
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.1562542911
Short name T178
Test name
Test status
Simulation time 549811679 ps
CPU time 18.62 seconds
Started Mar 10 02:43:51 PM PDT 24
Finished Mar 10 02:44:10 PM PDT 24
Peak memory 220036 kb
Host smart-a2b21db2-5ab4-4f04-bde0-3f5b60dd91b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562542911 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.1562542911
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1953942310
Short name T261
Test name
Test status
Simulation time 2556036736 ps
CPU time 25.66 seconds
Started Mar 10 02:43:51 PM PDT 24
Finished Mar 10 02:44:17 PM PDT 24
Peak memory 208552 kb
Host smart-73e3cb64-77fd-4007-8f09-a84a8c36ce3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953942310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1953942310
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3279184529
Short name T132
Test name
Test status
Simulation time 271904630 ps
CPU time 1.91 seconds
Started Mar 10 02:43:54 PM PDT 24
Finished Mar 10 02:43:56 PM PDT 24
Peak memory 210032 kb
Host smart-6e625d26-a1b6-4f19-9b75-c84d88cfd03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279184529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3279184529
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3748313572
Short name T568
Test name
Test status
Simulation time 19909634 ps
CPU time 0.73 seconds
Started Mar 10 02:43:57 PM PDT 24
Finished Mar 10 02:43:58 PM PDT 24
Peak memory 206188 kb
Host smart-31274afe-02ac-4d66-b53f-a763e297339e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748313572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3748313572
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1980340622
Short name T20
Test name
Test status
Simulation time 220837379 ps
CPU time 2.63 seconds
Started Mar 10 02:43:55 PM PDT 24
Finished Mar 10 02:43:59 PM PDT 24
Peak memory 218052 kb
Host smart-00ac6589-bb9b-4077-81ee-ef23f349a841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980340622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1980340622
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1491495147
Short name T42
Test name
Test status
Simulation time 31864993 ps
CPU time 1.39 seconds
Started Mar 10 02:43:56 PM PDT 24
Finished Mar 10 02:43:58 PM PDT 24
Peak memory 207384 kb
Host smart-2f012804-0d34-4c73-97af-c8a60221d26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491495147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1491495147
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.982217092
Short name T89
Test name
Test status
Simulation time 526554469 ps
CPU time 5.36 seconds
Started Mar 10 02:43:58 PM PDT 24
Finished Mar 10 02:44:04 PM PDT 24
Peak memory 214416 kb
Host smart-4ffa6aec-b80a-4465-9e67-265dfd4102e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982217092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.982217092
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3069031504
Short name T3
Test name
Test status
Simulation time 263912152 ps
CPU time 4 seconds
Started Mar 10 02:43:55 PM PDT 24
Finished Mar 10 02:43:59 PM PDT 24
Peak memory 209984 kb
Host smart-6d089074-7014-4dde-a493-9c4250bc6788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069031504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3069031504
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3095438864
Short name T866
Test name
Test status
Simulation time 261407895 ps
CPU time 3.69 seconds
Started Mar 10 02:43:57 PM PDT 24
Finished Mar 10 02:44:01 PM PDT 24
Peak memory 206884 kb
Host smart-6f848c8e-7b6f-4c06-9a5d-f2bce539fb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095438864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3095438864
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.4191041424
Short name T738
Test name
Test status
Simulation time 62785566 ps
CPU time 2.94 seconds
Started Mar 10 02:43:51 PM PDT 24
Finished Mar 10 02:43:54 PM PDT 24
Peak memory 207968 kb
Host smart-f65e2d27-37c0-4e17-81b3-41095eb75180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191041424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.4191041424
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1922089231
Short name T764
Test name
Test status
Simulation time 120888269 ps
CPU time 3.23 seconds
Started Mar 10 02:43:55 PM PDT 24
Finished Mar 10 02:43:58 PM PDT 24
Peak memory 208980 kb
Host smart-4234e363-ec94-4879-896b-3c9f019a43e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922089231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1922089231
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2950004705
Short name T512
Test name
Test status
Simulation time 319013513 ps
CPU time 5.29 seconds
Started Mar 10 02:43:57 PM PDT 24
Finished Mar 10 02:44:03 PM PDT 24
Peak memory 208936 kb
Host smart-ada94c77-52bc-4b88-9a54-6859442666a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950004705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2950004705
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3522494269
Short name T592
Test name
Test status
Simulation time 951541381 ps
CPU time 8.34 seconds
Started Mar 10 02:43:55 PM PDT 24
Finished Mar 10 02:44:04 PM PDT 24
Peak memory 208560 kb
Host smart-c6c9de74-f753-439e-a252-5dd5468e4d23
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522494269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3522494269
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3002129562
Short name T599
Test name
Test status
Simulation time 75133361 ps
CPU time 2.81 seconds
Started Mar 10 02:43:58 PM PDT 24
Finished Mar 10 02:44:02 PM PDT 24
Peak memory 208052 kb
Host smart-20a179b6-0ed3-49cb-a985-0043d0ef145f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002129562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3002129562
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1540656560
Short name T712
Test name
Test status
Simulation time 7623212493 ps
CPU time 21.46 seconds
Started Mar 10 02:43:52 PM PDT 24
Finished Mar 10 02:44:14 PM PDT 24
Peak memory 208320 kb
Host smart-6a044a03-a229-47c4-8149-e3e0f3ebba0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540656560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1540656560
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2631310749
Short name T315
Test name
Test status
Simulation time 161656423 ps
CPU time 4.08 seconds
Started Mar 10 02:43:57 PM PDT 24
Finished Mar 10 02:44:02 PM PDT 24
Peak memory 207540 kb
Host smart-e1cde58b-a152-436f-88ff-c7cb81d19614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631310749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2631310749
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3248950811
Short name T640
Test name
Test status
Simulation time 3522827236 ps
CPU time 27.14 seconds
Started Mar 10 02:43:56 PM PDT 24
Finished Mar 10 02:44:24 PM PDT 24
Peak memory 211476 kb
Host smart-7135c48e-1f6c-4cb4-91b3-b0186296562b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248950811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3248950811
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1094925899
Short name T98
Test name
Test status
Simulation time 15385568 ps
CPU time 0.75 seconds
Started Mar 10 02:42:19 PM PDT 24
Finished Mar 10 02:42:20 PM PDT 24
Peak memory 206124 kb
Host smart-55dcd5c6-e87b-456b-bbe8-9285c58bddb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094925899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1094925899
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2333284840
Short name T684
Test name
Test status
Simulation time 149128259 ps
CPU time 3.42 seconds
Started Mar 10 02:42:13 PM PDT 24
Finished Mar 10 02:42:16 PM PDT 24
Peak memory 210220 kb
Host smart-7338cea7-8974-413a-a46f-65db54d89ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333284840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2333284840
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.562454331
Short name T473
Test name
Test status
Simulation time 126332148 ps
CPU time 2.35 seconds
Started Mar 10 02:42:11 PM PDT 24
Finished Mar 10 02:42:13 PM PDT 24
Peak memory 210084 kb
Host smart-d244f217-13b9-4e8d-a7d1-971f96c2d227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562454331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.562454331
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3636698455
Short name T93
Test name
Test status
Simulation time 253475726 ps
CPU time 3.63 seconds
Started Mar 10 02:42:11 PM PDT 24
Finished Mar 10 02:42:15 PM PDT 24
Peak memory 209916 kb
Host smart-2c367ab0-e3f5-42b7-bdbc-da3220c5f8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636698455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3636698455
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2671776709
Short name T44
Test name
Test status
Simulation time 220711657 ps
CPU time 2.07 seconds
Started Mar 10 02:42:12 PM PDT 24
Finished Mar 10 02:42:14 PM PDT 24
Peak memory 214756 kb
Host smart-3cd175d6-ad7f-47d6-8ed0-9972f7819444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671776709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2671776709
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1853921630
Short name T299
Test name
Test status
Simulation time 206871952 ps
CPU time 4.14 seconds
Started Mar 10 02:42:08 PM PDT 24
Finished Mar 10 02:42:12 PM PDT 24
Peak memory 219856 kb
Host smart-fe1a7475-d8dd-462c-b176-6b141a1671db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853921630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1853921630
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3308600276
Short name T102
Test name
Test status
Simulation time 3011849865 ps
CPU time 21.43 seconds
Started Mar 10 02:42:17 PM PDT 24
Finished Mar 10 02:42:38 PM PDT 24
Peak memory 232960 kb
Host smart-f00e255d-b44d-4258-a826-ab5c26f1c21d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308600276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3308600276
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.4025841765
Short name T423
Test name
Test status
Simulation time 39787390 ps
CPU time 2.23 seconds
Started Mar 10 02:42:08 PM PDT 24
Finished Mar 10 02:42:10 PM PDT 24
Peak memory 206844 kb
Host smart-c27004e3-ae5a-4990-b8cf-506602c0e4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025841765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.4025841765
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.754806601
Short name T872
Test name
Test status
Simulation time 38835285 ps
CPU time 2.38 seconds
Started Mar 10 02:42:06 PM PDT 24
Finished Mar 10 02:42:09 PM PDT 24
Peak memory 206880 kb
Host smart-81eceacc-0d2c-4c1b-9314-f33163ef4935
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754806601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.754806601
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1270591259
Short name T424
Test name
Test status
Simulation time 99283632 ps
CPU time 3.93 seconds
Started Mar 10 02:42:07 PM PDT 24
Finished Mar 10 02:42:11 PM PDT 24
Peak memory 206728 kb
Host smart-9b8973c2-3ef5-4b1d-b129-1c152f75a70b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270591259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1270591259
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3170939594
Short name T105
Test name
Test status
Simulation time 215726193 ps
CPU time 3.07 seconds
Started Mar 10 02:42:06 PM PDT 24
Finished Mar 10 02:42:09 PM PDT 24
Peak memory 208960 kb
Host smart-7c62896f-2a17-4af2-98e7-8ba78294e1d9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170939594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3170939594
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2293799317
Short name T327
Test name
Test status
Simulation time 446776415 ps
CPU time 3.49 seconds
Started Mar 10 02:42:12 PM PDT 24
Finished Mar 10 02:42:16 PM PDT 24
Peak memory 209928 kb
Host smart-658e05b3-55e7-43db-ac98-6a6e4b287f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293799317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2293799317
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1479544691
Short name T711
Test name
Test status
Simulation time 916485196 ps
CPU time 2.68 seconds
Started Mar 10 02:42:09 PM PDT 24
Finished Mar 10 02:42:12 PM PDT 24
Peak memory 206752 kb
Host smart-04a285a1-64e0-41ed-a827-79d30b5199ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479544691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1479544691
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.273999994
Short name T294
Test name
Test status
Simulation time 1216156743 ps
CPU time 33.15 seconds
Started Mar 10 02:42:14 PM PDT 24
Finished Mar 10 02:42:47 PM PDT 24
Peak memory 216648 kb
Host smart-f51dd58d-3e96-4ede-9699-e8d725e0cd41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273999994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.273999994
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3083584512
Short name T451
Test name
Test status
Simulation time 316701800 ps
CPU time 3.19 seconds
Started Mar 10 02:42:11 PM PDT 24
Finished Mar 10 02:42:15 PM PDT 24
Peak memory 208348 kb
Host smart-88f144fe-bf8d-44d7-bedf-a3ff3cd7a69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083584512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3083584512
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3873946873
Short name T58
Test name
Test status
Simulation time 71557027 ps
CPU time 3.26 seconds
Started Mar 10 02:42:10 PM PDT 24
Finished Mar 10 02:42:14 PM PDT 24
Peak memory 210120 kb
Host smart-64dc5cb6-8381-4e2e-b83a-c32746cb3a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873946873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3873946873
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2002165928
Short name T437
Test name
Test status
Simulation time 13866089 ps
CPU time 0.87 seconds
Started Mar 10 02:44:06 PM PDT 24
Finished Mar 10 02:44:07 PM PDT 24
Peak memory 206188 kb
Host smart-2ec89318-46ae-4856-8360-b7d95cf59633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002165928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2002165928
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2682991856
Short name T281
Test name
Test status
Simulation time 130246323 ps
CPU time 3.05 seconds
Started Mar 10 02:44:03 PM PDT 24
Finished Mar 10 02:44:06 PM PDT 24
Peak memory 214520 kb
Host smart-b75af906-f6c7-4a87-a239-b5f1681389e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2682991856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2682991856
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3937058023
Short name T10
Test name
Test status
Simulation time 1085997693 ps
CPU time 6.81 seconds
Started Mar 10 02:44:01 PM PDT 24
Finished Mar 10 02:44:09 PM PDT 24
Peak memory 210148 kb
Host smart-8742c243-f943-4b41-8542-352a60b77552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937058023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3937058023
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1961528460
Short name T613
Test name
Test status
Simulation time 245216493 ps
CPU time 3.38 seconds
Started Mar 10 02:43:59 PM PDT 24
Finished Mar 10 02:44:03 PM PDT 24
Peak memory 207772 kb
Host smart-06947f1a-85a7-4756-9a28-f521c90d64cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961528460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1961528460
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1558727865
Short name T579
Test name
Test status
Simulation time 114234709 ps
CPU time 3.79 seconds
Started Mar 10 02:44:11 PM PDT 24
Finished Mar 10 02:44:16 PM PDT 24
Peak memory 214572 kb
Host smart-4d74903d-2a7c-4080-9db9-8fb7b6299ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558727865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1558727865
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.356677768
Short name T794
Test name
Test status
Simulation time 111216010 ps
CPU time 3.46 seconds
Started Mar 10 02:44:03 PM PDT 24
Finished Mar 10 02:44:07 PM PDT 24
Peak memory 208856 kb
Host smart-4863a2d8-0f88-43fc-8c3b-e54e796439be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356677768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.356677768
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2554088684
Short name T856
Test name
Test status
Simulation time 425051391 ps
CPU time 4.93 seconds
Started Mar 10 02:44:00 PM PDT 24
Finished Mar 10 02:44:06 PM PDT 24
Peak memory 207476 kb
Host smart-cf32089b-a88f-4ae6-8937-6871ed4406c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554088684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2554088684
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2605908025
Short name T698
Test name
Test status
Simulation time 245280489 ps
CPU time 5.36 seconds
Started Mar 10 02:44:11 PM PDT 24
Finished Mar 10 02:44:17 PM PDT 24
Peak memory 208512 kb
Host smart-35fc6932-0a14-411e-aed4-e5e360835c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605908025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2605908025
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.991411253
Short name T472
Test name
Test status
Simulation time 275576167 ps
CPU time 3.88 seconds
Started Mar 10 02:44:03 PM PDT 24
Finished Mar 10 02:44:07 PM PDT 24
Peak memory 208932 kb
Host smart-72ae5538-a66e-45aa-8e52-42a80d12e109
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991411253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.991411253
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.629078210
Short name T667
Test name
Test status
Simulation time 65842392 ps
CPU time 3.2 seconds
Started Mar 10 02:44:00 PM PDT 24
Finished Mar 10 02:44:04 PM PDT 24
Peak memory 208128 kb
Host smart-f9b5e2b2-eaf6-4993-b05d-e5e9ab6b76c7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629078210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.629078210
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2991229811
Short name T518
Test name
Test status
Simulation time 753029651 ps
CPU time 7.11 seconds
Started Mar 10 02:44:01 PM PDT 24
Finished Mar 10 02:44:10 PM PDT 24
Peak memory 207924 kb
Host smart-5926fad4-acb1-4783-9e4d-ac4096124b51
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991229811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2991229811
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3956043956
Short name T669
Test name
Test status
Simulation time 451014413 ps
CPU time 4.2 seconds
Started Mar 10 02:44:03 PM PDT 24
Finished Mar 10 02:44:07 PM PDT 24
Peak memory 210012 kb
Host smart-5d3facb6-c289-40ba-b3fb-e661d077233b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956043956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3956043956
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2101164880
Short name T537
Test name
Test status
Simulation time 232017781 ps
CPU time 5.66 seconds
Started Mar 10 02:44:11 PM PDT 24
Finished Mar 10 02:44:17 PM PDT 24
Peak memory 206756 kb
Host smart-737d2477-b96b-45a2-89b3-9d8ee75a1b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101164880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2101164880
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3090099087
Short name T135
Test name
Test status
Simulation time 9360307424 ps
CPU time 57.35 seconds
Started Mar 10 02:44:01 PM PDT 24
Finished Mar 10 02:44:59 PM PDT 24
Peak memory 217144 kb
Host smart-8910ad9c-a068-46d5-8832-7be82a220e85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090099087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3090099087
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.210449477
Short name T471
Test name
Test status
Simulation time 320196464 ps
CPU time 6.25 seconds
Started Mar 10 02:44:02 PM PDT 24
Finished Mar 10 02:44:09 PM PDT 24
Peak memory 206820 kb
Host smart-cd5a6925-185e-45de-88d7-9c2a9f3d468f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210449477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.210449477
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1017092016
Short name T762
Test name
Test status
Simulation time 10839911 ps
CPU time 0.73 seconds
Started Mar 10 02:44:08 PM PDT 24
Finished Mar 10 02:44:09 PM PDT 24
Peak memory 206184 kb
Host smart-1632baa2-55e0-4a08-b20d-8e8baae50172
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017092016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1017092016
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2459454602
Short name T308
Test name
Test status
Simulation time 130117888 ps
CPU time 6.91 seconds
Started Mar 10 02:44:05 PM PDT 24
Finished Mar 10 02:44:12 PM PDT 24
Peak memory 214780 kb
Host smart-191b6f0e-5d08-4e0e-a3df-d13983eedcf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2459454602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2459454602
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2636831568
Short name T410
Test name
Test status
Simulation time 197216676 ps
CPU time 2.4 seconds
Started Mar 10 02:44:08 PM PDT 24
Finished Mar 10 02:44:10 PM PDT 24
Peak memory 210096 kb
Host smart-572b53a9-3c68-41e2-824d-dafe83bf93d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636831568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2636831568
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2217396778
Short name T449
Test name
Test status
Simulation time 705625794 ps
CPU time 5.85 seconds
Started Mar 10 02:44:07 PM PDT 24
Finished Mar 10 02:44:13 PM PDT 24
Peak memory 209420 kb
Host smart-ef5eaca5-27fb-4e9d-8cfd-13bd1d52187a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217396778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2217396778
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2831380871
Short name T203
Test name
Test status
Simulation time 424320452 ps
CPU time 8.15 seconds
Started Mar 10 02:44:07 PM PDT 24
Finished Mar 10 02:44:15 PM PDT 24
Peak memory 214528 kb
Host smart-a1fb30b9-50bf-45ae-890d-3adc0188a18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831380871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2831380871
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1892125713
Short name T679
Test name
Test status
Simulation time 318012960 ps
CPU time 3.58 seconds
Started Mar 10 02:44:09 PM PDT 24
Finished Mar 10 02:44:13 PM PDT 24
Peak memory 216692 kb
Host smart-5df1494f-3807-480d-bc30-ddbe80d01272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892125713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1892125713
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3663700253
Short name T309
Test name
Test status
Simulation time 108737842 ps
CPU time 3.7 seconds
Started Mar 10 02:44:12 PM PDT 24
Finished Mar 10 02:44:16 PM PDT 24
Peak memory 214488 kb
Host smart-60f1726f-d922-4549-b4c6-41a2e6e72d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663700253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3663700253
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.550220782
Short name T441
Test name
Test status
Simulation time 3058387085 ps
CPU time 27.09 seconds
Started Mar 10 02:44:06 PM PDT 24
Finished Mar 10 02:44:33 PM PDT 24
Peak memory 208456 kb
Host smart-bb00acd5-c2e4-4980-b90b-3f955473d08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550220782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.550220782
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3241095118
Short name T703
Test name
Test status
Simulation time 340503535 ps
CPU time 4.16 seconds
Started Mar 10 02:44:06 PM PDT 24
Finished Mar 10 02:44:10 PM PDT 24
Peak memory 208940 kb
Host smart-b510663c-a856-4fda-9c85-0896d03249c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241095118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3241095118
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3003209452
Short name T596
Test name
Test status
Simulation time 77974981 ps
CPU time 3.53 seconds
Started Mar 10 02:44:06 PM PDT 24
Finished Mar 10 02:44:09 PM PDT 24
Peak memory 208996 kb
Host smart-98e2b21c-f487-43a5-8a05-707df40c4b3b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003209452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3003209452
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.710766630
Short name T605
Test name
Test status
Simulation time 130761958 ps
CPU time 4.38 seconds
Started Mar 10 02:44:06 PM PDT 24
Finished Mar 10 02:44:11 PM PDT 24
Peak memory 208724 kb
Host smart-fc1cce02-a2a0-4091-a71c-a85d3d2b6a1b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710766630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.710766630
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.671390732
Short name T352
Test name
Test status
Simulation time 250837376 ps
CPU time 4.18 seconds
Started Mar 10 02:44:11 PM PDT 24
Finished Mar 10 02:44:16 PM PDT 24
Peak memory 218620 kb
Host smart-82b9c453-33e2-469d-9f4f-39b764645104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671390732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.671390732
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.4142054711
Short name T700
Test name
Test status
Simulation time 442702777 ps
CPU time 2.89 seconds
Started Mar 10 02:44:06 PM PDT 24
Finished Mar 10 02:44:09 PM PDT 24
Peak memory 208884 kb
Host smart-79516a0e-cebb-46cd-aa3d-4310d7822d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142054711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.4142054711
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1499935468
Short name T226
Test name
Test status
Simulation time 3648733894 ps
CPU time 38.84 seconds
Started Mar 10 02:44:12 PM PDT 24
Finished Mar 10 02:44:51 PM PDT 24
Peak memory 216140 kb
Host smart-b5d7a820-3a53-43fc-a6b1-70f2fc6e0631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499935468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1499935468
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2509840519
Short name T623
Test name
Test status
Simulation time 436230885 ps
CPU time 6.02 seconds
Started Mar 10 02:44:11 PM PDT 24
Finished Mar 10 02:44:18 PM PDT 24
Peak memory 216372 kb
Host smart-c670ab74-21d2-4180-af03-f058c3b9dc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509840519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2509840519
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.4137161825
Short name T398
Test name
Test status
Simulation time 50021200 ps
CPU time 2.36 seconds
Started Mar 10 02:44:10 PM PDT 24
Finished Mar 10 02:44:13 PM PDT 24
Peak memory 209724 kb
Host smart-9b9e47f9-6eaf-4174-872f-abf229ccd198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137161825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.4137161825
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3058427145
Short name T665
Test name
Test status
Simulation time 14038932 ps
CPU time 0.92 seconds
Started Mar 10 02:44:13 PM PDT 24
Finished Mar 10 02:44:14 PM PDT 24
Peak memory 206152 kb
Host smart-0e762991-bb58-4a66-8324-7d2845feb8ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058427145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3058427145
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.325245480
Short name T457
Test name
Test status
Simulation time 159497955 ps
CPU time 2.79 seconds
Started Mar 10 02:44:09 PM PDT 24
Finished Mar 10 02:44:12 PM PDT 24
Peak memory 209448 kb
Host smart-d022c88e-d944-4b1d-af3b-035d3b4f7374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325245480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.325245480
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1365134514
Short name T509
Test name
Test status
Simulation time 93896772 ps
CPU time 4.04 seconds
Started Mar 10 02:44:10 PM PDT 24
Finished Mar 10 02:44:15 PM PDT 24
Peak memory 222608 kb
Host smart-07d1a2b5-bb61-46b3-bac5-627b046466ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365134514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1365134514
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2981525140
Short name T589
Test name
Test status
Simulation time 752744429 ps
CPU time 7.73 seconds
Started Mar 10 02:44:10 PM PDT 24
Finished Mar 10 02:44:18 PM PDT 24
Peak memory 209736 kb
Host smart-54984994-ade7-433a-8aed-06144383dd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981525140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2981525140
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2054469990
Short name T816
Test name
Test status
Simulation time 162617852 ps
CPU time 6.27 seconds
Started Mar 10 02:44:17 PM PDT 24
Finished Mar 10 02:44:23 PM PDT 24
Peak memory 208008 kb
Host smart-69408d3d-2bee-4874-8a4f-b8d1bac0085d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054469990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2054469990
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1292122614
Short name T689
Test name
Test status
Simulation time 404991324 ps
CPU time 6.26 seconds
Started Mar 10 02:44:06 PM PDT 24
Finished Mar 10 02:44:12 PM PDT 24
Peak memory 208716 kb
Host smart-e22912a8-8cba-4125-83c9-69d8b345efdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292122614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1292122614
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.4032265552
Short name T690
Test name
Test status
Simulation time 37915223 ps
CPU time 2.5 seconds
Started Mar 10 02:44:17 PM PDT 24
Finished Mar 10 02:44:20 PM PDT 24
Peak memory 206928 kb
Host smart-f486f4fc-dac6-4c40-aa71-f372bd294afc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032265552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.4032265552
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.361925863
Short name T436
Test name
Test status
Simulation time 240520373 ps
CPU time 5.8 seconds
Started Mar 10 02:44:05 PM PDT 24
Finished Mar 10 02:44:11 PM PDT 24
Peak memory 208772 kb
Host smart-4a7b46c2-9afa-4f89-be79-1337de180a3b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361925863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.361925863
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2965488604
Short name T217
Test name
Test status
Simulation time 3457417203 ps
CPU time 22.51 seconds
Started Mar 10 02:44:12 PM PDT 24
Finished Mar 10 02:44:34 PM PDT 24
Peak memory 208612 kb
Host smart-a40f1a16-9f1f-4857-9fe7-17d46c284134
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965488604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2965488604
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3410803727
Short name T548
Test name
Test status
Simulation time 175233459 ps
CPU time 2.8 seconds
Started Mar 10 02:44:10 PM PDT 24
Finished Mar 10 02:44:13 PM PDT 24
Peak memory 209212 kb
Host smart-83573c37-7b44-4672-8faf-01e23ad7c6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410803727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3410803727
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.4163578305
Short name T466
Test name
Test status
Simulation time 188670868 ps
CPU time 1.75 seconds
Started Mar 10 02:44:11 PM PDT 24
Finished Mar 10 02:44:12 PM PDT 24
Peak memory 206724 kb
Host smart-f82c1417-d8c7-410a-99a6-06a05fd125ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163578305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.4163578305
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3234841283
Short name T262
Test name
Test status
Simulation time 13401283480 ps
CPU time 135.57 seconds
Started Mar 10 02:44:09 PM PDT 24
Finished Mar 10 02:46:25 PM PDT 24
Peak memory 216696 kb
Host smart-444433f6-84d8-4dc5-aa2e-6ab269dd8345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234841283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3234841283
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1972842978
Short name T464
Test name
Test status
Simulation time 1563840763 ps
CPU time 11.25 seconds
Started Mar 10 02:44:09 PM PDT 24
Finished Mar 10 02:44:21 PM PDT 24
Peak memory 210036 kb
Host smart-8d2aaf3d-02d2-4f65-9c3b-8a31a692604f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972842978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1972842978
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1094986683
Short name T643
Test name
Test status
Simulation time 210732468 ps
CPU time 5 seconds
Started Mar 10 02:44:11 PM PDT 24
Finished Mar 10 02:44:17 PM PDT 24
Peak memory 210776 kb
Host smart-ddb7a8bb-40b8-4e2a-aff7-0b65bf7574a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094986683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1094986683
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.871749861
Short name T707
Test name
Test status
Simulation time 49894523 ps
CPU time 0.81 seconds
Started Mar 10 02:44:17 PM PDT 24
Finished Mar 10 02:44:18 PM PDT 24
Peak memory 206136 kb
Host smart-24510df4-2092-49bf-b8b5-631e2cd73af2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871749861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.871749861
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2016221930
Short name T238
Test name
Test status
Simulation time 216744785 ps
CPU time 4 seconds
Started Mar 10 02:44:11 PM PDT 24
Finished Mar 10 02:44:16 PM PDT 24
Peak memory 214524 kb
Host smart-070bddad-471c-41b1-a0c5-2a5d897927a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2016221930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2016221930
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3842980822
Short name T34
Test name
Test status
Simulation time 117967161 ps
CPU time 3.93 seconds
Started Mar 10 02:44:15 PM PDT 24
Finished Mar 10 02:44:19 PM PDT 24
Peak memory 210104 kb
Host smart-a9d6064f-3613-4097-a025-11b9d634717b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842980822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3842980822
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2033723131
Short name T55
Test name
Test status
Simulation time 414885267 ps
CPU time 3.64 seconds
Started Mar 10 02:44:13 PM PDT 24
Finished Mar 10 02:44:16 PM PDT 24
Peak memory 210124 kb
Host smart-9b7cb82c-de89-4c0e-aa87-3cde51671e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033723131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2033723131
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.798133249
Short name T847
Test name
Test status
Simulation time 773113347 ps
CPU time 4.94 seconds
Started Mar 10 02:44:15 PM PDT 24
Finished Mar 10 02:44:20 PM PDT 24
Peak memory 208740 kb
Host smart-699b265e-7adc-46fe-9e50-d8c207c52518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798133249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.798133249
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2379445687
Short name T539
Test name
Test status
Simulation time 111083289 ps
CPU time 2.13 seconds
Started Mar 10 02:44:15 PM PDT 24
Finished Mar 10 02:44:17 PM PDT 24
Peak memory 206344 kb
Host smart-66130a6c-d297-41cd-94b1-3c19f1029cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379445687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2379445687
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3341871919
Short name T100
Test name
Test status
Simulation time 1692635641 ps
CPU time 5.9 seconds
Started Mar 10 02:44:11 PM PDT 24
Finished Mar 10 02:44:18 PM PDT 24
Peak memory 207400 kb
Host smart-7040342a-bb6c-4507-ba3d-d40217824103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341871919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3341871919
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.186697663
Short name T621
Test name
Test status
Simulation time 150821972 ps
CPU time 3.33 seconds
Started Mar 10 02:44:13 PM PDT 24
Finished Mar 10 02:44:17 PM PDT 24
Peak memory 208660 kb
Host smart-d5c57565-0990-473a-9ddd-029689b2765c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186697663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.186697663
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3405284854
Short name T657
Test name
Test status
Simulation time 142866565 ps
CPU time 4.9 seconds
Started Mar 10 02:44:10 PM PDT 24
Finished Mar 10 02:44:15 PM PDT 24
Peak memory 206884 kb
Host smart-247024af-1530-45ff-b724-8130f0181dfe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405284854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3405284854
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2666936339
Short name T445
Test name
Test status
Simulation time 102778574 ps
CPU time 3.76 seconds
Started Mar 10 02:44:10 PM PDT 24
Finished Mar 10 02:44:14 PM PDT 24
Peak memory 208540 kb
Host smart-571f6283-2139-4312-b4c5-726202caaa0a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666936339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2666936339
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3013199667
Short name T258
Test name
Test status
Simulation time 4497989989 ps
CPU time 59.81 seconds
Started Mar 10 02:44:11 PM PDT 24
Finished Mar 10 02:45:11 PM PDT 24
Peak memory 209076 kb
Host smart-0c8eefa5-f8ac-443b-bc37-dadecea53c96
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013199667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3013199667
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2099258317
Short name T734
Test name
Test status
Simulation time 116567854 ps
CPU time 3.22 seconds
Started Mar 10 02:44:13 PM PDT 24
Finished Mar 10 02:44:17 PM PDT 24
Peak memory 218368 kb
Host smart-a3458c96-5b4e-4b31-8127-e541c8cf735b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099258317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2099258317
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.112694933
Short name T456
Test name
Test status
Simulation time 209442096 ps
CPU time 2.96 seconds
Started Mar 10 02:44:11 PM PDT 24
Finished Mar 10 02:44:15 PM PDT 24
Peak memory 206732 kb
Host smart-1f06e9a9-3766-4ae7-9654-2ee3a657ff4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112694933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.112694933
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3458559630
Short name T559
Test name
Test status
Simulation time 138397505 ps
CPU time 2.82 seconds
Started Mar 10 02:44:17 PM PDT 24
Finished Mar 10 02:44:20 PM PDT 24
Peak memory 208228 kb
Host smart-056a9d2e-b10e-4e4a-a961-012f93c7ba69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458559630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3458559630
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3893965689
Short name T718
Test name
Test status
Simulation time 144839361 ps
CPU time 3.68 seconds
Started Mar 10 02:44:16 PM PDT 24
Finished Mar 10 02:44:20 PM PDT 24
Peak memory 209676 kb
Host smart-83be507f-df8f-44bb-92e3-900e26773672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893965689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3893965689
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3611458342
Short name T503
Test name
Test status
Simulation time 12545582 ps
CPU time 0.89 seconds
Started Mar 10 02:44:19 PM PDT 24
Finished Mar 10 02:44:20 PM PDT 24
Peak memory 206132 kb
Host smart-a867edd6-d018-42c1-ad0b-b40876b8a727
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611458342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3611458342
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.194512338
Short name T607
Test name
Test status
Simulation time 1189254133 ps
CPU time 26.61 seconds
Started Mar 10 02:44:20 PM PDT 24
Finished Mar 10 02:44:47 PM PDT 24
Peak memory 214752 kb
Host smart-29953836-397a-4d69-bdc7-5fb1265ba1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194512338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.194512338
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3143279323
Short name T754
Test name
Test status
Simulation time 218210973 ps
CPU time 3.17 seconds
Started Mar 10 02:44:21 PM PDT 24
Finished Mar 10 02:44:24 PM PDT 24
Peak memory 210156 kb
Host smart-32b580a1-e7a5-4192-a932-a81079c15468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143279323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3143279323
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2706752946
Short name T695
Test name
Test status
Simulation time 342137766 ps
CPU time 6.71 seconds
Started Mar 10 02:44:21 PM PDT 24
Finished Mar 10 02:44:28 PM PDT 24
Peak memory 209580 kb
Host smart-b2f30035-fec1-407c-8177-e4a905a67c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706752946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2706752946
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1796622948
Short name T817
Test name
Test status
Simulation time 299852236 ps
CPU time 9.04 seconds
Started Mar 10 02:44:20 PM PDT 24
Finished Mar 10 02:44:29 PM PDT 24
Peak memory 210468 kb
Host smart-e07ade81-d1fb-440b-aa05-3ab29bb9ff48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796622948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1796622948
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_random.1944134177
Short name T894
Test name
Test status
Simulation time 3381421870 ps
CPU time 31.76 seconds
Started Mar 10 02:44:20 PM PDT 24
Finished Mar 10 02:44:52 PM PDT 24
Peak memory 209692 kb
Host smart-cf8e4fcb-079b-47da-a351-e4687b164901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944134177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1944134177
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1186975740
Short name T292
Test name
Test status
Simulation time 323181777 ps
CPU time 5.13 seconds
Started Mar 10 02:44:19 PM PDT 24
Finished Mar 10 02:44:25 PM PDT 24
Peak memory 207672 kb
Host smart-19e7d9f5-c352-4ac1-b873-74fff9e755c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186975740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1186975740
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2829879599
Short name T465
Test name
Test status
Simulation time 182372256 ps
CPU time 2.65 seconds
Started Mar 10 02:44:20 PM PDT 24
Finished Mar 10 02:44:23 PM PDT 24
Peak memory 206864 kb
Host smart-80bdcb00-5f0d-48f9-9b4c-5ff885d576cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829879599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2829879599
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.38811304
Short name T474
Test name
Test status
Simulation time 10964221689 ps
CPU time 56.29 seconds
Started Mar 10 02:44:18 PM PDT 24
Finished Mar 10 02:45:14 PM PDT 24
Peak memory 209104 kb
Host smart-b85387b8-7a0d-4287-a18e-caba2ced0597
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38811304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.38811304
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3402225772
Short name T769
Test name
Test status
Simulation time 2332645135 ps
CPU time 20.24 seconds
Started Mar 10 02:44:21 PM PDT 24
Finished Mar 10 02:44:43 PM PDT 24
Peak memory 208956 kb
Host smart-5c883cdd-791a-492b-b036-7a1a4598daa8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402225772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3402225772
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3189956379
Short name T735
Test name
Test status
Simulation time 207415467 ps
CPU time 4.01 seconds
Started Mar 10 02:44:19 PM PDT 24
Finished Mar 10 02:44:23 PM PDT 24
Peak memory 209780 kb
Host smart-dfb5e344-92be-4964-bf87-5371ce02c245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189956379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3189956379
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3017400175
Short name T435
Test name
Test status
Simulation time 516105870 ps
CPU time 3.85 seconds
Started Mar 10 02:44:14 PM PDT 24
Finished Mar 10 02:44:18 PM PDT 24
Peak memory 206732 kb
Host smart-e5df90e3-6986-40fe-992b-d51fd580f705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017400175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3017400175
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.4192546869
Short name T222
Test name
Test status
Simulation time 3641619077 ps
CPU time 30.2 seconds
Started Mar 10 02:44:25 PM PDT 24
Finished Mar 10 02:44:58 PM PDT 24
Peak memory 221312 kb
Host smart-ae12d699-5fce-44e9-9efe-705746050f02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192546869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.4192546869
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2240128766
Short name T267
Test name
Test status
Simulation time 559557874 ps
CPU time 4.58 seconds
Started Mar 10 02:44:21 PM PDT 24
Finished Mar 10 02:44:25 PM PDT 24
Peak memory 207896 kb
Host smart-99da586e-4bba-4362-8cae-02c7d87b1614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240128766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2240128766
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1686331375
Short name T4
Test name
Test status
Simulation time 60481964 ps
CPU time 2.54 seconds
Started Mar 10 02:44:19 PM PDT 24
Finished Mar 10 02:44:21 PM PDT 24
Peak memory 210660 kb
Host smart-ddb9a5cb-9a0a-4961-80f7-9c7a8f141145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686331375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1686331375
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3958002843
Short name T493
Test name
Test status
Simulation time 22576912 ps
CPU time 0.8 seconds
Started Mar 10 02:44:26 PM PDT 24
Finished Mar 10 02:44:28 PM PDT 24
Peak memory 206124 kb
Host smart-3b57b716-5679-4de5-83d7-74b9f1e2aca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958002843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3958002843
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.308471426
Short name T412
Test name
Test status
Simulation time 4547759217 ps
CPU time 118.55 seconds
Started Mar 10 02:44:26 PM PDT 24
Finished Mar 10 02:46:27 PM PDT 24
Peak memory 218892 kb
Host smart-b8d67b0c-f036-4aa0-82f5-d4638fdcae04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=308471426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.308471426
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.791897016
Short name T66
Test name
Test status
Simulation time 99142369 ps
CPU time 2.75 seconds
Started Mar 10 02:44:26 PM PDT 24
Finished Mar 10 02:44:31 PM PDT 24
Peak memory 219280 kb
Host smart-7fa3dd30-d8cb-4ca5-aff1-131fda225c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791897016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.791897016
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.695629972
Short name T492
Test name
Test status
Simulation time 5188229291 ps
CPU time 51.12 seconds
Started Mar 10 02:44:24 PM PDT 24
Finished Mar 10 02:45:16 PM PDT 24
Peak memory 214576 kb
Host smart-230d1891-0759-46f0-aca4-78ab91f325d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695629972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.695629972
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2042151946
Short name T253
Test name
Test status
Simulation time 100220082 ps
CPU time 4.97 seconds
Started Mar 10 02:44:26 PM PDT 24
Finished Mar 10 02:44:33 PM PDT 24
Peak memory 222644 kb
Host smart-2a72af49-2183-4f03-9f0f-82e8253b2ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042151946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2042151946
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1189186566
Short name T506
Test name
Test status
Simulation time 765225458 ps
CPU time 6.23 seconds
Started Mar 10 02:44:26 PM PDT 24
Finished Mar 10 02:44:33 PM PDT 24
Peak memory 219968 kb
Host smart-d07878be-535d-4e33-a8bb-96f8b9d7e3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189186566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1189186566
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.404226050
Short name T877
Test name
Test status
Simulation time 156783611 ps
CPU time 4.54 seconds
Started Mar 10 02:44:26 PM PDT 24
Finished Mar 10 02:44:32 PM PDT 24
Peak memory 209116 kb
Host smart-2f4bb391-07ec-461f-a71b-f5113b208028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404226050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.404226050
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1559721264
Short name T826
Test name
Test status
Simulation time 242092790 ps
CPU time 2.97 seconds
Started Mar 10 02:44:26 PM PDT 24
Finished Mar 10 02:44:31 PM PDT 24
Peak memory 207124 kb
Host smart-f5c006bd-f1bf-489c-83c7-25f69717a79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559721264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1559721264
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2116937828
Short name T354
Test name
Test status
Simulation time 7513708399 ps
CPU time 57.48 seconds
Started Mar 10 02:44:17 PM PDT 24
Finished Mar 10 02:45:15 PM PDT 24
Peak memory 208288 kb
Host smart-a687f2d0-9649-40d8-96dc-707c37c3714d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116937828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2116937828
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2364080143
Short name T490
Test name
Test status
Simulation time 236502293 ps
CPU time 3.12 seconds
Started Mar 10 02:44:25 PM PDT 24
Finished Mar 10 02:44:31 PM PDT 24
Peak memory 208504 kb
Host smart-91c49187-7095-45ef-aac5-459467b38a5b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364080143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2364080143
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.4156785733
Short name T311
Test name
Test status
Simulation time 1956919847 ps
CPU time 5.71 seconds
Started Mar 10 02:44:26 PM PDT 24
Finished Mar 10 02:44:33 PM PDT 24
Peak memory 208504 kb
Host smart-22230104-b48a-4636-b28e-de14571d8835
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156785733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.4156785733
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3473005296
Short name T658
Test name
Test status
Simulation time 81378712 ps
CPU time 1.88 seconds
Started Mar 10 02:44:24 PM PDT 24
Finished Mar 10 02:44:28 PM PDT 24
Peak memory 208496 kb
Host smart-6a24ef3a-5fc1-41d4-a283-5fccf74bd9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473005296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3473005296
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.122086905
Short name T789
Test name
Test status
Simulation time 900010280 ps
CPU time 6.45 seconds
Started Mar 10 02:44:22 PM PDT 24
Finished Mar 10 02:44:29 PM PDT 24
Peak memory 208404 kb
Host smart-5d027eb8-e98f-4d50-bb40-2841790774b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122086905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.122086905
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1328190910
Short name T392
Test name
Test status
Simulation time 2483759201 ps
CPU time 16.61 seconds
Started Mar 10 02:44:24 PM PDT 24
Finished Mar 10 02:44:43 PM PDT 24
Peak memory 220084 kb
Host smart-b4dd9632-f2ee-4088-b17b-e9fd8ea6eaac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328190910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1328190910
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.4288962218
Short name T177
Test name
Test status
Simulation time 550148934 ps
CPU time 18.75 seconds
Started Mar 10 02:44:28 PM PDT 24
Finished Mar 10 02:44:48 PM PDT 24
Peak memory 222832 kb
Host smart-8ab79f2f-ebaf-47da-bfab-ddeb78b70d08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288962218 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.4288962218
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3642557689
Short name T663
Test name
Test status
Simulation time 1189551292 ps
CPU time 28.52 seconds
Started Mar 10 02:44:26 PM PDT 24
Finished Mar 10 02:44:56 PM PDT 24
Peak memory 210068 kb
Host smart-7dccb0a5-4e80-4d85-a9f9-fb955bf0b173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642557689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3642557689
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2279211274
Short name T678
Test name
Test status
Simulation time 201518924 ps
CPU time 2.48 seconds
Started Mar 10 02:44:26 PM PDT 24
Finished Mar 10 02:44:30 PM PDT 24
Peak memory 209864 kb
Host smart-e698b612-182b-4c16-a66e-5e8432025bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279211274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2279211274
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1626782446
Short name T714
Test name
Test status
Simulation time 13771858 ps
CPU time 0.86 seconds
Started Mar 10 02:44:30 PM PDT 24
Finished Mar 10 02:44:33 PM PDT 24
Peak memory 206312 kb
Host smart-5bae1e8e-6fbe-48c6-acbd-82db4449491f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626782446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1626782446
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2258930628
Short name T338
Test name
Test status
Simulation time 332166059 ps
CPU time 9.23 seconds
Started Mar 10 02:44:26 PM PDT 24
Finished Mar 10 02:44:38 PM PDT 24
Peak memory 214476 kb
Host smart-5cdfe8cf-2dc1-42ca-b53d-69b71d70d578
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2258930628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2258930628
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.4140245586
Short name T31
Test name
Test status
Simulation time 69728397 ps
CPU time 3.87 seconds
Started Mar 10 02:44:31 PM PDT 24
Finished Mar 10 02:44:37 PM PDT 24
Peak memory 209576 kb
Host smart-af6a3312-284a-4450-b690-9599f0129ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140245586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.4140245586
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.381120641
Short name T104
Test name
Test status
Simulation time 66551985 ps
CPU time 2.53 seconds
Started Mar 10 02:44:26 PM PDT 24
Finished Mar 10 02:44:30 PM PDT 24
Peak memory 214460 kb
Host smart-5f73da86-a569-4298-adb7-37704a50f39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381120641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.381120641
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.415357690
Short name T287
Test name
Test status
Simulation time 2497958542 ps
CPU time 11.67 seconds
Started Mar 10 02:44:31 PM PDT 24
Finished Mar 10 02:44:43 PM PDT 24
Peak memory 222772 kb
Host smart-edd87b52-3963-4f79-9f56-78e40f4add16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415357690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.415357690
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1314819190
Short name T751
Test name
Test status
Simulation time 90777206 ps
CPU time 3.69 seconds
Started Mar 10 02:44:29 PM PDT 24
Finished Mar 10 02:44:34 PM PDT 24
Peak memory 209736 kb
Host smart-7c5d7493-2f72-4a4e-975d-dd1c403b860b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314819190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1314819190
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.4124894911
Short name T651
Test name
Test status
Simulation time 41051120 ps
CPU time 3.18 seconds
Started Mar 10 02:44:24 PM PDT 24
Finished Mar 10 02:44:28 PM PDT 24
Peak memory 207616 kb
Host smart-a1a831f9-d9a2-4d12-af50-e390df828ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124894911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.4124894911
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2562002851
Short name T206
Test name
Test status
Simulation time 1155822800 ps
CPU time 15.37 seconds
Started Mar 10 02:44:26 PM PDT 24
Finished Mar 10 02:44:43 PM PDT 24
Peak memory 208688 kb
Host smart-dd3f6c16-8883-4d24-b3c0-5ddd5729c7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562002851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2562002851
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2606011137
Short name T824
Test name
Test status
Simulation time 67607142 ps
CPU time 3.36 seconds
Started Mar 10 02:44:25 PM PDT 24
Finished Mar 10 02:44:30 PM PDT 24
Peak memory 208844 kb
Host smart-929ab4dd-264b-42a3-b0c3-9e5863177ddb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606011137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2606011137
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3783996731
Short name T801
Test name
Test status
Simulation time 254646583 ps
CPU time 3.46 seconds
Started Mar 10 02:44:22 PM PDT 24
Finished Mar 10 02:44:26 PM PDT 24
Peak memory 207316 kb
Host smart-22e7055d-b874-4a8f-969c-cf0d445584ec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783996731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3783996731
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3752936101
Short name T857
Test name
Test status
Simulation time 1488909071 ps
CPU time 10.47 seconds
Started Mar 10 02:44:23 PM PDT 24
Finished Mar 10 02:44:36 PM PDT 24
Peak memory 208880 kb
Host smart-df6d1d5f-71d4-4175-bcc8-4db8bb9a38d2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752936101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3752936101
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3915199727
Short name T510
Test name
Test status
Simulation time 2264301057 ps
CPU time 21.38 seconds
Started Mar 10 02:44:28 PM PDT 24
Finished Mar 10 02:44:51 PM PDT 24
Peak memory 209180 kb
Host smart-d0017ec7-0ac2-4366-8ff6-c06fb455aeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915199727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3915199727
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2610034870
Short name T858
Test name
Test status
Simulation time 34079701 ps
CPU time 2.27 seconds
Started Mar 10 02:44:24 PM PDT 24
Finished Mar 10 02:44:28 PM PDT 24
Peak memory 206676 kb
Host smart-10caee95-19bb-4fd8-9af5-1adc9aef7d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610034870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2610034870
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.323470036
Short name T74
Test name
Test status
Simulation time 6845610277 ps
CPU time 194.01 seconds
Started Mar 10 02:44:29 PM PDT 24
Finished Mar 10 02:47:45 PM PDT 24
Peak memory 217188 kb
Host smart-77b33b24-755e-42dd-8a8f-beec660a415e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323470036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.323470036
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3003854824
Short name T390
Test name
Test status
Simulation time 872961600 ps
CPU time 11.04 seconds
Started Mar 10 02:44:31 PM PDT 24
Finished Mar 10 02:44:43 PM PDT 24
Peak memory 218720 kb
Host smart-0e8e505b-1625-44d6-b823-5470d1f9b513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003854824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3003854824
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.880145451
Short name T158
Test name
Test status
Simulation time 125304078 ps
CPU time 2.57 seconds
Started Mar 10 02:44:31 PM PDT 24
Finished Mar 10 02:44:35 PM PDT 24
Peak memory 210364 kb
Host smart-117a16a9-ff4e-4632-9b00-e41c7c487281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880145451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.880145451
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2106526908
Short name T96
Test name
Test status
Simulation time 32304333 ps
CPU time 0.76 seconds
Started Mar 10 02:44:35 PM PDT 24
Finished Mar 10 02:44:36 PM PDT 24
Peak memory 206152 kb
Host smart-4b12c835-644a-4d3e-9d3f-a44139ec48fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106526908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2106526908
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.376131688
Short name T280
Test name
Test status
Simulation time 110563965 ps
CPU time 2.68 seconds
Started Mar 10 02:44:29 PM PDT 24
Finished Mar 10 02:44:33 PM PDT 24
Peak memory 215064 kb
Host smart-82e39bb3-c188-457a-acf5-d2f28ef167c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=376131688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.376131688
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3528473713
Short name T733
Test name
Test status
Simulation time 643726725 ps
CPU time 21.15 seconds
Started Mar 10 02:44:29 PM PDT 24
Finished Mar 10 02:44:53 PM PDT 24
Peak memory 222836 kb
Host smart-8f06ad0e-5dbc-41a8-8f1f-57d043854c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528473713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3528473713
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2844692723
Short name T848
Test name
Test status
Simulation time 59966493 ps
CPU time 3.35 seconds
Started Mar 10 02:44:28 PM PDT 24
Finished Mar 10 02:44:33 PM PDT 24
Peak memory 207412 kb
Host smart-2ca2d8bc-b368-4a15-ac98-9767439e4276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844692723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2844692723
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1035537910
Short name T378
Test name
Test status
Simulation time 117150763 ps
CPU time 4.76 seconds
Started Mar 10 02:44:29 PM PDT 24
Finished Mar 10 02:44:35 PM PDT 24
Peak memory 209344 kb
Host smart-770d5839-27c0-4721-9326-e0c8478cb2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035537910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1035537910
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3855787627
Short name T729
Test name
Test status
Simulation time 861532200 ps
CPU time 10.89 seconds
Started Mar 10 02:44:32 PM PDT 24
Finished Mar 10 02:44:44 PM PDT 24
Peak memory 214372 kb
Host smart-98d4ee81-2832-43bf-a113-cc24d1c68a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855787627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3855787627
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1197878766
Short name T838
Test name
Test status
Simulation time 108877859 ps
CPU time 3.56 seconds
Started Mar 10 02:44:27 PM PDT 24
Finished Mar 10 02:44:32 PM PDT 24
Peak memory 209192 kb
Host smart-7a870061-8ded-4f45-b504-3859b4544b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197878766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1197878766
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.103122210
Short name T2
Test name
Test status
Simulation time 249063483 ps
CPU time 5.71 seconds
Started Mar 10 02:44:30 PM PDT 24
Finished Mar 10 02:44:38 PM PDT 24
Peak memory 218496 kb
Host smart-8b67a653-231e-4f28-80cc-de8058f403e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103122210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.103122210
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3116964744
Short name T200
Test name
Test status
Simulation time 147321694 ps
CPU time 4.62 seconds
Started Mar 10 02:44:31 PM PDT 24
Finished Mar 10 02:44:38 PM PDT 24
Peak memory 208252 kb
Host smart-4ecb69e5-59c3-4a74-b773-734fc75576a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116964744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3116964744
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.723034431
Short name T259
Test name
Test status
Simulation time 72406136 ps
CPU time 3.18 seconds
Started Mar 10 02:44:30 PM PDT 24
Finished Mar 10 02:44:35 PM PDT 24
Peak memory 208460 kb
Host smart-8d84f04f-d160-4578-8e56-b16fb8aced56
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723034431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.723034431
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3941745716
Short name T211
Test name
Test status
Simulation time 67515685 ps
CPU time 2.6 seconds
Started Mar 10 02:44:29 PM PDT 24
Finished Mar 10 02:44:33 PM PDT 24
Peak memory 208584 kb
Host smart-79b6864e-8bc6-4199-b9a6-6aabdacf364e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941745716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3941745716
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3538459357
Short name T585
Test name
Test status
Simulation time 3914624329 ps
CPU time 44.09 seconds
Started Mar 10 02:44:30 PM PDT 24
Finished Mar 10 02:45:15 PM PDT 24
Peak memory 209076 kb
Host smart-d1f6fc4a-eaf1-457c-801f-2e53ca5b69b1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538459357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3538459357
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3815365450
Short name T779
Test name
Test status
Simulation time 299246947 ps
CPU time 2.88 seconds
Started Mar 10 02:44:30 PM PDT 24
Finished Mar 10 02:44:35 PM PDT 24
Peak memory 215772 kb
Host smart-7a2c52dd-d6ad-4368-9e8c-5f40ff1e7386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815365450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3815365450
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3596330994
Short name T614
Test name
Test status
Simulation time 124106864 ps
CPU time 2.45 seconds
Started Mar 10 02:44:29 PM PDT 24
Finished Mar 10 02:44:33 PM PDT 24
Peak memory 206640 kb
Host smart-d6e8e415-6a98-4a5a-bb89-ae0f57c92d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596330994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3596330994
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3330290269
Short name T300
Test name
Test status
Simulation time 598301260 ps
CPU time 8.32 seconds
Started Mar 10 02:44:30 PM PDT 24
Finished Mar 10 02:44:40 PM PDT 24
Peak memory 216412 kb
Host smart-d847759b-ee17-4724-be60-f128df4db94d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330290269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3330290269
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2340150529
Short name T349
Test name
Test status
Simulation time 175489675 ps
CPU time 3.44 seconds
Started Mar 10 02:44:28 PM PDT 24
Finished Mar 10 02:44:33 PM PDT 24
Peak memory 210180 kb
Host smart-1d72d1c4-ad4c-4894-bb9f-853ce2cb9f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340150529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2340150529
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3477238405
Short name T633
Test name
Test status
Simulation time 188974353 ps
CPU time 3.11 seconds
Started Mar 10 02:44:29 PM PDT 24
Finished Mar 10 02:44:35 PM PDT 24
Peak memory 209984 kb
Host smart-1fe4578f-8aa9-4969-a68e-8be590f2c954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477238405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3477238405
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3098966206
Short name T879
Test name
Test status
Simulation time 22716789 ps
CPU time 0.71 seconds
Started Mar 10 02:44:40 PM PDT 24
Finished Mar 10 02:44:41 PM PDT 24
Peak memory 206024 kb
Host smart-343ea4be-81c6-4aae-aeb0-419ba36ec8ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098966206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3098966206
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.245999949
Short name T358
Test name
Test status
Simulation time 110161470 ps
CPU time 3.92 seconds
Started Mar 10 02:44:40 PM PDT 24
Finished Mar 10 02:44:44 PM PDT 24
Peak memory 215516 kb
Host smart-af469779-3f93-479f-af19-2617188d6970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=245999949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.245999949
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3611144056
Short name T65
Test name
Test status
Simulation time 2769511596 ps
CPU time 53.8 seconds
Started Mar 10 02:44:35 PM PDT 24
Finished Mar 10 02:45:29 PM PDT 24
Peak memory 222636 kb
Host smart-bea8e673-0983-4603-945c-7f72914750ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611144056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3611144056
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2127907056
Short name T75
Test name
Test status
Simulation time 35726339 ps
CPU time 1.88 seconds
Started Mar 10 02:44:33 PM PDT 24
Finished Mar 10 02:44:35 PM PDT 24
Peak memory 206640 kb
Host smart-11984641-a07e-4d21-b2b2-bb968f20cbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127907056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2127907056
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2962983643
Short name T743
Test name
Test status
Simulation time 467756023 ps
CPU time 4.06 seconds
Started Mar 10 02:44:33 PM PDT 24
Finished Mar 10 02:44:38 PM PDT 24
Peak memory 218828 kb
Host smart-cb6331f7-4e8b-4532-8e19-090fc6c79fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962983643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2962983643
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.661885869
Short name T269
Test name
Test status
Simulation time 130167949 ps
CPU time 3.65 seconds
Started Mar 10 02:44:34 PM PDT 24
Finished Mar 10 02:44:38 PM PDT 24
Peak memory 210352 kb
Host smart-d8345db7-8646-4085-b4bd-8ddc2253dd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661885869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.661885869
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3547597660
Short name T798
Test name
Test status
Simulation time 267707771 ps
CPU time 3.8 seconds
Started Mar 10 02:44:35 PM PDT 24
Finished Mar 10 02:44:39 PM PDT 24
Peak memory 210092 kb
Host smart-68d3d6ee-cc71-4889-98d4-88722c3e28ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547597660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3547597660
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.886653394
Short name T854
Test name
Test status
Simulation time 252237171 ps
CPU time 3.69 seconds
Started Mar 10 02:44:34 PM PDT 24
Finished Mar 10 02:44:37 PM PDT 24
Peak memory 209040 kb
Host smart-5048cd69-cb2f-4804-8156-faef5c9d9274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886653394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.886653394
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1303337335
Short name T359
Test name
Test status
Simulation time 47233778 ps
CPU time 3.04 seconds
Started Mar 10 02:44:34 PM PDT 24
Finished Mar 10 02:44:37 PM PDT 24
Peak memory 208700 kb
Host smart-fc486e3c-c56b-4129-a33a-b164e77ff844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303337335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1303337335
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3450987500
Short name T422
Test name
Test status
Simulation time 45416430 ps
CPU time 2.4 seconds
Started Mar 10 02:44:36 PM PDT 24
Finished Mar 10 02:44:39 PM PDT 24
Peak memory 207924 kb
Host smart-967feedc-b3cd-44a0-b710-f26cfb43ab47
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450987500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3450987500
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3586792465
Short name T705
Test name
Test status
Simulation time 7173517132 ps
CPU time 28.44 seconds
Started Mar 10 02:44:38 PM PDT 24
Finished Mar 10 02:45:07 PM PDT 24
Peak memory 208088 kb
Host smart-3201f8cf-225c-4be8-8739-79e6aefa384f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586792465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3586792465
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.312116392
Short name T724
Test name
Test status
Simulation time 234268982 ps
CPU time 2.94 seconds
Started Mar 10 02:44:40 PM PDT 24
Finished Mar 10 02:44:43 PM PDT 24
Peak memory 206772 kb
Host smart-ef114f69-e928-4750-9e2e-99518f56589d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312116392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.312116392
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3769214789
Short name T836
Test name
Test status
Simulation time 57465814 ps
CPU time 2.64 seconds
Started Mar 10 02:44:33 PM PDT 24
Finished Mar 10 02:44:36 PM PDT 24
Peak memory 215336 kb
Host smart-1d93d965-6652-41e4-997c-0c454c62d40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769214789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3769214789
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3668401868
Short name T768
Test name
Test status
Simulation time 74281537 ps
CPU time 3.18 seconds
Started Mar 10 02:44:33 PM PDT 24
Finished Mar 10 02:44:37 PM PDT 24
Peak memory 206600 kb
Host smart-0c246d81-e4d8-46f2-8651-2d24a00202a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668401868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3668401868
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2831994706
Short name T855
Test name
Test status
Simulation time 3854217617 ps
CPU time 51.43 seconds
Started Mar 10 02:44:33 PM PDT 24
Finished Mar 10 02:45:25 PM PDT 24
Peak memory 216112 kb
Host smart-6d743f66-6a0f-46f2-b793-42c6f8ca2497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831994706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2831994706
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3006934966
Short name T385
Test name
Test status
Simulation time 297972993 ps
CPU time 3.32 seconds
Started Mar 10 02:44:36 PM PDT 24
Finished Mar 10 02:44:40 PM PDT 24
Peak memory 210244 kb
Host smart-743656b4-0113-4f00-98b4-0939978bcbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006934966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3006934966
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.222903944
Short name T635
Test name
Test status
Simulation time 22500511 ps
CPU time 0.74 seconds
Started Mar 10 02:44:46 PM PDT 24
Finished Mar 10 02:44:47 PM PDT 24
Peak memory 206136 kb
Host smart-a435ff70-2988-456a-9fbe-d1fba8e9cb93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222903944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.222903944
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3615485709
Short name T27
Test name
Test status
Simulation time 65136915 ps
CPU time 3.11 seconds
Started Mar 10 02:44:37 PM PDT 24
Finished Mar 10 02:44:40 PM PDT 24
Peak memory 210056 kb
Host smart-064356c7-304e-46e0-a9db-6054ce6d0b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615485709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3615485709
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3892156606
Short name T514
Test name
Test status
Simulation time 103714409 ps
CPU time 4.46 seconds
Started Mar 10 02:44:37 PM PDT 24
Finished Mar 10 02:44:42 PM PDT 24
Peak memory 209968 kb
Host smart-2a23e39c-e1c6-4e85-9f78-dc1ab490053c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892156606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3892156606
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3296723618
Short name T270
Test name
Test status
Simulation time 393550983 ps
CPU time 10.37 seconds
Started Mar 10 02:44:39 PM PDT 24
Finished Mar 10 02:44:49 PM PDT 24
Peak memory 222680 kb
Host smart-4efe0faa-0b7d-4b39-99a5-4abb1c202e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296723618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3296723618
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.783496684
Short name T680
Test name
Test status
Simulation time 70590037 ps
CPU time 3.57 seconds
Started Mar 10 02:44:39 PM PDT 24
Finished Mar 10 02:44:42 PM PDT 24
Peak memory 206392 kb
Host smart-db80ae38-38f3-4271-ac45-cb41a8ee49ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783496684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.783496684
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1184668907
Short name T834
Test name
Test status
Simulation time 2441744840 ps
CPU time 31.38 seconds
Started Mar 10 02:44:41 PM PDT 24
Finished Mar 10 02:45:12 PM PDT 24
Peak memory 209816 kb
Host smart-81b8a5ea-07cc-46e1-93a0-fcbd3511e61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184668907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1184668907
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3075577474
Short name T628
Test name
Test status
Simulation time 57139594 ps
CPU time 2.3 seconds
Started Mar 10 02:44:39 PM PDT 24
Finished Mar 10 02:44:42 PM PDT 24
Peak memory 206648 kb
Host smart-a80ca37a-5daf-4cb6-8ce3-5f6d35e8c192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075577474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3075577474
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2128022231
Short name T454
Test name
Test status
Simulation time 592524144 ps
CPU time 6.43 seconds
Started Mar 10 02:44:38 PM PDT 24
Finished Mar 10 02:44:44 PM PDT 24
Peak memory 207912 kb
Host smart-19d0b454-fdbf-480a-86ca-6a64b7af0391
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128022231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2128022231
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3584906135
Short name T770
Test name
Test status
Simulation time 230120765 ps
CPU time 7.94 seconds
Started Mar 10 02:44:40 PM PDT 24
Finished Mar 10 02:44:48 PM PDT 24
Peak memory 207904 kb
Host smart-733c1264-ebbc-49c7-81ef-87b9a316e6c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584906135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3584906135
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.772341574
Short name T805
Test name
Test status
Simulation time 309664695 ps
CPU time 7.72 seconds
Started Mar 10 02:44:40 PM PDT 24
Finished Mar 10 02:44:48 PM PDT 24
Peak memory 208772 kb
Host smart-c240b445-13c0-4b8f-8e5f-969be6e17689
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772341574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.772341574
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3682256986
Short name T644
Test name
Test status
Simulation time 155274449 ps
CPU time 4.13 seconds
Started Mar 10 02:44:40 PM PDT 24
Finished Mar 10 02:44:45 PM PDT 24
Peak memory 210436 kb
Host smart-e25d89dd-b47d-4d61-8fb5-086b2fcbd15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682256986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3682256986
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3823305044
Short name T430
Test name
Test status
Simulation time 36607180 ps
CPU time 2.37 seconds
Started Mar 10 02:44:40 PM PDT 24
Finished Mar 10 02:44:42 PM PDT 24
Peak memory 206848 kb
Host smart-c1656145-a291-46de-8ad8-3abea55ce887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823305044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3823305044
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2816539271
Short name T529
Test name
Test status
Simulation time 328051345 ps
CPU time 9 seconds
Started Mar 10 02:44:47 PM PDT 24
Finished Mar 10 02:44:56 PM PDT 24
Peak memory 216268 kb
Host smart-e9938caa-efd5-4a07-819e-107bbdd9a1e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816539271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2816539271
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2342029649
Short name T180
Test name
Test status
Simulation time 318927469 ps
CPU time 8.09 seconds
Started Mar 10 02:44:43 PM PDT 24
Finished Mar 10 02:44:51 PM PDT 24
Peak memory 222780 kb
Host smart-1fbb32b1-c5fc-4e8f-a588-3d27040a7f77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342029649 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2342029649
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.546130974
Short name T204
Test name
Test status
Simulation time 81504391 ps
CPU time 4.24 seconds
Started Mar 10 02:44:37 PM PDT 24
Finished Mar 10 02:44:41 PM PDT 24
Peak memory 208484 kb
Host smart-dd9a20bb-22e6-4d48-915f-44f6856475c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546130974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.546130974
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1552781918
Short name T717
Test name
Test status
Simulation time 20720656 ps
CPU time 0.85 seconds
Started Mar 10 02:42:25 PM PDT 24
Finished Mar 10 02:42:27 PM PDT 24
Peak memory 206048 kb
Host smart-26e42987-0c0e-4d98-b86b-62e2306de46d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552781918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1552781918
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.697340350
Short name T411
Test name
Test status
Simulation time 105177288 ps
CPU time 3.69 seconds
Started Mar 10 02:42:17 PM PDT 24
Finished Mar 10 02:42:21 PM PDT 24
Peak memory 214428 kb
Host smart-60d66b69-483a-48a9-95cb-85d36c0cc7a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697340350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.697340350
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2863697599
Short name T43
Test name
Test status
Simulation time 186108656 ps
CPU time 2.33 seconds
Started Mar 10 02:42:16 PM PDT 24
Finished Mar 10 02:42:19 PM PDT 24
Peak memory 207468 kb
Host smart-6ecf22b7-daaf-46a7-a569-3ddd3b7ff82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863697599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2863697599
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3361149476
Short name T577
Test name
Test status
Simulation time 3364064307 ps
CPU time 18 seconds
Started Mar 10 02:42:23 PM PDT 24
Finished Mar 10 02:42:41 PM PDT 24
Peak memory 214572 kb
Host smart-56af6670-20c5-468b-a1e4-8cea396576df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361149476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3361149476
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1333885112
Short name T22
Test name
Test status
Simulation time 289930827 ps
CPU time 4.86 seconds
Started Mar 10 02:42:21 PM PDT 24
Finished Mar 10 02:42:26 PM PDT 24
Peak memory 221240 kb
Host smart-7d908cac-dd11-45cf-a04a-03eb9f906496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333885112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1333885112
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2549151180
Short name T219
Test name
Test status
Simulation time 74683125 ps
CPU time 3.53 seconds
Started Mar 10 02:42:17 PM PDT 24
Finished Mar 10 02:42:20 PM PDT 24
Peak memory 220320 kb
Host smart-62568623-cacb-45d0-a32e-a7f4a36af3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549151180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2549151180
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.926168671
Short name T189
Test name
Test status
Simulation time 91697469 ps
CPU time 4.87 seconds
Started Mar 10 02:42:17 PM PDT 24
Finished Mar 10 02:42:22 PM PDT 24
Peak memory 207392 kb
Host smart-b1b76723-62ba-41a3-a7cf-6e9e6c423849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926168671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.926168671
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2037566133
Short name T12
Test name
Test status
Simulation time 3028745023 ps
CPU time 30.83 seconds
Started Mar 10 02:42:21 PM PDT 24
Finished Mar 10 02:42:52 PM PDT 24
Peak memory 233752 kb
Host smart-59c9995d-be71-49fe-ab53-c2e42643d763
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037566133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2037566133
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.4141632065
Short name T570
Test name
Test status
Simulation time 486567816 ps
CPU time 4.34 seconds
Started Mar 10 02:42:18 PM PDT 24
Finished Mar 10 02:42:23 PM PDT 24
Peak memory 206744 kb
Host smart-b91e7940-6dcf-4b26-a014-b4a7144b1d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141632065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4141632065
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1782739104
Short name T809
Test name
Test status
Simulation time 119358415 ps
CPU time 3.21 seconds
Started Mar 10 02:42:17 PM PDT 24
Finished Mar 10 02:42:21 PM PDT 24
Peak memory 207496 kb
Host smart-0c788f7e-1156-4a0d-8a93-626c3bec6fbf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782739104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1782739104
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.4106077286
Short name T336
Test name
Test status
Simulation time 203562392 ps
CPU time 2.7 seconds
Started Mar 10 02:42:18 PM PDT 24
Finished Mar 10 02:42:21 PM PDT 24
Peak memory 206728 kb
Host smart-9f5df77e-551e-4c5a-9299-c65f1304397e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106077286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.4106077286
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.870356794
Short name T305
Test name
Test status
Simulation time 354392036 ps
CPU time 3.39 seconds
Started Mar 10 02:42:15 PM PDT 24
Finished Mar 10 02:42:19 PM PDT 24
Peak memory 208460 kb
Host smart-3e7ae542-7e93-49fb-9fc0-a8581a9dc9f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870356794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.870356794
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3526637686
Short name T5
Test name
Test status
Simulation time 145740350 ps
CPU time 3.37 seconds
Started Mar 10 02:42:23 PM PDT 24
Finished Mar 10 02:42:27 PM PDT 24
Peak memory 209576 kb
Host smart-0d5e78f6-019a-4877-9efa-5e723fb67329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526637686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3526637686
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.4247601235
Short name T612
Test name
Test status
Simulation time 2101328823 ps
CPU time 25.35 seconds
Started Mar 10 02:42:18 PM PDT 24
Finished Mar 10 02:42:44 PM PDT 24
Peak memory 208008 kb
Host smart-cbd29128-0857-4621-af38-b87c4cf3b9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247601235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.4247601235
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.4057813096
Short name T868
Test name
Test status
Simulation time 5082635173 ps
CPU time 36.23 seconds
Started Mar 10 02:42:22 PM PDT 24
Finished Mar 10 02:42:59 PM PDT 24
Peak memory 216040 kb
Host smart-cd8e47a4-f155-4801-adc4-1e8d475950b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057813096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.4057813096
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2125782375
Short name T804
Test name
Test status
Simulation time 9456721764 ps
CPU time 96.2 seconds
Started Mar 10 02:42:18 PM PDT 24
Finished Mar 10 02:43:54 PM PDT 24
Peak memory 210328 kb
Host smart-36ebe730-ce57-43dc-9273-722502d3783d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125782375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2125782375
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3035748194
Short name T111
Test name
Test status
Simulation time 83704265 ps
CPU time 2.08 seconds
Started Mar 10 02:42:23 PM PDT 24
Finished Mar 10 02:42:25 PM PDT 24
Peak memory 209920 kb
Host smart-27185eec-6179-485b-990f-665a7880fba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035748194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3035748194
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.446758444
Short name T555
Test name
Test status
Simulation time 15696776 ps
CPU time 0.86 seconds
Started Mar 10 02:44:47 PM PDT 24
Finished Mar 10 02:44:48 PM PDT 24
Peak memory 206172 kb
Host smart-f8d16260-aa21-4469-b4bf-9d382d15a30c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446758444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.446758444
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3397070136
Short name T682
Test name
Test status
Simulation time 95650855 ps
CPU time 2.36 seconds
Started Mar 10 02:44:45 PM PDT 24
Finished Mar 10 02:44:47 PM PDT 24
Peak memory 214480 kb
Host smart-bedb98c1-35dc-4c18-8ac4-84833395656d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397070136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3397070136
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1739398179
Short name T675
Test name
Test status
Simulation time 46418232 ps
CPU time 2.24 seconds
Started Mar 10 02:44:45 PM PDT 24
Finished Mar 10 02:44:48 PM PDT 24
Peak memory 208336 kb
Host smart-9f192d5f-e5be-4c32-890a-07e1422d0dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739398179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1739398179
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1896300006
Short name T551
Test name
Test status
Simulation time 70630846 ps
CPU time 2.74 seconds
Started Mar 10 02:44:43 PM PDT 24
Finished Mar 10 02:44:46 PM PDT 24
Peak memory 209316 kb
Host smart-e9131837-30c6-4900-ad27-3fa3e4bd780e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896300006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1896300006
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3864518866
Short name T525
Test name
Test status
Simulation time 383260526 ps
CPU time 3.72 seconds
Started Mar 10 02:44:42 PM PDT 24
Finished Mar 10 02:44:46 PM PDT 24
Peak memory 216108 kb
Host smart-7741d5b2-1e75-4525-8b0d-9f0aeb6bdeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864518866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3864518866
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2569718527
Short name T832
Test name
Test status
Simulation time 31734777 ps
CPU time 2.49 seconds
Started Mar 10 02:44:49 PM PDT 24
Finished Mar 10 02:44:51 PM PDT 24
Peak memory 207556 kb
Host smart-099b4172-01a3-4856-bf18-dd30d70245d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569718527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2569718527
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2920161572
Short name T272
Test name
Test status
Simulation time 347811440 ps
CPU time 6.16 seconds
Started Mar 10 02:44:44 PM PDT 24
Finished Mar 10 02:44:50 PM PDT 24
Peak memory 208812 kb
Host smart-b6314d88-7461-4037-9e4a-5fde562e5bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920161572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2920161572
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.919503278
Short name T694
Test name
Test status
Simulation time 59520042 ps
CPU time 2.92 seconds
Started Mar 10 02:44:43 PM PDT 24
Finished Mar 10 02:44:46 PM PDT 24
Peak memory 206932 kb
Host smart-b8310514-c731-4d83-834a-47c3c455050b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919503278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.919503278
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2484914105
Short name T434
Test name
Test status
Simulation time 112879429 ps
CPU time 4.37 seconds
Started Mar 10 02:44:44 PM PDT 24
Finished Mar 10 02:44:48 PM PDT 24
Peak memory 208692 kb
Host smart-8fed3016-e980-4d89-b8c2-e1eef1ac457a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484914105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2484914105
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2370056124
Short name T625
Test name
Test status
Simulation time 1141789974 ps
CPU time 3.85 seconds
Started Mar 10 02:44:46 PM PDT 24
Finished Mar 10 02:44:50 PM PDT 24
Peak memory 208664 kb
Host smart-7a167dd4-fad8-49a5-b907-0e0e130c48f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370056124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2370056124
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.390250263
Short name T208
Test name
Test status
Simulation time 2479619758 ps
CPU time 29.45 seconds
Started Mar 10 02:44:44 PM PDT 24
Finished Mar 10 02:45:13 PM PDT 24
Peak memory 209876 kb
Host smart-8e544c14-fcf5-4563-8313-2f74ac1ef1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390250263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.390250263
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3446190545
Short name T195
Test name
Test status
Simulation time 559829826 ps
CPU time 3.95 seconds
Started Mar 10 02:44:42 PM PDT 24
Finished Mar 10 02:44:46 PM PDT 24
Peak memory 208484 kb
Host smart-516915bc-c41e-494f-8a13-29888203f603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446190545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3446190545
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1251379722
Short name T788
Test name
Test status
Simulation time 5065114158 ps
CPU time 31.39 seconds
Started Mar 10 02:44:48 PM PDT 24
Finished Mar 10 02:45:19 PM PDT 24
Peak memory 219772 kb
Host smart-17077ffa-c902-472a-8705-785d832d10e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251379722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1251379722
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1611141371
Short name T666
Test name
Test status
Simulation time 2999952930 ps
CPU time 23.34 seconds
Started Mar 10 02:44:43 PM PDT 24
Finished Mar 10 02:45:06 PM PDT 24
Peak memory 219948 kb
Host smart-83be5821-f4a3-42e3-8ad5-e84add87e6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611141371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1611141371
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.554105954
Short name T220
Test name
Test status
Simulation time 67670659 ps
CPU time 2.9 seconds
Started Mar 10 02:44:49 PM PDT 24
Finished Mar 10 02:44:52 PM PDT 24
Peak memory 209864 kb
Host smart-344bfd59-c9b8-4950-9132-10c3664750c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554105954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.554105954
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.4047258927
Short name T732
Test name
Test status
Simulation time 19871420 ps
CPU time 0.72 seconds
Started Mar 10 02:44:51 PM PDT 24
Finished Mar 10 02:44:52 PM PDT 24
Peak memory 206172 kb
Host smart-7c59097c-c701-4e6e-9f18-1d538dc50bcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047258927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.4047258927
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1409325845
Short name T36
Test name
Test status
Simulation time 111929436 ps
CPU time 3.3 seconds
Started Mar 10 02:44:49 PM PDT 24
Finished Mar 10 02:44:53 PM PDT 24
Peak memory 222860 kb
Host smart-edae1ec5-dc93-4265-824e-aa8264e6f9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409325845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1409325845
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1501343181
Short name T784
Test name
Test status
Simulation time 214324619 ps
CPU time 5.56 seconds
Started Mar 10 02:44:51 PM PDT 24
Finished Mar 10 02:44:56 PM PDT 24
Peak memory 214452 kb
Host smart-71e4434a-6994-4bd9-96d0-5d3499d7c8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501343181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1501343181
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1754316974
Short name T835
Test name
Test status
Simulation time 516503194 ps
CPU time 5.08 seconds
Started Mar 10 02:44:48 PM PDT 24
Finished Mar 10 02:44:53 PM PDT 24
Peak memory 208804 kb
Host smart-104f9320-b4bf-4301-a0bc-b14449b79a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754316974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1754316974
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2893670725
Short name T224
Test name
Test status
Simulation time 146153226 ps
CPU time 4.32 seconds
Started Mar 10 02:44:49 PM PDT 24
Finished Mar 10 02:44:54 PM PDT 24
Peak memory 220360 kb
Host smart-2847767c-b6fd-4171-81b0-04ef9db88c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893670725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2893670725
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.590835471
Short name T701
Test name
Test status
Simulation time 1253313940 ps
CPU time 38.11 seconds
Started Mar 10 02:44:50 PM PDT 24
Finished Mar 10 02:45:28 PM PDT 24
Peak memory 218352 kb
Host smart-b09ac609-d02e-4693-b7d4-e213bb822516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590835471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.590835471
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3858214849
Short name T615
Test name
Test status
Simulation time 111634984 ps
CPU time 2.83 seconds
Started Mar 10 02:44:49 PM PDT 24
Finished Mar 10 02:44:52 PM PDT 24
Peak memory 208020 kb
Host smart-ecc95286-d567-4dce-bc53-4c4a1cd0d754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858214849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3858214849
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.4131262085
Short name T333
Test name
Test status
Simulation time 251290305 ps
CPU time 7.45 seconds
Started Mar 10 02:44:50 PM PDT 24
Finished Mar 10 02:44:57 PM PDT 24
Peak memory 207944 kb
Host smart-5cea2ca5-385d-4ca5-8fa6-7ddc9ee44613
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131262085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.4131262085
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2343733160
Short name T708
Test name
Test status
Simulation time 79818883 ps
CPU time 3.65 seconds
Started Mar 10 02:44:49 PM PDT 24
Finished Mar 10 02:44:53 PM PDT 24
Peak memory 208452 kb
Host smart-5118a641-ca32-4a7b-88ef-1e211ffaefc0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343733160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2343733160
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1766720245
Short name T522
Test name
Test status
Simulation time 50417224 ps
CPU time 2.66 seconds
Started Mar 10 02:44:51 PM PDT 24
Finished Mar 10 02:44:53 PM PDT 24
Peak memory 206740 kb
Host smart-25761519-4649-4ed4-9d67-ff792dd50dd6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766720245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1766720245
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2915524423
Short name T721
Test name
Test status
Simulation time 156426257 ps
CPU time 1.86 seconds
Started Mar 10 02:44:48 PM PDT 24
Finished Mar 10 02:44:50 PM PDT 24
Peak memory 209888 kb
Host smart-8862962e-99e8-473e-af5c-9e5f78e5aee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915524423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2915524423
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.840901733
Short name T187
Test name
Test status
Simulation time 26154575 ps
CPU time 2.07 seconds
Started Mar 10 02:44:51 PM PDT 24
Finished Mar 10 02:44:53 PM PDT 24
Peak memory 208516 kb
Host smart-69ec6ac4-e2c0-4305-be09-c6463adf35ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840901733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.840901733
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3157424524
Short name T312
Test name
Test status
Simulation time 2913160127 ps
CPU time 53.56 seconds
Started Mar 10 02:44:53 PM PDT 24
Finished Mar 10 02:45:47 PM PDT 24
Peak memory 215716 kb
Host smart-583b40b1-244a-4359-b6a9-2b7214127714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157424524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3157424524
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3450504507
Short name T837
Test name
Test status
Simulation time 2199208578 ps
CPU time 49.08 seconds
Started Mar 10 02:44:52 PM PDT 24
Finished Mar 10 02:45:42 PM PDT 24
Peak memory 208892 kb
Host smart-6fdd34d0-364f-41db-a509-19d7c028dab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450504507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3450504507
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2204517757
Short name T53
Test name
Test status
Simulation time 7192977295 ps
CPU time 41.1 seconds
Started Mar 10 02:44:50 PM PDT 24
Finished Mar 10 02:45:31 PM PDT 24
Peak memory 211488 kb
Host smart-aa0464f7-bc06-4b6d-bfe2-a5ae48181842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204517757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2204517757
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3889934734
Short name T674
Test name
Test status
Simulation time 19599140 ps
CPU time 0.85 seconds
Started Mar 10 02:44:52 PM PDT 24
Finished Mar 10 02:44:53 PM PDT 24
Peak memory 206036 kb
Host smart-82d236a2-d53b-443a-b7b3-62ad663031fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889934734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3889934734
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1635269570
Short name T303
Test name
Test status
Simulation time 639211290 ps
CPU time 9.86 seconds
Started Mar 10 02:44:54 PM PDT 24
Finished Mar 10 02:45:04 PM PDT 24
Peak memory 216028 kb
Host smart-1394e3d2-d86d-4b36-aa30-089578891fd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635269570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1635269570
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1475179470
Short name T19
Test name
Test status
Simulation time 150895149 ps
CPU time 4.06 seconds
Started Mar 10 02:44:52 PM PDT 24
Finished Mar 10 02:44:56 PM PDT 24
Peak memory 222860 kb
Host smart-5e2f8a65-4d0b-4301-8f6b-9f4ad1d5e98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475179470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1475179470
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3465151956
Short name T775
Test name
Test status
Simulation time 59866252 ps
CPU time 2.58 seconds
Started Mar 10 02:44:54 PM PDT 24
Finished Mar 10 02:44:56 PM PDT 24
Peak memory 207356 kb
Host smart-33792235-c04e-4dd8-9f18-efff3b0d8fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465151956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3465151956
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2000212611
Short name T347
Test name
Test status
Simulation time 264796250 ps
CPU time 4.27 seconds
Started Mar 10 02:44:55 PM PDT 24
Finished Mar 10 02:44:59 PM PDT 24
Peak memory 214696 kb
Host smart-32d8c5a6-6066-425b-9452-6732a6fe138d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000212611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2000212611
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3050192002
Short name T284
Test name
Test status
Simulation time 97218246 ps
CPU time 2.29 seconds
Started Mar 10 02:44:52 PM PDT 24
Finished Mar 10 02:44:54 PM PDT 24
Peak memory 208836 kb
Host smart-e649cca0-7ae7-4c48-8615-a445e1fb6472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050192002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3050192002
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_random.3821783634
Short name T513
Test name
Test status
Simulation time 75444740 ps
CPU time 4.52 seconds
Started Mar 10 02:44:53 PM PDT 24
Finished Mar 10 02:44:57 PM PDT 24
Peak memory 209716 kb
Host smart-91a6d6e2-6198-41e6-8a69-4d6353847ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821783634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3821783634
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2505408898
Short name T713
Test name
Test status
Simulation time 471843410 ps
CPU time 4.01 seconds
Started Mar 10 02:44:52 PM PDT 24
Finished Mar 10 02:44:56 PM PDT 24
Peak memory 208836 kb
Host smart-dcb8833d-e855-495d-9477-9e28f4af5c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505408898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2505408898
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1722803453
Short name T650
Test name
Test status
Simulation time 315365756 ps
CPU time 4.96 seconds
Started Mar 10 02:44:54 PM PDT 24
Finished Mar 10 02:44:59 PM PDT 24
Peak memory 208524 kb
Host smart-509b535e-c523-4286-b114-06daa8cb3041
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722803453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1722803453
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1279703921
Short name T554
Test name
Test status
Simulation time 13760918705 ps
CPU time 78.74 seconds
Started Mar 10 02:44:52 PM PDT 24
Finished Mar 10 02:46:11 PM PDT 24
Peak memory 208400 kb
Host smart-0ff1147b-1e60-489b-aca0-f570b3b4156e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279703921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1279703921
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.159684634
Short name T840
Test name
Test status
Simulation time 551209709 ps
CPU time 3.56 seconds
Started Mar 10 02:44:52 PM PDT 24
Finished Mar 10 02:44:55 PM PDT 24
Peak memory 206896 kb
Host smart-3769a195-3c6d-4c80-8076-cc77338a6a61
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159684634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.159684634
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.170565675
Short name T845
Test name
Test status
Simulation time 125150124 ps
CPU time 2.33 seconds
Started Mar 10 02:44:54 PM PDT 24
Finished Mar 10 02:44:56 PM PDT 24
Peak memory 215540 kb
Host smart-e8f78231-edfb-4473-b206-438cd641b1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170565675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.170565675
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.986805247
Short name T81
Test name
Test status
Simulation time 92747355 ps
CPU time 3.32 seconds
Started Mar 10 02:44:49 PM PDT 24
Finished Mar 10 02:44:53 PM PDT 24
Peak memory 208576 kb
Host smart-cba98705-5dc6-4a1a-82f0-1305a95a5555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986805247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.986805247
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.428380432
Short name T183
Test name
Test status
Simulation time 1284148385 ps
CPU time 44.95 seconds
Started Mar 10 02:44:51 PM PDT 24
Finished Mar 10 02:45:36 PM PDT 24
Peak memory 216568 kb
Host smart-d1fa64e5-b9b4-48be-979e-0a81cb1b9bd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428380432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.428380432
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.4237734728
Short name T631
Test name
Test status
Simulation time 766118118 ps
CPU time 10.28 seconds
Started Mar 10 02:44:52 PM PDT 24
Finished Mar 10 02:45:02 PM PDT 24
Peak memory 208988 kb
Host smart-fcb0a5fa-385c-4363-8c04-c0dd18f27c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237734728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.4237734728
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2516817340
Short name T642
Test name
Test status
Simulation time 45375778 ps
CPU time 2.8 seconds
Started Mar 10 02:44:52 PM PDT 24
Finished Mar 10 02:44:55 PM PDT 24
Peak memory 210352 kb
Host smart-bdaf8f0b-c2be-4fed-b3ae-c18e7850e575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516817340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2516817340
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1910886469
Short name T814
Test name
Test status
Simulation time 42910902 ps
CPU time 0.89 seconds
Started Mar 10 02:44:57 PM PDT 24
Finished Mar 10 02:44:58 PM PDT 24
Peak memory 206164 kb
Host smart-d5036f1f-fe8a-40dc-90be-88162c64b96d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910886469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1910886469
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.702100002
Short name T696
Test name
Test status
Simulation time 308375663 ps
CPU time 3.59 seconds
Started Mar 10 02:44:54 PM PDT 24
Finished Mar 10 02:44:58 PM PDT 24
Peak memory 209452 kb
Host smart-b6633ea5-57cb-421f-9d43-bb724e9113e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702100002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.702100002
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3748262975
Short name T842
Test name
Test status
Simulation time 12603972786 ps
CPU time 33.81 seconds
Started Mar 10 02:44:55 PM PDT 24
Finished Mar 10 02:45:29 PM PDT 24
Peak memory 214620 kb
Host smart-1a11b684-aa57-4e82-9ec8-9284da720e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748262975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3748262975
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3964639496
Short name T893
Test name
Test status
Simulation time 37371213 ps
CPU time 2.74 seconds
Started Mar 10 02:44:53 PM PDT 24
Finished Mar 10 02:44:56 PM PDT 24
Peak memory 216204 kb
Host smart-42158cb8-6a19-4643-847c-db02c7ecb79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964639496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3964639496
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1592376660
Short name T243
Test name
Test status
Simulation time 2107382263 ps
CPU time 51.43 seconds
Started Mar 10 02:44:53 PM PDT 24
Finished Mar 10 02:45:44 PM PDT 24
Peak memory 208992 kb
Host smart-b382a47e-c8a0-40c8-a73a-94ad2e6b46b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592376660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1592376660
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1784951378
Short name T275
Test name
Test status
Simulation time 64817116 ps
CPU time 3.24 seconds
Started Mar 10 02:44:51 PM PDT 24
Finished Mar 10 02:44:54 PM PDT 24
Peak memory 208520 kb
Host smart-467247d1-2d52-4a63-9a09-6ad48d2b4cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784951378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1784951378
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2483838063
Short name T496
Test name
Test status
Simulation time 110627107 ps
CPU time 2.95 seconds
Started Mar 10 02:44:54 PM PDT 24
Finished Mar 10 02:44:57 PM PDT 24
Peak memory 206880 kb
Host smart-0a8f1312-2a25-4ded-a043-8f089b4f4b59
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483838063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2483838063
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3783537845
Short name T427
Test name
Test status
Simulation time 34007470 ps
CPU time 2.29 seconds
Started Mar 10 02:44:53 PM PDT 24
Finished Mar 10 02:44:56 PM PDT 24
Peak memory 206784 kb
Host smart-c5ab629e-a418-4c39-8d02-fd7b35dc6617
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783537845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3783537845
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2795494514
Short name T600
Test name
Test status
Simulation time 447073417 ps
CPU time 6.02 seconds
Started Mar 10 02:44:52 PM PDT 24
Finished Mar 10 02:44:58 PM PDT 24
Peak memory 208016 kb
Host smart-e5db3e38-aec3-4155-b442-eecbab04277b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795494514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2795494514
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1929586297
Short name T759
Test name
Test status
Simulation time 51520150 ps
CPU time 2.13 seconds
Started Mar 10 02:44:59 PM PDT 24
Finished Mar 10 02:45:01 PM PDT 24
Peak memory 207992 kb
Host smart-2984d62b-83ac-4d67-bc89-37f496249c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929586297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1929586297
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2858018010
Short name T523
Test name
Test status
Simulation time 119412480 ps
CPU time 2.8 seconds
Started Mar 10 02:44:54 PM PDT 24
Finished Mar 10 02:44:57 PM PDT 24
Peak memory 208460 kb
Host smart-69fb51fb-787f-4c52-ac36-72b89c98f71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858018010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2858018010
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2039852969
Short name T863
Test name
Test status
Simulation time 15889191967 ps
CPU time 97.35 seconds
Started Mar 10 02:44:57 PM PDT 24
Finished Mar 10 02:46:35 PM PDT 24
Peak memory 219020 kb
Host smart-359d50d1-86e0-483b-82c7-4fb62cffa7df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039852969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2039852969
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2065530024
Short name T844
Test name
Test status
Simulation time 81172771 ps
CPU time 1.79 seconds
Started Mar 10 02:44:59 PM PDT 24
Finished Mar 10 02:45:01 PM PDT 24
Peak memory 209944 kb
Host smart-8bcdbad5-22a1-4e35-a467-84fa5609d088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065530024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2065530024
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1925175461
Short name T433
Test name
Test status
Simulation time 28619132 ps
CPU time 0.91 seconds
Started Mar 10 02:45:03 PM PDT 24
Finished Mar 10 02:45:04 PM PDT 24
Peak memory 206332 kb
Host smart-fddcec8d-eca8-414d-ac7d-e99c2c276323
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925175461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1925175461
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2542189560
Short name T244
Test name
Test status
Simulation time 11700508921 ps
CPU time 125.25 seconds
Started Mar 10 02:44:59 PM PDT 24
Finished Mar 10 02:47:04 PM PDT 24
Peak memory 215032 kb
Host smart-827b0a7a-0938-4952-a4b0-ed48a928ba6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2542189560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2542189560
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1687771050
Short name T740
Test name
Test status
Simulation time 63684793 ps
CPU time 3.77 seconds
Started Mar 10 02:45:02 PM PDT 24
Finished Mar 10 02:45:06 PM PDT 24
Peak memory 210272 kb
Host smart-5a9ad686-27aa-41fc-b3e4-13b3471d9084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687771050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1687771050
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1266005327
Short name T719
Test name
Test status
Simulation time 1843092980 ps
CPU time 16.32 seconds
Started Mar 10 02:45:00 PM PDT 24
Finished Mar 10 02:45:17 PM PDT 24
Peak memory 218284 kb
Host smart-d00fb16b-9e50-4d68-a6a5-ee5da79241de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266005327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1266005327
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.133863193
Short name T194
Test name
Test status
Simulation time 228515669 ps
CPU time 6.59 seconds
Started Mar 10 02:45:04 PM PDT 24
Finished Mar 10 02:45:10 PM PDT 24
Peak memory 209252 kb
Host smart-dc76c153-2c85-4401-a87e-47bd2ef202cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133863193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.133863193
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3062133780
Short name T591
Test name
Test status
Simulation time 120918550 ps
CPU time 5.72 seconds
Started Mar 10 02:45:03 PM PDT 24
Finished Mar 10 02:45:08 PM PDT 24
Peak memory 214572 kb
Host smart-c06de137-8f42-46e5-aa50-5dea5e1c74c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062133780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3062133780
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1091439812
Short name T777
Test name
Test status
Simulation time 2124083199 ps
CPU time 38.1 seconds
Started Mar 10 02:44:57 PM PDT 24
Finished Mar 10 02:45:35 PM PDT 24
Peak memory 208844 kb
Host smart-3cc5edb5-23fb-458c-96bc-b315c92db110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091439812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1091439812
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.1845013470
Short name T878
Test name
Test status
Simulation time 2796031794 ps
CPU time 9.89 seconds
Started Mar 10 02:44:57 PM PDT 24
Finished Mar 10 02:45:07 PM PDT 24
Peak memory 208596 kb
Host smart-0c2dce9c-e654-4714-a995-162a47dad95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845013470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1845013470
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.4013071437
Short name T606
Test name
Test status
Simulation time 97558717 ps
CPU time 4.13 seconds
Started Mar 10 02:45:04 PM PDT 24
Finished Mar 10 02:45:08 PM PDT 24
Peak memory 206848 kb
Host smart-ed0a62fd-923b-4c43-a8f5-8bcf17c220f4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013071437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.4013071437
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3940100670
Short name T517
Test name
Test status
Simulation time 212431014 ps
CPU time 7.66 seconds
Started Mar 10 02:45:04 PM PDT 24
Finished Mar 10 02:45:12 PM PDT 24
Peak memory 207844 kb
Host smart-12654787-69a3-42a4-ac8b-975295e7c37c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940100670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3940100670
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2024177424
Short name T618
Test name
Test status
Simulation time 381155578 ps
CPU time 12.76 seconds
Started Mar 10 02:45:01 PM PDT 24
Finished Mar 10 02:45:13 PM PDT 24
Peak memory 208492 kb
Host smart-15c74ae9-964d-47b7-ba5d-fc77138cd02d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024177424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2024177424
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.4095302921
Short name T389
Test name
Test status
Simulation time 298820109 ps
CPU time 3.89 seconds
Started Mar 10 02:45:04 PM PDT 24
Finished Mar 10 02:45:08 PM PDT 24
Peak memory 215828 kb
Host smart-baf342af-3930-4706-a77c-dfcc65df03b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095302921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.4095302921
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.433778859
Short name T476
Test name
Test status
Simulation time 193098258 ps
CPU time 2.62 seconds
Started Mar 10 02:45:01 PM PDT 24
Finished Mar 10 02:45:03 PM PDT 24
Peak memory 207048 kb
Host smart-0d3f2dcd-64f1-4acd-8ab8-f9e59db09410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433778859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.433778859
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.783274793
Short name T128
Test name
Test status
Simulation time 218737757 ps
CPU time 9.18 seconds
Started Mar 10 02:45:02 PM PDT 24
Finished Mar 10 02:45:12 PM PDT 24
Peak memory 220700 kb
Host smart-f72b4ba0-234d-40aa-b426-c2b846427c03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783274793 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.783274793
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1960553810
Short name T193
Test name
Test status
Simulation time 579331631 ps
CPU time 3.86 seconds
Started Mar 10 02:45:04 PM PDT 24
Finished Mar 10 02:45:08 PM PDT 24
Peak memory 207416 kb
Host smart-0be7f55d-ba87-44d1-a05a-74444eb8f4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960553810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1960553810
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2122987107
Short name T593
Test name
Test status
Simulation time 60630445 ps
CPU time 2.69 seconds
Started Mar 10 02:45:08 PM PDT 24
Finished Mar 10 02:45:11 PM PDT 24
Peak memory 209868 kb
Host smart-53cf63a1-9166-439d-98c8-24233b0481a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122987107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2122987107
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.627696754
Short name T883
Test name
Test status
Simulation time 7744727 ps
CPU time 0.75 seconds
Started Mar 10 02:45:13 PM PDT 24
Finished Mar 10 02:45:14 PM PDT 24
Peak memory 206076 kb
Host smart-7a72835e-a78c-475e-a042-dde749a6c9e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627696754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.627696754
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2434428545
Short name T507
Test name
Test status
Simulation time 200068885 ps
CPU time 4.66 seconds
Started Mar 10 02:45:10 PM PDT 24
Finished Mar 10 02:45:15 PM PDT 24
Peak memory 209972 kb
Host smart-1e1eeb68-d95f-43b5-8d6f-e5e1f79acf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434428545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2434428545
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3964216202
Short name T730
Test name
Test status
Simulation time 18548242 ps
CPU time 1.52 seconds
Started Mar 10 02:45:04 PM PDT 24
Finished Mar 10 02:45:06 PM PDT 24
Peak memory 208144 kb
Host smart-ab66caae-4881-45c1-bdb4-13dfcc456d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964216202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3964216202
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3506320504
Short name T800
Test name
Test status
Simulation time 1663601701 ps
CPU time 52.79 seconds
Started Mar 10 02:45:08 PM PDT 24
Finished Mar 10 02:46:01 PM PDT 24
Peak memory 214532 kb
Host smart-2c3c6537-1720-492f-9bd1-cd5ecb7b1152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506320504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3506320504
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1128776505
Short name T264
Test name
Test status
Simulation time 524895530 ps
CPU time 3.45 seconds
Started Mar 10 02:45:13 PM PDT 24
Finished Mar 10 02:45:17 PM PDT 24
Peak memory 209676 kb
Host smart-15d7d96c-da71-49c1-b7e8-53ebcc1aac5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128776505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1128776505
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1341536793
Short name T823
Test name
Test status
Simulation time 165475718 ps
CPU time 6.21 seconds
Started Mar 10 02:45:05 PM PDT 24
Finished Mar 10 02:45:11 PM PDT 24
Peak memory 214476 kb
Host smart-494602f7-ca0b-4e4e-b92a-b837a1263b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341536793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1341536793
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.409210211
Short name T396
Test name
Test status
Simulation time 130804353 ps
CPU time 2.52 seconds
Started Mar 10 02:45:01 PM PDT 24
Finished Mar 10 02:45:04 PM PDT 24
Peak memory 207484 kb
Host smart-044b0354-f244-46e1-861c-4d253819d883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409210211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.409210211
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2849231542
Short name T463
Test name
Test status
Simulation time 109596890 ps
CPU time 2.46 seconds
Started Mar 10 02:45:02 PM PDT 24
Finished Mar 10 02:45:04 PM PDT 24
Peak memory 206792 kb
Host smart-67536daf-d3ed-47d9-9977-0a85c79647b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849231542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2849231542
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1302143668
Short name T487
Test name
Test status
Simulation time 289644963 ps
CPU time 4.73 seconds
Started Mar 10 02:45:02 PM PDT 24
Finished Mar 10 02:45:07 PM PDT 24
Peak memory 206820 kb
Host smart-8e0d3465-b75f-49f0-9440-745af8fc2a4f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302143668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1302143668
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1827780209
Short name T301
Test name
Test status
Simulation time 4740713361 ps
CPU time 32.73 seconds
Started Mar 10 02:45:03 PM PDT 24
Finished Mar 10 02:45:36 PM PDT 24
Peak memory 208784 kb
Host smart-f0dc776b-124f-4fff-a785-f3af4d7ace72
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827780209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1827780209
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.4150160932
Short name T652
Test name
Test status
Simulation time 374254266 ps
CPU time 3.8 seconds
Started Mar 10 02:45:09 PM PDT 24
Finished Mar 10 02:45:13 PM PDT 24
Peak memory 208444 kb
Host smart-4a2e65e9-0ab5-47b6-817a-c1487180a29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150160932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.4150160932
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1413787420
Short name T477
Test name
Test status
Simulation time 336386894 ps
CPU time 3.82 seconds
Started Mar 10 02:45:06 PM PDT 24
Finished Mar 10 02:45:10 PM PDT 24
Peak memory 208612 kb
Host smart-9c760c11-3c6c-4966-9b74-7f48990a46d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413787420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1413787420
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.4064229687
Short name T330
Test name
Test status
Simulation time 14514535901 ps
CPU time 45.97 seconds
Started Mar 10 02:45:09 PM PDT 24
Finished Mar 10 02:45:55 PM PDT 24
Peak memory 221648 kb
Host smart-ae987cd0-c979-4ddf-9d1b-e680fe078243
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064229687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.4064229687
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.10477130
Short name T846
Test name
Test status
Simulation time 860855102 ps
CPU time 7.21 seconds
Started Mar 10 02:45:12 PM PDT 24
Finished Mar 10 02:45:20 PM PDT 24
Peak memory 207556 kb
Host smart-b29abdf8-6a1d-45ae-96b2-731ceb03b0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10477130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.10477130
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1928835954
Short name T59
Test name
Test status
Simulation time 54959744 ps
CPU time 2.81 seconds
Started Mar 10 02:45:07 PM PDT 24
Finished Mar 10 02:45:10 PM PDT 24
Peak memory 210416 kb
Host smart-d6d3d01a-02c1-4838-b795-4f3580ceae6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928835954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1928835954
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3312861023
Short name T760
Test name
Test status
Simulation time 19557654 ps
CPU time 0.85 seconds
Started Mar 10 02:45:20 PM PDT 24
Finished Mar 10 02:45:21 PM PDT 24
Peak memory 206168 kb
Host smart-8215d8f0-0a0a-4c88-b4f4-603f8955b354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312861023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3312861023
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3852414409
Short name T405
Test name
Test status
Simulation time 57117954 ps
CPU time 3.69 seconds
Started Mar 10 02:45:14 PM PDT 24
Finished Mar 10 02:45:18 PM PDT 24
Peak memory 215816 kb
Host smart-60afd5d6-677e-4c1f-9e90-cefcce0c49b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852414409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3852414409
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3667893584
Short name T584
Test name
Test status
Simulation time 5441817408 ps
CPU time 36.23 seconds
Started Mar 10 02:45:09 PM PDT 24
Finished Mar 10 02:45:45 PM PDT 24
Peak memory 208048 kb
Host smart-096bfab8-6fd1-4409-a2a6-af314b39bf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667893584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3667893584
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2723946348
Short name T255
Test name
Test status
Simulation time 5033457444 ps
CPU time 33.9 seconds
Started Mar 10 02:45:08 PM PDT 24
Finished Mar 10 02:45:42 PM PDT 24
Peak memory 222608 kb
Host smart-76ad89ac-ed55-4a7e-917c-9bbc692ec7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723946348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2723946348
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1936248679
Short name T341
Test name
Test status
Simulation time 1882866652 ps
CPU time 8.44 seconds
Started Mar 10 02:45:09 PM PDT 24
Finished Mar 10 02:45:18 PM PDT 24
Peak memory 222596 kb
Host smart-242abb37-66df-484e-86ab-e06c749ffe3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936248679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1936248679
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.60222180
Short name T230
Test name
Test status
Simulation time 63266570 ps
CPU time 3.23 seconds
Started Mar 10 02:45:08 PM PDT 24
Finished Mar 10 02:45:11 PM PDT 24
Peak memory 220496 kb
Host smart-dff83827-4658-4876-b893-9534745bb15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60222180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.60222180
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3793513994
Short name T896
Test name
Test status
Simulation time 106157680 ps
CPU time 5.32 seconds
Started Mar 10 02:45:08 PM PDT 24
Finished Mar 10 02:45:13 PM PDT 24
Peak memory 218608 kb
Host smart-dfb14895-8742-4617-bffe-56de0ce6e595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793513994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3793513994
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.745951361
Short name T720
Test name
Test status
Simulation time 1012743685 ps
CPU time 7.42 seconds
Started Mar 10 02:45:13 PM PDT 24
Finished Mar 10 02:45:21 PM PDT 24
Peak memory 207892 kb
Host smart-48cf4730-d37c-484f-8869-32d699fcd1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745951361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.745951361
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2941841365
Short name T653
Test name
Test status
Simulation time 1495041335 ps
CPU time 39.33 seconds
Started Mar 10 02:45:06 PM PDT 24
Finished Mar 10 02:45:45 PM PDT 24
Peak memory 208984 kb
Host smart-418e7685-d502-4819-8864-5fdc1b15a8d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941841365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2941841365
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.4271207168
Short name T728
Test name
Test status
Simulation time 334623066 ps
CPU time 6.75 seconds
Started Mar 10 02:45:13 PM PDT 24
Finished Mar 10 02:45:20 PM PDT 24
Peak memory 208592 kb
Host smart-65622816-3063-480c-8bad-55bed5e02993
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271207168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.4271207168
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3296556834
Short name T440
Test name
Test status
Simulation time 95281684 ps
CPU time 4.37 seconds
Started Mar 10 02:45:07 PM PDT 24
Finished Mar 10 02:45:11 PM PDT 24
Peak memory 208796 kb
Host smart-9beff9ea-8885-43d2-bac1-eb52552fedfc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296556834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3296556834
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2495933652
Short name T852
Test name
Test status
Simulation time 34672388 ps
CPU time 2.59 seconds
Started Mar 10 02:45:07 PM PDT 24
Finished Mar 10 02:45:10 PM PDT 24
Peak memory 215812 kb
Host smart-0e9560e8-5734-4b00-9ca8-88a239609a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495933652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2495933652
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.594447493
Short name T656
Test name
Test status
Simulation time 196754978 ps
CPU time 6.85 seconds
Started Mar 10 02:45:14 PM PDT 24
Finished Mar 10 02:45:21 PM PDT 24
Peak memory 208424 kb
Host smart-8c42ddd2-a773-44fc-8c36-b388cec3e8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594447493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.594447493
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1346371183
Short name T550
Test name
Test status
Simulation time 4090359593 ps
CPU time 39.98 seconds
Started Mar 10 02:45:16 PM PDT 24
Finished Mar 10 02:45:57 PM PDT 24
Peak memory 218092 kb
Host smart-45b1ef6d-7308-4a3f-a1c6-107d44d120c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346371183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1346371183
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.847222798
Short name T821
Test name
Test status
Simulation time 316428773 ps
CPU time 4.2 seconds
Started Mar 10 02:45:12 PM PDT 24
Finished Mar 10 02:45:17 PM PDT 24
Peak memory 207116 kb
Host smart-da070293-6597-4b98-a6d5-105681b9a42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847222798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.847222798
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1326059033
Short name T379
Test name
Test status
Simulation time 242205117 ps
CPU time 2.8 seconds
Started Mar 10 02:45:13 PM PDT 24
Finished Mar 10 02:45:16 PM PDT 24
Peak memory 210120 kb
Host smart-d1e540a0-c089-43d9-9328-64ed65fee34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326059033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1326059033
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2687355230
Short name T624
Test name
Test status
Simulation time 10694822 ps
CPU time 0.86 seconds
Started Mar 10 02:45:19 PM PDT 24
Finished Mar 10 02:45:20 PM PDT 24
Peak memory 206160 kb
Host smart-26da842b-927c-431a-9445-9f8d48b29bdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687355230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2687355230
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3737186670
Short name T387
Test name
Test status
Simulation time 213617783 ps
CPU time 4.05 seconds
Started Mar 10 02:45:12 PM PDT 24
Finished Mar 10 02:45:17 PM PDT 24
Peak memory 215044 kb
Host smart-79282f37-00a4-49e7-89e3-990ca33a473a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3737186670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3737186670
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2287086105
Short name T9
Test name
Test status
Simulation time 93702239 ps
CPU time 3.56 seconds
Started Mar 10 02:45:19 PM PDT 24
Finished Mar 10 02:45:23 PM PDT 24
Peak memory 217380 kb
Host smart-b2296b99-633e-4ccc-a6a7-dcee3479b55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287086105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2287086105
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2044943435
Short name T73
Test name
Test status
Simulation time 883453674 ps
CPU time 15.6 seconds
Started Mar 10 02:45:12 PM PDT 24
Finished Mar 10 02:45:27 PM PDT 24
Peak memory 214540 kb
Host smart-b7ec35bc-be99-4ea5-a3f2-22cc733b5b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044943435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2044943435
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2287451162
Short name T790
Test name
Test status
Simulation time 139313776 ps
CPU time 5.9 seconds
Started Mar 10 02:45:13 PM PDT 24
Finished Mar 10 02:45:19 PM PDT 24
Peak memory 210056 kb
Host smart-2819a9b7-8175-4b48-8a67-0b4eacca1204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287451162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2287451162
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1831797176
Short name T671
Test name
Test status
Simulation time 121602222 ps
CPU time 4.38 seconds
Started Mar 10 02:45:13 PM PDT 24
Finished Mar 10 02:45:17 PM PDT 24
Peak memory 211340 kb
Host smart-586074c5-b9d4-4681-a84a-d64b3c6e8690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831797176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1831797176
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2986600277
Short name T565
Test name
Test status
Simulation time 163599390 ps
CPU time 5.27 seconds
Started Mar 10 02:45:14 PM PDT 24
Finished Mar 10 02:45:19 PM PDT 24
Peak memory 209524 kb
Host smart-63ce23fe-4c3b-429a-93f5-2f08aa119b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986600277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2986600277
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2345496658
Short name T247
Test name
Test status
Simulation time 210549771 ps
CPU time 3.38 seconds
Started Mar 10 02:45:11 PM PDT 24
Finished Mar 10 02:45:15 PM PDT 24
Peak memory 207700 kb
Host smart-2d2635e1-3010-425d-9b41-7682fdce6d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345496658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2345496658
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.364076810
Short name T459
Test name
Test status
Simulation time 1286179115 ps
CPU time 9.33 seconds
Started Mar 10 02:45:15 PM PDT 24
Finished Mar 10 02:45:25 PM PDT 24
Peak memory 208528 kb
Host smart-62f9dd86-d577-47b2-8d26-8b2ad2ec980a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364076810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.364076810
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2438842903
Short name T453
Test name
Test status
Simulation time 222196872 ps
CPU time 8.32 seconds
Started Mar 10 02:45:12 PM PDT 24
Finished Mar 10 02:45:21 PM PDT 24
Peak memory 207856 kb
Host smart-8bb1a66e-56db-49f5-9c9e-7ba199841183
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438842903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2438842903
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.617182718
Short name T793
Test name
Test status
Simulation time 64800448 ps
CPU time 3.25 seconds
Started Mar 10 02:45:11 PM PDT 24
Finished Mar 10 02:45:14 PM PDT 24
Peak memory 206788 kb
Host smart-0c1d6538-bc57-43ef-a438-169f69a6d60a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617182718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.617182718
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2404959565
Short name T475
Test name
Test status
Simulation time 37799298 ps
CPU time 1.76 seconds
Started Mar 10 02:45:12 PM PDT 24
Finished Mar 10 02:45:14 PM PDT 24
Peak memory 206816 kb
Host smart-7b406ce7-4343-4462-9e3d-195324b3a5eb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404959565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2404959565
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2331866818
Short name T196
Test name
Test status
Simulation time 1225871519 ps
CPU time 3.39 seconds
Started Mar 10 02:45:14 PM PDT 24
Finished Mar 10 02:45:18 PM PDT 24
Peak memory 209880 kb
Host smart-0ad117b7-b031-47c6-a9e2-1b6ad0f2482a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331866818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2331866818
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.308237449
Short name T578
Test name
Test status
Simulation time 96843896 ps
CPU time 1.83 seconds
Started Mar 10 02:45:13 PM PDT 24
Finished Mar 10 02:45:15 PM PDT 24
Peak memory 206840 kb
Host smart-b639b21c-9ff9-48a1-952d-6878d53204d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308237449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.308237449
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3922384015
Short name T325
Test name
Test status
Simulation time 1266461664 ps
CPU time 31.31 seconds
Started Mar 10 02:45:18 PM PDT 24
Finished Mar 10 02:45:49 PM PDT 24
Peak memory 216120 kb
Host smart-9edeb9db-f9be-4f48-bbae-e9a83849391b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922384015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3922384015
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.314046410
Short name T186
Test name
Test status
Simulation time 60101096 ps
CPU time 2.72 seconds
Started Mar 10 02:45:10 PM PDT 24
Finished Mar 10 02:45:13 PM PDT 24
Peak memory 210024 kb
Host smart-fd3ef21a-596c-42b8-bb30-c9aa3dfbcbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314046410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.314046410
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.414141333
Short name T526
Test name
Test status
Simulation time 116512036 ps
CPU time 0.73 seconds
Started Mar 10 02:45:20 PM PDT 24
Finished Mar 10 02:45:21 PM PDT 24
Peak memory 206032 kb
Host smart-b750e21e-22f2-4f4c-89d1-b020ad5dc3b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414141333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.414141333
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.655395124
Short name T429
Test name
Test status
Simulation time 185580857 ps
CPU time 2.53 seconds
Started Mar 10 02:45:17 PM PDT 24
Finished Mar 10 02:45:19 PM PDT 24
Peak memory 209776 kb
Host smart-fe9bbe00-2a77-4d54-88f5-52739657ba70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655395124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.655395124
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2916108998
Short name T364
Test name
Test status
Simulation time 156947908 ps
CPU time 4.85 seconds
Started Mar 10 02:45:19 PM PDT 24
Finished Mar 10 02:45:24 PM PDT 24
Peak memory 214508 kb
Host smart-2a2b26be-69bc-4248-880b-e71636026ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916108998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2916108998
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.771665050
Short name T228
Test name
Test status
Simulation time 354433463 ps
CPU time 3.54 seconds
Started Mar 10 02:45:20 PM PDT 24
Finished Mar 10 02:45:24 PM PDT 24
Peak memory 209832 kb
Host smart-72b703d2-4353-4aca-91a3-b511f1e51f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771665050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.771665050
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.38031277
Short name T586
Test name
Test status
Simulation time 65630705 ps
CPU time 3.62 seconds
Started Mar 10 02:45:20 PM PDT 24
Finished Mar 10 02:45:23 PM PDT 24
Peak memory 209916 kb
Host smart-44074635-f413-42b2-834b-7cd2bc2b6f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38031277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.38031277
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.4277961229
Short name T307
Test name
Test status
Simulation time 273282419 ps
CPU time 4.74 seconds
Started Mar 10 02:45:23 PM PDT 24
Finished Mar 10 02:45:28 PM PDT 24
Peak memory 207980 kb
Host smart-d94b931b-6424-4a53-b83f-a6bb04f8ecb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277961229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.4277961229
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3697423815
Short name T756
Test name
Test status
Simulation time 1273545790 ps
CPU time 9.76 seconds
Started Mar 10 02:45:16 PM PDT 24
Finished Mar 10 02:45:26 PM PDT 24
Peak memory 208752 kb
Host smart-49cb7a9f-b31d-4f80-b302-f8813ee60865
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697423815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3697423815
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.67685691
Short name T546
Test name
Test status
Simulation time 894169507 ps
CPU time 9.77 seconds
Started Mar 10 02:45:17 PM PDT 24
Finished Mar 10 02:45:27 PM PDT 24
Peak memory 209028 kb
Host smart-c4913d18-d245-444c-b668-c5d5f7cdd842
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67685691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.67685691
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.469548106
Short name T213
Test name
Test status
Simulation time 143859672 ps
CPU time 2.51 seconds
Started Mar 10 02:45:18 PM PDT 24
Finished Mar 10 02:45:21 PM PDT 24
Peak memory 206844 kb
Host smart-ce7c052f-ea1d-46cc-bff3-3bd8f3dc5c67
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469548106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.469548106
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.424756733
Short name T616
Test name
Test status
Simulation time 81206848 ps
CPU time 1.53 seconds
Started Mar 10 02:45:19 PM PDT 24
Finished Mar 10 02:45:21 PM PDT 24
Peak memory 207664 kb
Host smart-d1b9acbc-5630-49e1-a2b4-0edc89d31375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424756733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.424756733
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2732488894
Short name T541
Test name
Test status
Simulation time 246461750 ps
CPU time 2.07 seconds
Started Mar 10 02:45:19 PM PDT 24
Finished Mar 10 02:45:21 PM PDT 24
Peak memory 208444 kb
Host smart-952fbb22-c264-4aae-bc17-17493d6d6179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732488894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2732488894
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3748372870
Short name T229
Test name
Test status
Simulation time 2297611441 ps
CPU time 56.41 seconds
Started Mar 10 02:45:18 PM PDT 24
Finished Mar 10 02:46:15 PM PDT 24
Peak memory 222772 kb
Host smart-47080315-bbdd-430f-b4c7-55351901153a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748372870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3748372870
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1721248662
Short name T191
Test name
Test status
Simulation time 1095650718 ps
CPU time 4.53 seconds
Started Mar 10 02:45:22 PM PDT 24
Finished Mar 10 02:45:26 PM PDT 24
Peak memory 207588 kb
Host smart-26cf7317-553e-4a2d-88f3-29afa98c7d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721248662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1721248662
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.4105089434
Short name T829
Test name
Test status
Simulation time 146060479 ps
CPU time 2.52 seconds
Started Mar 10 02:45:14 PM PDT 24
Finished Mar 10 02:45:17 PM PDT 24
Peak memory 210240 kb
Host smart-79960c77-78f8-4ce4-b872-e93336e9165a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105089434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.4105089434
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3974817575
Short name T683
Test name
Test status
Simulation time 49338273 ps
CPU time 0.98 seconds
Started Mar 10 02:45:24 PM PDT 24
Finished Mar 10 02:45:25 PM PDT 24
Peak memory 206104 kb
Host smart-2d2a44fa-d443-4876-af1c-822006e971ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974817575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3974817575
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2245758595
Short name T431
Test name
Test status
Simulation time 387622216 ps
CPU time 4.88 seconds
Started Mar 10 02:45:22 PM PDT 24
Finished Mar 10 02:45:27 PM PDT 24
Peak memory 207892 kb
Host smart-bc84df79-453f-4553-94e4-dd18f2321fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245758595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2245758595
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2319124056
Short name T746
Test name
Test status
Simulation time 425793847 ps
CPU time 4.74 seconds
Started Mar 10 02:45:22 PM PDT 24
Finished Mar 10 02:45:27 PM PDT 24
Peak memory 208852 kb
Host smart-4bf84ce5-ee3a-4d1d-8d54-6953f7d18205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319124056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2319124056
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3737551617
Short name T286
Test name
Test status
Simulation time 47165161 ps
CPU time 3.05 seconds
Started Mar 10 02:45:25 PM PDT 24
Finished Mar 10 02:45:28 PM PDT 24
Peak memory 209300 kb
Host smart-4381ff6a-2a73-43a0-a83e-b6f9f664821b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737551617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3737551617
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2614023718
Short name T52
Test name
Test status
Simulation time 609518925 ps
CPU time 5.86 seconds
Started Mar 10 02:45:22 PM PDT 24
Finished Mar 10 02:45:28 PM PDT 24
Peak memory 209804 kb
Host smart-bb2d9248-c31f-4a35-a926-4a373b69b16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614023718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2614023718
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1117293804
Short name T371
Test name
Test status
Simulation time 105687506 ps
CPU time 2.19 seconds
Started Mar 10 02:45:23 PM PDT 24
Finished Mar 10 02:45:26 PM PDT 24
Peak memory 207476 kb
Host smart-bd3c8adb-5cde-4d54-9e83-d1dcdded4b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117293804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1117293804
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.143674361
Short name T245
Test name
Test status
Simulation time 155780223 ps
CPU time 2.44 seconds
Started Mar 10 02:45:21 PM PDT 24
Finished Mar 10 02:45:24 PM PDT 24
Peak memory 206656 kb
Host smart-69830b01-f168-459b-93dc-bd81e2d13c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143674361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.143674361
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1927699268
Short name T619
Test name
Test status
Simulation time 93231439 ps
CPU time 2.7 seconds
Started Mar 10 02:45:25 PM PDT 24
Finished Mar 10 02:45:27 PM PDT 24
Peak memory 206804 kb
Host smart-37e30d4c-3568-404a-bcb2-758c0d6ab5a3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927699268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1927699268
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3381110875
Short name T334
Test name
Test status
Simulation time 315245632 ps
CPU time 6.53 seconds
Started Mar 10 02:45:23 PM PDT 24
Finished Mar 10 02:45:29 PM PDT 24
Peak memory 208092 kb
Host smart-ae7cd529-2a09-4db2-b91d-fc0750454358
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381110875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3381110875
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2948586268
Short name T778
Test name
Test status
Simulation time 161196058 ps
CPU time 2.82 seconds
Started Mar 10 02:45:21 PM PDT 24
Finished Mar 10 02:45:25 PM PDT 24
Peak memory 208304 kb
Host smart-32562bca-e724-4392-8728-1298e4a962d4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948586268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2948586268
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.3574425935
Short name T540
Test name
Test status
Simulation time 84017632 ps
CPU time 2.94 seconds
Started Mar 10 02:45:23 PM PDT 24
Finished Mar 10 02:45:26 PM PDT 24
Peak memory 214604 kb
Host smart-82f246ad-5983-414a-b0f8-2a78ace39f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574425935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3574425935
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.4022006376
Short name T673
Test name
Test status
Simulation time 227393713 ps
CPU time 5.7 seconds
Started Mar 10 02:45:18 PM PDT 24
Finished Mar 10 02:45:23 PM PDT 24
Peak memory 208484 kb
Host smart-e20bb5b0-51a6-4828-bb3c-556798ce2cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022006376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.4022006376
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2463934714
Short name T567
Test name
Test status
Simulation time 6022919898 ps
CPU time 31.15 seconds
Started Mar 10 02:45:26 PM PDT 24
Finished Mar 10 02:45:57 PM PDT 24
Peak memory 216968 kb
Host smart-6c8a03c6-846e-4936-b1dd-1ad00258f02c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463934714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2463934714
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.4043379033
Short name T532
Test name
Test status
Simulation time 155932155 ps
CPU time 5.93 seconds
Started Mar 10 02:45:20 PM PDT 24
Finished Mar 10 02:45:27 PM PDT 24
Peak memory 207852 kb
Host smart-2556fcf6-0d27-4f78-bb8e-765e3dd30c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043379033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.4043379033
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3029693728
Short name T495
Test name
Test status
Simulation time 24682035 ps
CPU time 0.76 seconds
Started Mar 10 02:42:32 PM PDT 24
Finished Mar 10 02:42:33 PM PDT 24
Peak memory 206172 kb
Host smart-9a49231b-d56f-4e7a-a150-75735993de18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029693728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3029693728
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.4199766694
Short name T401
Test name
Test status
Simulation time 483478641 ps
CPU time 3.45 seconds
Started Mar 10 02:42:29 PM PDT 24
Finished Mar 10 02:42:33 PM PDT 24
Peak memory 214520 kb
Host smart-b3ac6d7d-13ba-4c8c-854d-b5fef490c673
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4199766694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.4199766694
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2903545214
Short name T28
Test name
Test status
Simulation time 3776992047 ps
CPU time 25.93 seconds
Started Mar 10 02:42:33 PM PDT 24
Finished Mar 10 02:42:59 PM PDT 24
Peak memory 222760 kb
Host smart-e4f01bec-a798-405d-9542-79b89fcb8ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903545214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2903545214
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2938200983
Short name T645
Test name
Test status
Simulation time 634715511 ps
CPU time 4.25 seconds
Started Mar 10 02:42:26 PM PDT 24
Finished Mar 10 02:42:31 PM PDT 24
Peak memory 210312 kb
Host smart-c32050b9-83fc-4f22-967b-d0287d38af7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938200983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2938200983
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.399195773
Short name T629
Test name
Test status
Simulation time 99179858 ps
CPU time 3.47 seconds
Started Mar 10 02:42:29 PM PDT 24
Finished Mar 10 02:42:33 PM PDT 24
Peak memory 222764 kb
Host smart-400a8555-ca00-484e-b6e1-34fbbded8645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399195773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.399195773
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2518288064
Short name T691
Test name
Test status
Simulation time 984882929 ps
CPU time 7.81 seconds
Started Mar 10 02:42:27 PM PDT 24
Finished Mar 10 02:42:36 PM PDT 24
Peak memory 214368 kb
Host smart-78dd02ae-4837-4ebb-a8f5-f552983a64fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518288064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2518288064
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3223822008
Short name T13
Test name
Test status
Simulation time 12127409333 ps
CPU time 130.67 seconds
Started Mar 10 02:42:33 PM PDT 24
Finished Mar 10 02:44:44 PM PDT 24
Peak memory 257284 kb
Host smart-17db0a14-70ab-40b5-804e-2eb17c1e3286
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223822008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3223822008
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3548269458
Short name T560
Test name
Test status
Simulation time 913662998 ps
CPU time 7.06 seconds
Started Mar 10 02:42:26 PM PDT 24
Finished Mar 10 02:42:34 PM PDT 24
Peak memory 206780 kb
Host smart-07516c47-7d9c-4cfc-a149-13b819619f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548269458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3548269458
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1585164736
Short name T438
Test name
Test status
Simulation time 167105671 ps
CPU time 3.27 seconds
Started Mar 10 02:42:28 PM PDT 24
Finished Mar 10 02:42:32 PM PDT 24
Peak memory 206864 kb
Host smart-5771d3c1-9382-4ef5-889f-66e74a7f22d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585164736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1585164736
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3529717195
Short name T884
Test name
Test status
Simulation time 141529870 ps
CPU time 4.38 seconds
Started Mar 10 02:42:28 PM PDT 24
Finished Mar 10 02:42:33 PM PDT 24
Peak memory 208600 kb
Host smart-22a6df6d-d007-4443-9dfc-ad41a6ea4a4d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529717195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3529717195
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2088790974
Short name T485
Test name
Test status
Simulation time 67620902 ps
CPU time 3.38 seconds
Started Mar 10 02:42:27 PM PDT 24
Finished Mar 10 02:42:31 PM PDT 24
Peak memory 206696 kb
Host smart-dcf9b713-c88b-4a8f-bfdc-f4113cdbd6c3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088790974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2088790974
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3345479371
Short name T556
Test name
Test status
Simulation time 855900345 ps
CPU time 7.29 seconds
Started Mar 10 02:42:33 PM PDT 24
Finished Mar 10 02:42:41 PM PDT 24
Peak memory 209680 kb
Host smart-ba900919-6be8-49d8-b4af-149a7b07aa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345479371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3345479371
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2321361662
Short name T515
Test name
Test status
Simulation time 52058418 ps
CPU time 2.66 seconds
Started Mar 10 02:42:26 PM PDT 24
Finished Mar 10 02:42:30 PM PDT 24
Peak memory 206736 kb
Host smart-17d78bd5-e9b8-4548-bcc4-caa5a41b2807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321361662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2321361662
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1651625850
Short name T184
Test name
Test status
Simulation time 6667155023 ps
CPU time 43.74 seconds
Started Mar 10 02:42:34 PM PDT 24
Finished Mar 10 02:43:18 PM PDT 24
Peak memory 222760 kb
Host smart-e73d877a-905f-428a-a974-0a8b956489f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651625850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1651625850
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3233288507
Short name T126
Test name
Test status
Simulation time 566345370 ps
CPU time 14.92 seconds
Started Mar 10 02:42:36 PM PDT 24
Finished Mar 10 02:42:51 PM PDT 24
Peak memory 222788 kb
Host smart-d0a138dc-549e-4f9d-b4df-5a3b464e4b45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233288507 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.3233288507
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1446400056
Short name T511
Test name
Test status
Simulation time 831800635 ps
CPU time 5.61 seconds
Started Mar 10 02:42:25 PM PDT 24
Finished Mar 10 02:42:32 PM PDT 24
Peak memory 208100 kb
Host smart-a31bd182-cfef-4011-83d4-46d0701f134a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446400056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1446400056
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2960027640
Short name T134
Test name
Test status
Simulation time 51175018 ps
CPU time 2.52 seconds
Started Mar 10 02:42:33 PM PDT 24
Finished Mar 10 02:42:35 PM PDT 24
Peak memory 209960 kb
Host smart-ca066b94-0b98-4650-b10a-0ba919e23768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960027640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2960027640
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.623356048
Short name T494
Test name
Test status
Simulation time 24507289 ps
CPU time 0.89 seconds
Started Mar 10 02:45:26 PM PDT 24
Finished Mar 10 02:45:27 PM PDT 24
Peak memory 206184 kb
Host smart-813f163d-8ce2-470d-8a9f-f5bcd70965f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623356048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.623356048
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2019502147
Short name T820
Test name
Test status
Simulation time 518664504 ps
CPU time 6.7 seconds
Started Mar 10 02:45:25 PM PDT 24
Finished Mar 10 02:45:33 PM PDT 24
Peak memory 215708 kb
Host smart-6444101c-2021-4d7e-b4dd-57eb5571db04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2019502147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2019502147
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3312230500
Short name T497
Test name
Test status
Simulation time 33790566 ps
CPU time 2.38 seconds
Started Mar 10 02:45:31 PM PDT 24
Finished Mar 10 02:45:34 PM PDT 24
Peak memory 209788 kb
Host smart-3f3f6de6-1c11-4a25-96ae-8572fd4e820d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312230500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3312230500
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3395565567
Short name T326
Test name
Test status
Simulation time 75096750 ps
CPU time 4.16 seconds
Started Mar 10 02:45:27 PM PDT 24
Finished Mar 10 02:45:31 PM PDT 24
Peak memory 214544 kb
Host smart-748c738f-e7fc-4cd9-bff1-677f2d472998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395565567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3395565567
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2637120803
Short name T62
Test name
Test status
Simulation time 305478229 ps
CPU time 10.1 seconds
Started Mar 10 02:45:26 PM PDT 24
Finished Mar 10 02:45:36 PM PDT 24
Peak memory 214452 kb
Host smart-60ba1a7e-4eb7-4b62-bea0-e236ac1945c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637120803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2637120803
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.410337991
Short name T417
Test name
Test status
Simulation time 447709733 ps
CPU time 3.83 seconds
Started Mar 10 02:45:28 PM PDT 24
Finished Mar 10 02:45:32 PM PDT 24
Peak memory 210096 kb
Host smart-0d643e60-a374-4cfa-ad3e-959627c050ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410337991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.410337991
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.876038235
Short name T890
Test name
Test status
Simulation time 1143319611 ps
CPU time 9.2 seconds
Started Mar 10 02:45:30 PM PDT 24
Finished Mar 10 02:45:40 PM PDT 24
Peak memory 209104 kb
Host smart-d14d5232-a647-47e6-8e3a-835425e061f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876038235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.876038235
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3445817440
Short name T887
Test name
Test status
Simulation time 1780239962 ps
CPU time 40.97 seconds
Started Mar 10 02:45:29 PM PDT 24
Finished Mar 10 02:46:10 PM PDT 24
Peak memory 207656 kb
Host smart-11a8a584-b53d-491b-9ef4-2b66588ced6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445817440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3445817440
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2800350445
Short name T582
Test name
Test status
Simulation time 436287472 ps
CPU time 3.11 seconds
Started Mar 10 02:45:26 PM PDT 24
Finished Mar 10 02:45:30 PM PDT 24
Peak memory 206792 kb
Host smart-59ecfa8b-1c37-4fe8-a4ff-44b26ef8d631
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800350445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2800350445
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.456451360
Short name T82
Test name
Test status
Simulation time 132741891 ps
CPU time 3.49 seconds
Started Mar 10 02:45:27 PM PDT 24
Finished Mar 10 02:45:31 PM PDT 24
Peak memory 206852 kb
Host smart-5fd84813-8dcc-417c-9639-4dccc682f721
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456451360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.456451360
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.4018807579
Short name T545
Test name
Test status
Simulation time 206572143 ps
CPU time 5.96 seconds
Started Mar 10 02:45:31 PM PDT 24
Finished Mar 10 02:45:37 PM PDT 24
Peak memory 208444 kb
Host smart-4535447b-f55d-44bb-b6b4-38d2f2751e2c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018807579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.4018807579
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.222652123
Short name T404
Test name
Test status
Simulation time 89906539 ps
CPU time 2.98 seconds
Started Mar 10 02:45:28 PM PDT 24
Finished Mar 10 02:45:32 PM PDT 24
Peak memory 208124 kb
Host smart-2a53267c-ef5e-4bb1-909a-56f63f6e7b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222652123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.222652123
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.4026978363
Short name T501
Test name
Test status
Simulation time 248901394 ps
CPU time 4.03 seconds
Started Mar 10 02:45:25 PM PDT 24
Finished Mar 10 02:45:30 PM PDT 24
Peak memory 206724 kb
Host smart-58eb3362-2ffa-4483-97d3-6fd8163adc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026978363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.4026978363
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2216847572
Short name T185
Test name
Test status
Simulation time 4922344639 ps
CPU time 22.92 seconds
Started Mar 10 02:45:29 PM PDT 24
Finished Mar 10 02:45:52 PM PDT 24
Peak memory 222728 kb
Host smart-958f8b5c-8a11-424a-bf91-5a689f3943d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216847572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2216847572
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.341678304
Short name T648
Test name
Test status
Simulation time 104830589 ps
CPU time 3.96 seconds
Started Mar 10 02:45:28 PM PDT 24
Finished Mar 10 02:45:32 PM PDT 24
Peak memory 214476 kb
Host smart-fb0a8ac3-7383-4116-af70-9c3cc6e71727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341678304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.341678304
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3700079713
Short name T384
Test name
Test status
Simulation time 74607073 ps
CPU time 1.89 seconds
Started Mar 10 02:45:28 PM PDT 24
Finished Mar 10 02:45:30 PM PDT 24
Peak memory 208944 kb
Host smart-c2c67caa-3c7f-43e2-b05b-f2f278a24dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700079713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3700079713
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2512275269
Short name T566
Test name
Test status
Simulation time 23945897 ps
CPU time 0.85 seconds
Started Mar 10 02:45:33 PM PDT 24
Finished Mar 10 02:45:35 PM PDT 24
Peak memory 206052 kb
Host smart-6ec46f61-3153-4725-a963-141021e01353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512275269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2512275269
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3663277007
Short name T386
Test name
Test status
Simulation time 237538699 ps
CPU time 4.39 seconds
Started Mar 10 02:45:29 PM PDT 24
Finished Mar 10 02:45:34 PM PDT 24
Peak memory 215672 kb
Host smart-121b04f5-a6d2-4356-8b17-4de243085cef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3663277007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3663277007
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2995918754
Short name T33
Test name
Test status
Simulation time 171530209 ps
CPU time 4.24 seconds
Started Mar 10 02:45:30 PM PDT 24
Finished Mar 10 02:45:35 PM PDT 24
Peak memory 214796 kb
Host smart-2556d5f9-1cf1-4122-a2df-7b389a47380b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995918754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2995918754
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.575472115
Short name T750
Test name
Test status
Simulation time 198989815 ps
CPU time 2.87 seconds
Started Mar 10 02:45:28 PM PDT 24
Finished Mar 10 02:45:31 PM PDT 24
Peak memory 207564 kb
Host smart-c6c8e2a5-7d0f-47b1-ba8b-57ca236f2f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575472115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.575472115
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2695740161
Short name T377
Test name
Test status
Simulation time 215213012 ps
CPU time 5.3 seconds
Started Mar 10 02:45:33 PM PDT 24
Finished Mar 10 02:45:39 PM PDT 24
Peak memory 221048 kb
Host smart-e4a3ec9c-c508-49fd-bf03-934c46212780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695740161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2695740161
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3241506919
Short name T202
Test name
Test status
Simulation time 186125714 ps
CPU time 6.98 seconds
Started Mar 10 02:45:31 PM PDT 24
Finished Mar 10 02:45:39 PM PDT 24
Peak memory 214396 kb
Host smart-93d94687-e1b1-4d06-8bab-0a4ce1d17564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241506919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3241506919
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2180805979
Short name T602
Test name
Test status
Simulation time 453469130 ps
CPU time 3.4 seconds
Started Mar 10 02:45:31 PM PDT 24
Finished Mar 10 02:45:35 PM PDT 24
Peak memory 215332 kb
Host smart-b7b2e06e-0282-4160-a6ce-c1e8be3b02d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180805979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2180805979
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2404142750
Short name T498
Test name
Test status
Simulation time 575898259 ps
CPU time 5.43 seconds
Started Mar 10 02:45:29 PM PDT 24
Finished Mar 10 02:45:34 PM PDT 24
Peak memory 207644 kb
Host smart-49bfa0f6-a647-45ed-8fb3-68de6c52619e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404142750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2404142750
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2913739140
Short name T188
Test name
Test status
Simulation time 213323272 ps
CPU time 3.58 seconds
Started Mar 10 02:45:30 PM PDT 24
Finished Mar 10 02:45:34 PM PDT 24
Peak memory 207136 kb
Host smart-cf8095fa-5193-40e7-9265-915e0feb8586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913739140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2913739140
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1215981429
Short name T468
Test name
Test status
Simulation time 797219332 ps
CPU time 10.01 seconds
Started Mar 10 02:45:31 PM PDT 24
Finished Mar 10 02:45:41 PM PDT 24
Peak memory 208120 kb
Host smart-a40e6578-798b-4111-8097-44e030c1467f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215981429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1215981429
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1586770480
Short name T14
Test name
Test status
Simulation time 216312489 ps
CPU time 3.07 seconds
Started Mar 10 02:45:28 PM PDT 24
Finished Mar 10 02:45:31 PM PDT 24
Peak memory 207288 kb
Host smart-cebd6f9a-3afb-4965-ac71-4e6ef65fc32c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586770480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1586770480
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2568359645
Short name T676
Test name
Test status
Simulation time 54732783 ps
CPU time 3.1 seconds
Started Mar 10 02:45:28 PM PDT 24
Finished Mar 10 02:45:31 PM PDT 24
Peak memory 208388 kb
Host smart-e3a94148-1e32-4699-b5d3-4b665b55bbb5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568359645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2568359645
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1073093946
Short name T815
Test name
Test status
Simulation time 195394758 ps
CPU time 2.8 seconds
Started Mar 10 02:45:28 PM PDT 24
Finished Mar 10 02:45:31 PM PDT 24
Peak memory 207352 kb
Host smart-09b400ca-7c6f-4140-b93a-5cd7b483cee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073093946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1073093946
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2171009239
Short name T664
Test name
Test status
Simulation time 40024417 ps
CPU time 2.29 seconds
Started Mar 10 02:45:30 PM PDT 24
Finished Mar 10 02:45:33 PM PDT 24
Peak memory 208100 kb
Host smart-aeab9d9b-1776-403c-84a2-8c2a71438f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171009239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2171009239
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.4186175732
Short name T332
Test name
Test status
Simulation time 615234578 ps
CPU time 15.55 seconds
Started Mar 10 02:45:32 PM PDT 24
Finished Mar 10 02:45:48 PM PDT 24
Peak memory 219248 kb
Host smart-ae13becb-385d-498b-b422-5519a52a4f1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186175732 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.4186175732
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3469216532
Short name T637
Test name
Test status
Simulation time 789071734 ps
CPU time 17.79 seconds
Started Mar 10 02:45:26 PM PDT 24
Finished Mar 10 02:45:44 PM PDT 24
Peak memory 208620 kb
Host smart-57949625-0f5b-4111-9be2-dec001a09b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469216532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3469216532
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3739808231
Short name T561
Test name
Test status
Simulation time 111382590 ps
CPU time 3.14 seconds
Started Mar 10 02:45:29 PM PDT 24
Finished Mar 10 02:45:32 PM PDT 24
Peak memory 209692 kb
Host smart-c3459f77-1506-44c1-92ae-3c36f228df0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739808231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3739808231
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2213651704
Short name T442
Test name
Test status
Simulation time 58279927 ps
CPU time 0.78 seconds
Started Mar 10 02:45:30 PM PDT 24
Finished Mar 10 02:45:32 PM PDT 24
Peak memory 206112 kb
Host smart-f143316d-505b-44cd-adbc-14e912c4d964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213651704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2213651704
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3901788077
Short name T256
Test name
Test status
Simulation time 272345457 ps
CPU time 7.91 seconds
Started Mar 10 02:45:32 PM PDT 24
Finished Mar 10 02:45:40 PM PDT 24
Peak memory 215816 kb
Host smart-c4087e7e-1ef8-4390-be36-4c319500b87c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3901788077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3901788077
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1582707176
Short name T780
Test name
Test status
Simulation time 29034252 ps
CPU time 2.34 seconds
Started Mar 10 02:45:33 PM PDT 24
Finished Mar 10 02:45:36 PM PDT 24
Peak memory 214568 kb
Host smart-f3919f4c-56b2-4b50-b653-e0f8b93f5421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582707176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1582707176
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1936685626
Short name T617
Test name
Test status
Simulation time 203265162 ps
CPU time 5.83 seconds
Started Mar 10 02:45:35 PM PDT 24
Finished Mar 10 02:45:41 PM PDT 24
Peak memory 209328 kb
Host smart-7784f42d-d643-46c2-ae85-510c23d5ebc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936685626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1936685626
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2014183964
Short name T282
Test name
Test status
Simulation time 1361536051 ps
CPU time 20.51 seconds
Started Mar 10 02:45:30 PM PDT 24
Finished Mar 10 02:45:52 PM PDT 24
Peak memory 222648 kb
Host smart-f851e8be-c458-4fed-8f63-df0218719577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014183964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2014183964
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.978038923
Short name T626
Test name
Test status
Simulation time 411909642 ps
CPU time 3.87 seconds
Started Mar 10 02:45:33 PM PDT 24
Finished Mar 10 02:45:38 PM PDT 24
Peak memory 209296 kb
Host smart-9ad56783-1a77-4aa4-8ffe-328047dd2a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978038923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.978038923
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.642914181
Short name T710
Test name
Test status
Simulation time 148374452 ps
CPU time 3.84 seconds
Started Mar 10 02:45:34 PM PDT 24
Finished Mar 10 02:45:38 PM PDT 24
Peak memory 207436 kb
Host smart-84ec8b89-19ec-4676-a684-cb0be2334255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642914181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.642914181
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1848503989
Short name T400
Test name
Test status
Simulation time 53007649 ps
CPU time 2.83 seconds
Started Mar 10 02:45:32 PM PDT 24
Finished Mar 10 02:45:35 PM PDT 24
Peak memory 206744 kb
Host smart-98f9452e-3eb4-42ad-ae76-bfa3687dec47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848503989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1848503989
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3978583930
Short name T604
Test name
Test status
Simulation time 760897921 ps
CPU time 3.41 seconds
Started Mar 10 02:45:34 PM PDT 24
Finished Mar 10 02:45:38 PM PDT 24
Peak memory 208584 kb
Host smart-9a9882e8-814b-471e-b340-8f6e7433993e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978583930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3978583930
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2399933042
Short name T420
Test name
Test status
Simulation time 100136695 ps
CPU time 2.87 seconds
Started Mar 10 02:45:32 PM PDT 24
Finished Mar 10 02:45:36 PM PDT 24
Peak memory 206740 kb
Host smart-7b007f2d-4937-453a-8036-3a8094715bd9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399933042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2399933042
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3598983950
Short name T418
Test name
Test status
Simulation time 1785025554 ps
CPU time 10.41 seconds
Started Mar 10 02:45:35 PM PDT 24
Finished Mar 10 02:45:45 PM PDT 24
Peak memory 208104 kb
Host smart-d5149b67-b407-4da8-8948-85b5ae580cb7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598983950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3598983950
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1427640576
Short name T580
Test name
Test status
Simulation time 335187683 ps
CPU time 2.73 seconds
Started Mar 10 02:45:33 PM PDT 24
Finished Mar 10 02:45:37 PM PDT 24
Peak memory 214528 kb
Host smart-95b2ef52-0ebe-464b-af93-462adaa91a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427640576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1427640576
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2108266909
Short name T692
Test name
Test status
Simulation time 2665769092 ps
CPU time 31.79 seconds
Started Mar 10 02:45:31 PM PDT 24
Finished Mar 10 02:46:03 PM PDT 24
Peak memory 208748 kb
Host smart-36360325-f53a-4a8f-b741-2bef8155c855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108266909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2108266909
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1083625104
Short name T60
Test name
Test status
Simulation time 2355861324 ps
CPU time 28.43 seconds
Started Mar 10 02:45:32 PM PDT 24
Finished Mar 10 02:46:01 PM PDT 24
Peak memory 221032 kb
Host smart-c04b6898-ad0e-4ded-9ad2-9bebc581b465
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083625104 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.1083625104
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2274627118
Short name T697
Test name
Test status
Simulation time 252683228 ps
CPU time 3.68 seconds
Started Mar 10 02:45:33 PM PDT 24
Finished Mar 10 02:45:36 PM PDT 24
Peak memory 207880 kb
Host smart-672a2beb-f4e3-4882-a713-3bbf71dda075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274627118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2274627118
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.577746468
Short name T647
Test name
Test status
Simulation time 124858599 ps
CPU time 3 seconds
Started Mar 10 02:45:35 PM PDT 24
Finished Mar 10 02:45:38 PM PDT 24
Peak memory 210884 kb
Host smart-6e596a6f-9226-4932-bf3c-0a5567703193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577746468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.577746468
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3082714775
Short name T641
Test name
Test status
Simulation time 62043283 ps
CPU time 0.89 seconds
Started Mar 10 02:45:37 PM PDT 24
Finished Mar 10 02:45:38 PM PDT 24
Peak memory 206136 kb
Host smart-c6e57c6b-028d-4021-b65f-8b02b5fdfbbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082714775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3082714775
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.329509694
Short name T895
Test name
Test status
Simulation time 164725643 ps
CPU time 3.2 seconds
Started Mar 10 02:45:39 PM PDT 24
Finished Mar 10 02:45:42 PM PDT 24
Peak memory 215856 kb
Host smart-cabd70fd-9917-4f9b-8f23-bc00ad77f3dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=329509694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.329509694
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.79991555
Short name T528
Test name
Test status
Simulation time 13251919808 ps
CPU time 35.71 seconds
Started Mar 10 02:45:39 PM PDT 24
Finished Mar 10 02:46:15 PM PDT 24
Peak memory 208996 kb
Host smart-31829bb4-f64b-403d-8aa5-b1215b2e687f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79991555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.79991555
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1602114580
Short name T87
Test name
Test status
Simulation time 151006428 ps
CPU time 4.06 seconds
Started Mar 10 02:45:39 PM PDT 24
Finished Mar 10 02:45:44 PM PDT 24
Peak memory 208816 kb
Host smart-2f0f2284-b5d3-48ac-959d-fc113c30915d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602114580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1602114580
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1775922238
Short name T394
Test name
Test status
Simulation time 385034561 ps
CPU time 2.72 seconds
Started Mar 10 02:45:38 PM PDT 24
Finished Mar 10 02:45:41 PM PDT 24
Peak memory 206292 kb
Host smart-a3b3fae2-9fe2-403f-98c6-059338c42d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775922238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1775922238
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.4256414787
Short name T370
Test name
Test status
Simulation time 5236140335 ps
CPU time 34.82 seconds
Started Mar 10 02:45:37 PM PDT 24
Finished Mar 10 02:46:12 PM PDT 24
Peak memory 209092 kb
Host smart-2d915062-0ca2-4407-92ae-449e0370afd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256414787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.4256414787
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.121857196
Short name T249
Test name
Test status
Simulation time 178505311 ps
CPU time 3.74 seconds
Started Mar 10 02:45:31 PM PDT 24
Finished Mar 10 02:45:35 PM PDT 24
Peak memory 206628 kb
Host smart-82acb158-1302-4c11-aa07-2261d63a21cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121857196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.121857196
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.738736552
Short name T553
Test name
Test status
Simulation time 70523645 ps
CPU time 2.96 seconds
Started Mar 10 02:45:32 PM PDT 24
Finished Mar 10 02:45:35 PM PDT 24
Peak memory 208024 kb
Host smart-d0cb8a9f-d8e4-43fa-8b1a-a96b543f856e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738736552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.738736552
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2767462838
Short name T677
Test name
Test status
Simulation time 53719984 ps
CPU time 2.22 seconds
Started Mar 10 02:45:30 PM PDT 24
Finished Mar 10 02:45:33 PM PDT 24
Peak memory 208604 kb
Host smart-671c93b5-0928-42d8-bc26-4c95fb04c97c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767462838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2767462838
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2572787275
Short name T610
Test name
Test status
Simulation time 135931815 ps
CPU time 2.64 seconds
Started Mar 10 02:45:32 PM PDT 24
Finished Mar 10 02:45:34 PM PDT 24
Peak memory 208748 kb
Host smart-38141fd8-daa2-40d5-b585-2d297df7efd3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572787275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2572787275
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1779871368
Short name T783
Test name
Test status
Simulation time 412060163 ps
CPU time 3.61 seconds
Started Mar 10 02:45:39 PM PDT 24
Finished Mar 10 02:45:43 PM PDT 24
Peak memory 208576 kb
Host smart-feb591b4-7a1d-4e72-823e-1c7dec3fbc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779871368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1779871368
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.521239573
Short name T421
Test name
Test status
Simulation time 37521693 ps
CPU time 2.37 seconds
Started Mar 10 02:45:35 PM PDT 24
Finished Mar 10 02:45:38 PM PDT 24
Peak memory 206848 kb
Host smart-da09ef77-5994-4fcd-aa6e-af081b3e4a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521239573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.521239573
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2957581182
Short name T242
Test name
Test status
Simulation time 359170527 ps
CPU time 5.45 seconds
Started Mar 10 02:45:40 PM PDT 24
Finished Mar 10 02:45:46 PM PDT 24
Peak memory 214516 kb
Host smart-1a3717f8-9ca8-4fff-a6ec-98740da785f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957581182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2957581182
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2633369592
Short name T771
Test name
Test status
Simulation time 849517617 ps
CPU time 3.14 seconds
Started Mar 10 02:45:38 PM PDT 24
Finished Mar 10 02:45:41 PM PDT 24
Peak memory 209908 kb
Host smart-7f85a5a1-7cc8-434a-acd1-dd1f2891a1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633369592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2633369592
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1550653465
Short name T483
Test name
Test status
Simulation time 48213918 ps
CPU time 0.77 seconds
Started Mar 10 02:45:41 PM PDT 24
Finished Mar 10 02:45:43 PM PDT 24
Peak memory 206168 kb
Host smart-78cc094c-491b-41dd-8136-24d56c80d03c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550653465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1550653465
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1863670949
Short name T265
Test name
Test status
Simulation time 233320542 ps
CPU time 4.09 seconds
Started Mar 10 02:45:44 PM PDT 24
Finished Mar 10 02:45:48 PM PDT 24
Peak memory 214520 kb
Host smart-7fd2a5af-e729-4f7a-ade7-ba6042f8e20b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1863670949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1863670949
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.551442500
Short name T388
Test name
Test status
Simulation time 106010701 ps
CPU time 3.03 seconds
Started Mar 10 02:45:43 PM PDT 24
Finished Mar 10 02:45:46 PM PDT 24
Peak memory 210908 kb
Host smart-2606b121-f526-42d1-95ea-d0c1629f22a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551442500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.551442500
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.4073835816
Short name T346
Test name
Test status
Simulation time 45791345 ps
CPU time 1.78 seconds
Started Mar 10 02:45:41 PM PDT 24
Finished Mar 10 02:45:44 PM PDT 24
Peak memory 214524 kb
Host smart-d8c568ed-b6f1-4960-b619-7611313189f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073835816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.4073835816
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.794425561
Short name T479
Test name
Test status
Simulation time 382827151 ps
CPU time 5.42 seconds
Started Mar 10 02:45:40 PM PDT 24
Finished Mar 10 02:45:46 PM PDT 24
Peak memory 209180 kb
Host smart-38878141-5c44-49d2-b839-c3c1eb75ce8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794425561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.794425561
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3738804306
Short name T250
Test name
Test status
Simulation time 1090647815 ps
CPU time 8.63 seconds
Started Mar 10 02:45:42 PM PDT 24
Finished Mar 10 02:45:51 PM PDT 24
Peak memory 211592 kb
Host smart-d80e2a78-5d83-41c4-ad69-01d9d77dc5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738804306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3738804306
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_random.2756126201
Short name T372
Test name
Test status
Simulation time 193903655 ps
CPU time 5.03 seconds
Started Mar 10 02:45:45 PM PDT 24
Finished Mar 10 02:45:50 PM PDT 24
Peak memory 207740 kb
Host smart-ed79c4d0-9312-46bf-86b3-78aafeb3d24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756126201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2756126201
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.417645632
Short name T460
Test name
Test status
Simulation time 117717266 ps
CPU time 2.58 seconds
Started Mar 10 02:45:43 PM PDT 24
Finished Mar 10 02:45:46 PM PDT 24
Peak memory 206772 kb
Host smart-552580a7-9b77-45e5-939a-7d087ec5794e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417645632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.417645632
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3844069491
Short name T304
Test name
Test status
Simulation time 233989064 ps
CPU time 4.04 seconds
Started Mar 10 02:45:44 PM PDT 24
Finished Mar 10 02:45:48 PM PDT 24
Peak memory 206836 kb
Host smart-22c35a58-0cb8-49eb-b50f-526ba25207cf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844069491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3844069491
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.556201464
Short name T581
Test name
Test status
Simulation time 119469598 ps
CPU time 3.65 seconds
Started Mar 10 02:45:42 PM PDT 24
Finished Mar 10 02:45:46 PM PDT 24
Peak memory 208720 kb
Host smart-12d3a104-f786-4626-b789-fed0b67e0d4a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556201464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.556201464
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1899477941
Short name T774
Test name
Test status
Simulation time 244653703 ps
CPU time 2.79 seconds
Started Mar 10 02:45:41 PM PDT 24
Finished Mar 10 02:45:45 PM PDT 24
Peak memory 206844 kb
Host smart-68884836-63e2-4263-bb56-d1e8bc9f83c1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899477941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1899477941
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.498791838
Short name T558
Test name
Test status
Simulation time 523750503 ps
CPU time 13.31 seconds
Started Mar 10 02:45:45 PM PDT 24
Finished Mar 10 02:45:58 PM PDT 24
Peak memory 217368 kb
Host smart-a6c6ce92-1cbb-4b45-907d-f30b6675e07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498791838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.498791838
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1717518224
Short name T530
Test name
Test status
Simulation time 176499628 ps
CPU time 3.08 seconds
Started Mar 10 02:45:38 PM PDT 24
Finished Mar 10 02:45:41 PM PDT 24
Peak memory 206692 kb
Host smart-8b46a8c2-a9a1-4d8c-afa0-2e6045f7c2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717518224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1717518224
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2528854983
Short name T340
Test name
Test status
Simulation time 502391083 ps
CPU time 7.48 seconds
Started Mar 10 02:45:44 PM PDT 24
Finished Mar 10 02:45:52 PM PDT 24
Peak memory 209100 kb
Host smart-f8f525f1-174d-4215-bb97-4a369a2ad4a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528854983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2528854983
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3499998317
Short name T458
Test name
Test status
Simulation time 297399212 ps
CPU time 8.81 seconds
Started Mar 10 02:45:45 PM PDT 24
Finished Mar 10 02:45:54 PM PDT 24
Peak memory 209156 kb
Host smart-5060ba43-4157-466c-91c3-fb3512e69275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499998317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3499998317
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1526034020
Short name T382
Test name
Test status
Simulation time 987422720 ps
CPU time 26.95 seconds
Started Mar 10 02:45:41 PM PDT 24
Finished Mar 10 02:46:09 PM PDT 24
Peak memory 222224 kb
Host smart-2a9e78e0-8e4b-4d40-bb2a-82d407d8030b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526034020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1526034020
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.913961512
Short name T536
Test name
Test status
Simulation time 38276111 ps
CPU time 0.86 seconds
Started Mar 10 02:45:48 PM PDT 24
Finished Mar 10 02:45:49 PM PDT 24
Peak memory 206136 kb
Host smart-9b975031-f986-46cf-8868-c106dbc0c2e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913961512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.913961512
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3610740758
Short name T69
Test name
Test status
Simulation time 1305853506 ps
CPU time 27.12 seconds
Started Mar 10 02:45:48 PM PDT 24
Finished Mar 10 02:46:15 PM PDT 24
Peak memory 218524 kb
Host smart-7af068d5-4686-4582-9cd0-611d28247f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610740758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3610740758
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.544528403
Short name T375
Test name
Test status
Simulation time 7788699754 ps
CPU time 37.38 seconds
Started Mar 10 02:45:50 PM PDT 24
Finished Mar 10 02:46:27 PM PDT 24
Peak memory 214584 kb
Host smart-dee26d5c-732d-4de9-8d1f-2ef41557403c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544528403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.544528403
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.477071663
Short name T288
Test name
Test status
Simulation time 373648998 ps
CPU time 2.35 seconds
Started Mar 10 02:45:47 PM PDT 24
Finished Mar 10 02:45:50 PM PDT 24
Peak memory 206848 kb
Host smart-5277abf0-ea07-4f39-9ce8-a24118c25303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477071663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.477071663
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1521791032
Short name T681
Test name
Test status
Simulation time 185279636 ps
CPU time 3.67 seconds
Started Mar 10 02:45:51 PM PDT 24
Finished Mar 10 02:45:55 PM PDT 24
Peak memory 208932 kb
Host smart-508c2ec6-d9ad-4fe4-b38d-074b09cecaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521791032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1521791032
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1489283970
Short name T419
Test name
Test status
Simulation time 169402462 ps
CPU time 2.5 seconds
Started Mar 10 02:45:43 PM PDT 24
Finished Mar 10 02:45:45 PM PDT 24
Peak memory 208240 kb
Host smart-50c7f398-7313-45bc-a51c-21feb03d51e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489283970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1489283970
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2342325227
Short name T337
Test name
Test status
Simulation time 932031605 ps
CPU time 36.34 seconds
Started Mar 10 02:45:40 PM PDT 24
Finished Mar 10 02:46:17 PM PDT 24
Peak memory 208392 kb
Host smart-290039a3-b4cd-4d0a-85f8-882547028efc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342325227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2342325227
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1810863892
Short name T508
Test name
Test status
Simulation time 52072836 ps
CPU time 2.97 seconds
Started Mar 10 02:45:42 PM PDT 24
Finished Mar 10 02:45:45 PM PDT 24
Peak memory 206720 kb
Host smart-9dbd592f-daeb-4bea-8752-4221125cde40
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810863892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1810863892
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3766367554
Short name T273
Test name
Test status
Simulation time 37439498 ps
CPU time 2.64 seconds
Started Mar 10 02:45:43 PM PDT 24
Finished Mar 10 02:45:46 PM PDT 24
Peak memory 208392 kb
Host smart-0d1af94f-495f-478d-8591-b416ed651860
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766367554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3766367554
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1273524550
Short name T210
Test name
Test status
Simulation time 682961065 ps
CPU time 4.73 seconds
Started Mar 10 02:45:51 PM PDT 24
Finished Mar 10 02:45:56 PM PDT 24
Peak memory 207728 kb
Host smart-2c838d41-0f6d-434f-9e58-c173a1bc36af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273524550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1273524550
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3759412983
Short name T521
Test name
Test status
Simulation time 206326901 ps
CPU time 2.81 seconds
Started Mar 10 02:45:44 PM PDT 24
Finished Mar 10 02:45:47 PM PDT 24
Peak memory 206764 kb
Host smart-f70c9ccf-3af2-4656-bad2-21f433526962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759412983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3759412983
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3564688129
Short name T875
Test name
Test status
Simulation time 179755828 ps
CPU time 4.07 seconds
Started Mar 10 02:45:47 PM PDT 24
Finished Mar 10 02:45:52 PM PDT 24
Peak memory 209216 kb
Host smart-d7dc2e93-377b-414a-b340-bbcb17bea209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564688129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3564688129
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2002414999
Short name T776
Test name
Test status
Simulation time 787722835 ps
CPU time 3.56 seconds
Started Mar 10 02:45:46 PM PDT 24
Finished Mar 10 02:45:50 PM PDT 24
Peak memory 210468 kb
Host smart-11186156-6245-4522-9db8-d36260ca7cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002414999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2002414999
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3092988761
Short name T542
Test name
Test status
Simulation time 17805079 ps
CPU time 0.82 seconds
Started Mar 10 02:45:53 PM PDT 24
Finished Mar 10 02:45:54 PM PDT 24
Peak memory 206092 kb
Host smart-d5d4d2bd-e2bc-42bf-af20-fe58f6cc2705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092988761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3092988761
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3273287001
Short name T408
Test name
Test status
Simulation time 223001250 ps
CPU time 12.34 seconds
Started Mar 10 02:45:50 PM PDT 24
Finished Mar 10 02:46:02 PM PDT 24
Peak memory 215780 kb
Host smart-ed6a653c-7ed3-4ba2-9462-0737263a2122
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3273287001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3273287001
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.617253044
Short name T30
Test name
Test status
Simulation time 280071996 ps
CPU time 2.55 seconds
Started Mar 10 02:45:51 PM PDT 24
Finished Mar 10 02:45:54 PM PDT 24
Peak memory 207460 kb
Host smart-b35f45c2-9881-4297-a972-1035902fdb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617253044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.617253044
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.4158404370
Short name T818
Test name
Test status
Simulation time 4560214928 ps
CPU time 38.04 seconds
Started Mar 10 02:45:49 PM PDT 24
Finished Mar 10 02:46:27 PM PDT 24
Peak memory 214464 kb
Host smart-7bc5701a-cc92-4790-852c-22ed3d1445b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158404370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.4158404370
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.4102998584
Short name T765
Test name
Test status
Simulation time 480195155 ps
CPU time 5.85 seconds
Started Mar 10 02:45:50 PM PDT 24
Finished Mar 10 02:45:57 PM PDT 24
Peak memory 209148 kb
Host smart-407ae3b7-9c49-4a4c-851c-550fbec71ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102998584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.4102998584
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2723255934
Short name T199
Test name
Test status
Simulation time 18303039283 ps
CPU time 80.36 seconds
Started Mar 10 02:45:52 PM PDT 24
Finished Mar 10 02:47:13 PM PDT 24
Peak memory 231348 kb
Host smart-0a138b08-9762-46cc-afa2-8179bd2463c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723255934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2723255934
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2503434804
Short name T223
Test name
Test status
Simulation time 167800275 ps
CPU time 5.18 seconds
Started Mar 10 02:45:51 PM PDT 24
Finished Mar 10 02:45:57 PM PDT 24
Peak memory 214600 kb
Host smart-91fc6ab0-8e90-4fe2-af22-cc07128a114d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503434804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2503434804
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2493010435
Short name T552
Test name
Test status
Simulation time 91036904 ps
CPU time 4.36 seconds
Started Mar 10 02:45:47 PM PDT 24
Finished Mar 10 02:45:52 PM PDT 24
Peak memory 210052 kb
Host smart-25153491-7505-4a48-bd99-038b6b9e3be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493010435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2493010435
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3135587023
Short name T576
Test name
Test status
Simulation time 115469433 ps
CPU time 3.61 seconds
Started Mar 10 02:45:49 PM PDT 24
Finished Mar 10 02:45:53 PM PDT 24
Peak memory 208480 kb
Host smart-2ea59f84-6f7c-4eb8-ab08-b610648ac2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135587023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3135587023
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3090375347
Short name T505
Test name
Test status
Simulation time 1216909433 ps
CPU time 9.98 seconds
Started Mar 10 02:45:51 PM PDT 24
Finished Mar 10 02:46:01 PM PDT 24
Peak memory 208356 kb
Host smart-474993d4-bc85-45b9-8b34-cadd72463acf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090375347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3090375347
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1642433237
Short name T212
Test name
Test status
Simulation time 24503055 ps
CPU time 1.86 seconds
Started Mar 10 02:45:48 PM PDT 24
Finished Mar 10 02:45:51 PM PDT 24
Peak memory 206952 kb
Host smart-7575a61b-21cc-468a-bb2e-d2c3cf4bcd92
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642433237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1642433237
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3336851773
Short name T571
Test name
Test status
Simulation time 152030945 ps
CPU time 3.13 seconds
Started Mar 10 02:45:49 PM PDT 24
Finished Mar 10 02:45:53 PM PDT 24
Peak memory 206900 kb
Host smart-921ca741-a909-479d-8b64-9493d37962e3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336851773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3336851773
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.166161074
Short name T79
Test name
Test status
Simulation time 129106038 ps
CPU time 3 seconds
Started Mar 10 02:45:52 PM PDT 24
Finished Mar 10 02:45:55 PM PDT 24
Peak memory 214552 kb
Host smart-c49336d7-d141-448a-a2a5-441e7a895253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166161074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.166161074
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3048380249
Short name T516
Test name
Test status
Simulation time 310570730 ps
CPU time 3.69 seconds
Started Mar 10 02:45:48 PM PDT 24
Finished Mar 10 02:45:53 PM PDT 24
Peak memory 208692 kb
Host smart-5ab17dbb-a24e-4e9f-9f34-3f86493b6f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048380249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3048380249
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2326173577
Short name T654
Test name
Test status
Simulation time 84822546 ps
CPU time 4.06 seconds
Started Mar 10 02:45:47 PM PDT 24
Finished Mar 10 02:45:51 PM PDT 24
Peak memory 209460 kb
Host smart-792ec669-30c7-49e6-9fe5-67972528a122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326173577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2326173577
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2223764448
Short name T885
Test name
Test status
Simulation time 120611984 ps
CPU time 1.49 seconds
Started Mar 10 02:45:52 PM PDT 24
Finished Mar 10 02:45:54 PM PDT 24
Peak memory 209612 kb
Host smart-3f5c0cbf-9710-459e-a484-da9bd69993ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223764448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2223764448
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.4263595265
Short name T569
Test name
Test status
Simulation time 25891160 ps
CPU time 0.68 seconds
Started Mar 10 02:45:51 PM PDT 24
Finished Mar 10 02:45:52 PM PDT 24
Peak memory 206188 kb
Host smart-0efe0099-a49c-43b8-8e66-7070cd89ce37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263595265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.4263595265
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2949026624
Short name T239
Test name
Test status
Simulation time 87479297 ps
CPU time 3 seconds
Started Mar 10 02:45:50 PM PDT 24
Finished Mar 10 02:45:53 PM PDT 24
Peak memory 214536 kb
Host smart-ab296841-f79e-4a71-8329-621c4f1be93f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2949026624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2949026624
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2661982650
Short name T722
Test name
Test status
Simulation time 112449333 ps
CPU time 2.2 seconds
Started Mar 10 02:45:52 PM PDT 24
Finished Mar 10 02:45:55 PM PDT 24
Peak memory 207536 kb
Host smart-85aabae3-4ff8-4875-b472-1ef27114f281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661982650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2661982650
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2782701922
Short name T76
Test name
Test status
Simulation time 1528821627 ps
CPU time 8.71 seconds
Started Mar 10 02:45:52 PM PDT 24
Finished Mar 10 02:46:01 PM PDT 24
Peak memory 214528 kb
Host smart-d571122d-86dd-431e-a2db-d3e4946a5fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782701922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2782701922
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.213611786
Short name T342
Test name
Test status
Simulation time 2170580242 ps
CPU time 15.21 seconds
Started Mar 10 02:45:56 PM PDT 24
Finished Mar 10 02:46:11 PM PDT 24
Peak memory 214504 kb
Host smart-409231c9-147d-4902-8182-433ae19653e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213611786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.213611786
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1186031709
Short name T409
Test name
Test status
Simulation time 185544926 ps
CPU time 2.69 seconds
Started Mar 10 02:45:54 PM PDT 24
Finished Mar 10 02:45:57 PM PDT 24
Peak memory 208512 kb
Host smart-ae68bd39-8f4b-42f2-b429-039919c36a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186031709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1186031709
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1222034277
Short name T611
Test name
Test status
Simulation time 92885344 ps
CPU time 2.99 seconds
Started Mar 10 02:45:53 PM PDT 24
Finished Mar 10 02:45:57 PM PDT 24
Peak memory 214568 kb
Host smart-a93e975c-da1a-4435-921f-6b1fc376123e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222034277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1222034277
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1316516975
Short name T313
Test name
Test status
Simulation time 201380817 ps
CPU time 2.99 seconds
Started Mar 10 02:45:51 PM PDT 24
Finished Mar 10 02:45:55 PM PDT 24
Peak memory 206776 kb
Host smart-1792b1f4-31ec-44a2-8c94-9493e866c6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316516975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1316516975
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.4272766912
Short name T892
Test name
Test status
Simulation time 141957041 ps
CPU time 2.3 seconds
Started Mar 10 02:45:54 PM PDT 24
Finished Mar 10 02:45:57 PM PDT 24
Peak memory 206724 kb
Host smart-6bf47ab5-b8cf-42dd-8b61-65cc132cf713
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272766912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.4272766912
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.4254893696
Short name T630
Test name
Test status
Simulation time 142955450 ps
CPU time 4.65 seconds
Started Mar 10 02:45:51 PM PDT 24
Finished Mar 10 02:45:57 PM PDT 24
Peak memory 208432 kb
Host smart-1a9dae51-5ef8-4640-b06d-04c66cada851
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254893696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.4254893696
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.249962598
Short name T215
Test name
Test status
Simulation time 294149323 ps
CPU time 4.7 seconds
Started Mar 10 02:45:56 PM PDT 24
Finished Mar 10 02:46:01 PM PDT 24
Peak memory 206776 kb
Host smart-447fd610-388c-414d-a81a-21acf65a13dc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249962598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.249962598
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1486104295
Short name T80
Test name
Test status
Simulation time 4345431404 ps
CPU time 18.03 seconds
Started Mar 10 02:45:54 PM PDT 24
Finished Mar 10 02:46:12 PM PDT 24
Peak memory 210116 kb
Host smart-29038e1c-1560-4ed5-8735-3ab10728b9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486104295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1486104295
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3731564732
Short name T622
Test name
Test status
Simulation time 125302732 ps
CPU time 3.64 seconds
Started Mar 10 02:45:56 PM PDT 24
Finished Mar 10 02:46:01 PM PDT 24
Peak memory 206672 kb
Host smart-936a70ad-5642-4253-9681-4d7d75c2eb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731564732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3731564732
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.796403897
Short name T365
Test name
Test status
Simulation time 3293747833 ps
CPU time 22.71 seconds
Started Mar 10 02:45:52 PM PDT 24
Finished Mar 10 02:46:15 PM PDT 24
Peak memory 216840 kb
Host smart-05b3c446-8996-46a3-9c9c-9b14a3709d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796403897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.796403897
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.4211886557
Short name T687
Test name
Test status
Simulation time 757674447 ps
CPU time 22.86 seconds
Started Mar 10 02:45:53 PM PDT 24
Finished Mar 10 02:46:17 PM PDT 24
Peak memory 208176 kb
Host smart-f2b21ae2-9edd-4c9b-95cf-0bc85ecedf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211886557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.4211886557
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.717683086
Short name T741
Test name
Test status
Simulation time 476302206 ps
CPU time 3.71 seconds
Started Mar 10 02:45:52 PM PDT 24
Finished Mar 10 02:45:56 PM PDT 24
Peak memory 210224 kb
Host smart-7df4bb84-732e-4d89-8116-cba8fc1f0db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717683086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.717683086
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3754695270
Short name T704
Test name
Test status
Simulation time 19290472 ps
CPU time 0.72 seconds
Started Mar 10 02:45:56 PM PDT 24
Finished Mar 10 02:45:57 PM PDT 24
Peak memory 206184 kb
Host smart-73a6f675-f39d-4635-af08-e75b3db16cd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754695270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3754695270
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3447080843
Short name T24
Test name
Test status
Simulation time 2859519457 ps
CPU time 15.8 seconds
Started Mar 10 02:45:58 PM PDT 24
Finished Mar 10 02:46:14 PM PDT 24
Peak memory 222908 kb
Host smart-8d663db6-9e11-4412-b8a4-04bc747efa40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447080843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3447080843
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2129431012
Short name T723
Test name
Test status
Simulation time 70150410 ps
CPU time 3.33 seconds
Started Mar 10 02:45:59 PM PDT 24
Finished Mar 10 02:46:02 PM PDT 24
Peak memory 207496 kb
Host smart-755a40dc-56b8-4529-9eff-199a2f1bbe19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129431012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2129431012
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.715893747
Short name T757
Test name
Test status
Simulation time 127218279 ps
CPU time 4.71 seconds
Started Mar 10 02:46:00 PM PDT 24
Finished Mar 10 02:46:04 PM PDT 24
Peak memory 219320 kb
Host smart-e3afee87-d0ab-487a-9c2f-9f0515904915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715893747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.715893747
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3303006194
Short name T1
Test name
Test status
Simulation time 1451877554 ps
CPU time 4.28 seconds
Started Mar 10 02:45:56 PM PDT 24
Finished Mar 10 02:46:00 PM PDT 24
Peak memory 218940 kb
Host smart-e0140bb6-12b4-4522-a293-1559316ff4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303006194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3303006194
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.956573035
Short name T324
Test name
Test status
Simulation time 1657331839 ps
CPU time 53.91 seconds
Started Mar 10 02:45:58 PM PDT 24
Finished Mar 10 02:46:52 PM PDT 24
Peak memory 218732 kb
Host smart-dcd67051-2664-4855-a785-2ac840dfa537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956573035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.956573035
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2157471429
Short name T351
Test name
Test status
Simulation time 641730922 ps
CPU time 3.19 seconds
Started Mar 10 02:45:53 PM PDT 24
Finished Mar 10 02:45:57 PM PDT 24
Peak memory 208560 kb
Host smart-3ccd6f7e-3b58-4e3e-b441-de0fe8b8ff49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157471429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2157471429
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2455729281
Short name T467
Test name
Test status
Simulation time 127897699 ps
CPU time 2.41 seconds
Started Mar 10 02:45:59 PM PDT 24
Finished Mar 10 02:46:01 PM PDT 24
Peak memory 207484 kb
Host smart-4e03568f-7207-4c93-bb12-da3fa2ed766e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455729281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2455729281
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1306475594
Short name T500
Test name
Test status
Simulation time 784372879 ps
CPU time 7.18 seconds
Started Mar 10 02:45:59 PM PDT 24
Finished Mar 10 02:46:06 PM PDT 24
Peak memory 207964 kb
Host smart-16848fb9-c832-4f9c-a7e0-496affd16f34
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306475594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1306475594
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.4108550016
Short name T668
Test name
Test status
Simulation time 662710324 ps
CPU time 19.22 seconds
Started Mar 10 02:45:58 PM PDT 24
Finished Mar 10 02:46:18 PM PDT 24
Peak memory 207780 kb
Host smart-1eb05fad-755d-4740-b6aa-248a445b9e71
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108550016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.4108550016
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.4272679429
Short name T190
Test name
Test status
Simulation time 59420533 ps
CPU time 3.14 seconds
Started Mar 10 02:45:59 PM PDT 24
Finished Mar 10 02:46:02 PM PDT 24
Peak memory 209640 kb
Host smart-c326c783-6299-41de-bd1a-0d99920caf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272679429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.4272679429
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2242322767
Short name T524
Test name
Test status
Simulation time 9164568737 ps
CPU time 43.22 seconds
Started Mar 10 02:45:53 PM PDT 24
Finished Mar 10 02:46:37 PM PDT 24
Peak memory 208492 kb
Host smart-c614fb59-cddc-4be1-b60a-cd14e29bae26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242322767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2242322767
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.630019283
Short name T744
Test name
Test status
Simulation time 1261894064 ps
CPU time 24.13 seconds
Started Mar 10 02:46:00 PM PDT 24
Finished Mar 10 02:46:25 PM PDT 24
Peak memory 216136 kb
Host smart-1bcd66a4-3442-42af-bef5-c1dfb2eb9721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630019283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.630019283
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1625538056
Short name T133
Test name
Test status
Simulation time 376439884 ps
CPU time 14.73 seconds
Started Mar 10 02:45:59 PM PDT 24
Finished Mar 10 02:46:13 PM PDT 24
Peak memory 222800 kb
Host smart-ce21ea43-34f0-41d1-a527-2b8d99313b5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625538056 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1625538056
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2465562787
Short name T870
Test name
Test status
Simulation time 733387497 ps
CPU time 23.87 seconds
Started Mar 10 02:46:00 PM PDT 24
Finished Mar 10 02:46:24 PM PDT 24
Peak memory 214420 kb
Host smart-71a86a61-c892-4b74-8584-0ffbc6376c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465562787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2465562787
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1758440501
Short name T383
Test name
Test status
Simulation time 129335633 ps
CPU time 1.78 seconds
Started Mar 10 02:45:58 PM PDT 24
Finished Mar 10 02:46:00 PM PDT 24
Peak memory 210040 kb
Host smart-a28a9fd6-ec26-42ae-a460-22198fbe911b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758440501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1758440501
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2156605183
Short name T461
Test name
Test status
Simulation time 16891034 ps
CPU time 0.94 seconds
Started Mar 10 02:46:04 PM PDT 24
Finished Mar 10 02:46:05 PM PDT 24
Peak memory 206344 kb
Host smart-958b300a-ca46-432b-a9bf-d1d094c79db8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156605183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2156605183
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1943911403
Short name T874
Test name
Test status
Simulation time 148855160 ps
CPU time 3.96 seconds
Started Mar 10 02:46:00 PM PDT 24
Finished Mar 10 02:46:04 PM PDT 24
Peak memory 215416 kb
Host smart-7909f438-6b89-4db7-9065-82fcc7ced3fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1943911403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1943911403
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.4028160425
Short name T739
Test name
Test status
Simulation time 97788598 ps
CPU time 2.58 seconds
Started Mar 10 02:46:04 PM PDT 24
Finished Mar 10 02:46:07 PM PDT 24
Peak memory 217400 kb
Host smart-506151f2-591c-45e7-9f61-3436922764f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028160425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.4028160425
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1665338822
Short name T462
Test name
Test status
Simulation time 81236777 ps
CPU time 1.84 seconds
Started Mar 10 02:46:01 PM PDT 24
Finished Mar 10 02:46:03 PM PDT 24
Peak memory 218704 kb
Host smart-4f5f0cd1-7a9e-45de-848f-a6a67eb8a583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665338822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1665338822
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3784103180
Short name T825
Test name
Test status
Simulation time 146503396 ps
CPU time 2.89 seconds
Started Mar 10 02:46:03 PM PDT 24
Finished Mar 10 02:46:06 PM PDT 24
Peak memory 214548 kb
Host smart-99a352d1-7d8c-43a6-8039-021ec1899364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784103180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3784103180
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3781723738
Short name T32
Test name
Test status
Simulation time 597793982 ps
CPU time 7.92 seconds
Started Mar 10 02:46:04 PM PDT 24
Finished Mar 10 02:46:12 PM PDT 24
Peak memory 211488 kb
Host smart-9c6871b2-5fd4-464e-b8d4-f0be546fc732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781723738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3781723738
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.379627333
Short name T7
Test name
Test status
Simulation time 219092836 ps
CPU time 3.15 seconds
Started Mar 10 02:46:03 PM PDT 24
Finished Mar 10 02:46:06 PM PDT 24
Peak memory 214772 kb
Host smart-6d7282b1-6ca1-4fb8-aaa5-9f52c3522214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379627333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.379627333
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1944432880
Short name T819
Test name
Test status
Simulation time 57440607 ps
CPU time 3.54 seconds
Started Mar 10 02:46:02 PM PDT 24
Finished Mar 10 02:46:06 PM PDT 24
Peak memory 208196 kb
Host smart-26e57bb5-39cd-45db-91eb-084bb6d34dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944432880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1944432880
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3797119190
Short name T636
Test name
Test status
Simulation time 202762571 ps
CPU time 7.6 seconds
Started Mar 10 02:45:56 PM PDT 24
Finished Mar 10 02:46:04 PM PDT 24
Peak memory 207884 kb
Host smart-bc9e22d2-3b31-49c5-a3f1-313238a80ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797119190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3797119190
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2871979614
Short name T547
Test name
Test status
Simulation time 651809889 ps
CPU time 17.36 seconds
Started Mar 10 02:46:03 PM PDT 24
Finished Mar 10 02:46:21 PM PDT 24
Peak memory 208040 kb
Host smart-be0df258-bc6c-4382-a57c-e7173208e284
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871979614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2871979614
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3161332594
Short name T660
Test name
Test status
Simulation time 131996711 ps
CPU time 4.22 seconds
Started Mar 10 02:46:05 PM PDT 24
Finished Mar 10 02:46:09 PM PDT 24
Peak memory 207728 kb
Host smart-9c01ccd9-e8da-4e7b-9ced-36ae74311c4e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161332594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3161332594
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2019165447
Short name T655
Test name
Test status
Simulation time 898324072 ps
CPU time 13.14 seconds
Started Mar 10 02:46:04 PM PDT 24
Finished Mar 10 02:46:17 PM PDT 24
Peak memory 208020 kb
Host smart-ca1e1e5b-f5a6-405a-8a10-856e759b9f31
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019165447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2019165447
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2580197845
Short name T747
Test name
Test status
Simulation time 389799152 ps
CPU time 5.45 seconds
Started Mar 10 02:46:01 PM PDT 24
Finished Mar 10 02:46:07 PM PDT 24
Peak memory 207356 kb
Host smart-4fa380db-4b69-44e1-b983-0ef6c36874ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580197845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2580197845
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1108645517
Short name T538
Test name
Test status
Simulation time 524135427 ps
CPU time 12.42 seconds
Started Mar 10 02:46:00 PM PDT 24
Finished Mar 10 02:46:12 PM PDT 24
Peak memory 208504 kb
Host smart-29c95aa3-e6ac-4cb4-ba61-b80766567b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108645517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1108645517
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2321097818
Short name T833
Test name
Test status
Simulation time 567320658 ps
CPU time 5.36 seconds
Started Mar 10 02:46:04 PM PDT 24
Finished Mar 10 02:46:09 PM PDT 24
Peak memory 218480 kb
Host smart-36cbff02-ea6d-4a86-af79-a92b95e0e67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321097818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2321097818
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2982994186
Short name T520
Test name
Test status
Simulation time 135545899 ps
CPU time 1.92 seconds
Started Mar 10 02:46:06 PM PDT 24
Finished Mar 10 02:46:08 PM PDT 24
Peak memory 210608 kb
Host smart-9a41b17d-3d1c-4ff2-b327-460e03132f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982994186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2982994186
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3274605228
Short name T812
Test name
Test status
Simulation time 183412763 ps
CPU time 0.81 seconds
Started Mar 10 02:42:38 PM PDT 24
Finished Mar 10 02:42:39 PM PDT 24
Peak memory 206048 kb
Host smart-40492153-ad88-47ea-9e80-e71c3e9be93b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274605228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3274605228
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1818512514
Short name T860
Test name
Test status
Simulation time 1198852956 ps
CPU time 42.62 seconds
Started Mar 10 02:42:42 PM PDT 24
Finished Mar 10 02:43:25 PM PDT 24
Peak memory 222624 kb
Host smart-b4dd54db-31d5-4d4f-b11e-40d742eaef47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818512514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1818512514
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1231069058
Short name T107
Test name
Test status
Simulation time 366313664 ps
CPU time 4.71 seconds
Started Mar 10 02:42:41 PM PDT 24
Finished Mar 10 02:42:47 PM PDT 24
Peak memory 209944 kb
Host smart-716abe8c-c993-4478-ab6a-161804c3029b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231069058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1231069058
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3221172594
Short name T92
Test name
Test status
Simulation time 230691962 ps
CPU time 5.2 seconds
Started Mar 10 02:42:39 PM PDT 24
Finished Mar 10 02:42:45 PM PDT 24
Peak memory 215084 kb
Host smart-50c8e3fb-91a2-4b23-9438-ed5ca872ba34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221172594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3221172594
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3660189457
Short name T218
Test name
Test status
Simulation time 114049683 ps
CPU time 3.58 seconds
Started Mar 10 02:42:38 PM PDT 24
Finished Mar 10 02:42:42 PM PDT 24
Peak memory 220152 kb
Host smart-0f6e1d74-5418-413e-9140-af118185341c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660189457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3660189457
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3742976499
Short name T822
Test name
Test status
Simulation time 1441260729 ps
CPU time 18.76 seconds
Started Mar 10 02:42:38 PM PDT 24
Finished Mar 10 02:42:57 PM PDT 24
Peak memory 209180 kb
Host smart-2e85a7a4-1ab5-4e5e-a034-c7804561eb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742976499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3742976499
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2105223462
Short name T197
Test name
Test status
Simulation time 118350335 ps
CPU time 3.85 seconds
Started Mar 10 02:42:36 PM PDT 24
Finished Mar 10 02:42:40 PM PDT 24
Peak memory 207924 kb
Host smart-fcfa42bd-21b7-4bd4-b606-ebcb65bda507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105223462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2105223462
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2419882277
Short name T851
Test name
Test status
Simulation time 136358481 ps
CPU time 4.27 seconds
Started Mar 10 02:42:33 PM PDT 24
Finished Mar 10 02:42:38 PM PDT 24
Peak memory 208284 kb
Host smart-7b03e55e-ab07-4e8a-b992-84057d5efe95
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419882277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2419882277
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3112455703
Short name T328
Test name
Test status
Simulation time 60020318 ps
CPU time 2.25 seconds
Started Mar 10 02:42:32 PM PDT 24
Finished Mar 10 02:42:34 PM PDT 24
Peak memory 207220 kb
Host smart-2921d2ff-261c-4951-bbb3-6a8a6028c18e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112455703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3112455703
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3683979689
Short name T773
Test name
Test status
Simulation time 340333337 ps
CPU time 3.16 seconds
Started Mar 10 02:42:40 PM PDT 24
Finished Mar 10 02:42:43 PM PDT 24
Peak memory 206824 kb
Host smart-38bdb0f4-60f8-4686-9afd-b560b199d6f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683979689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3683979689
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3907092734
Short name T534
Test name
Test status
Simulation time 57821191 ps
CPU time 2.19 seconds
Started Mar 10 02:42:42 PM PDT 24
Finished Mar 10 02:42:46 PM PDT 24
Peak memory 209964 kb
Host smart-bbe3be97-86b6-4ccb-9c59-89e2d0694b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907092734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3907092734
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3012476748
Short name T482
Test name
Test status
Simulation time 186451027 ps
CPU time 2.94 seconds
Started Mar 10 02:42:33 PM PDT 24
Finished Mar 10 02:42:37 PM PDT 24
Peak memory 206804 kb
Host smart-f1533f8a-f4fd-4d0b-ab38-7df080406021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012476748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3012476748
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3403864573
Short name T71
Test name
Test status
Simulation time 3936189562 ps
CPU time 40.59 seconds
Started Mar 10 02:42:39 PM PDT 24
Finished Mar 10 02:43:19 PM PDT 24
Peak memory 215580 kb
Host smart-76fadbb1-38a3-491d-9fe4-e371a9d10ae3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403864573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3403864573
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1828342728
Short name T357
Test name
Test status
Simulation time 189630020 ps
CPU time 4.73 seconds
Started Mar 10 02:42:38 PM PDT 24
Finished Mar 10 02:42:43 PM PDT 24
Peak memory 209676 kb
Host smart-8bd4b17d-b5bf-47fa-bb93-1c6a8929ff4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828342728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1828342728
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3182973634
Short name T380
Test name
Test status
Simulation time 515870333 ps
CPU time 12.84 seconds
Started Mar 10 02:42:39 PM PDT 24
Finished Mar 10 02:42:52 PM PDT 24
Peak memory 211080 kb
Host smart-de965901-2c96-43d7-946a-68585e7f9f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182973634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3182973634
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2673843517
Short name T891
Test name
Test status
Simulation time 71198841 ps
CPU time 0.94 seconds
Started Mar 10 02:42:44 PM PDT 24
Finished Mar 10 02:42:45 PM PDT 24
Peak memory 206332 kb
Host smart-1e814cf4-5079-4d58-90c0-5871a435622b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673843517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2673843517
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3015551432
Short name T201
Test name
Test status
Simulation time 162181622 ps
CPU time 8.44 seconds
Started Mar 10 02:42:44 PM PDT 24
Finished Mar 10 02:42:53 PM PDT 24
Peak memory 215592 kb
Host smart-0dc8cf84-8543-4c05-86d8-fc0a9ea2fbbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3015551432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3015551432
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2582181685
Short name T590
Test name
Test status
Simulation time 619739508 ps
CPU time 7.2 seconds
Started Mar 10 02:42:43 PM PDT 24
Finished Mar 10 02:42:51 PM PDT 24
Peak memory 219632 kb
Host smart-09e27493-2784-4730-a661-d390139e1f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582181685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2582181685
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1909065910
Short name T709
Test name
Test status
Simulation time 143595073 ps
CPU time 1.92 seconds
Started Mar 10 02:42:45 PM PDT 24
Finished Mar 10 02:42:47 PM PDT 24
Peak memory 207324 kb
Host smart-fb392615-a282-4122-ad8f-c5445032688c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909065910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1909065910
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1609485582
Short name T727
Test name
Test status
Simulation time 431300056 ps
CPU time 5.29 seconds
Started Mar 10 02:42:41 PM PDT 24
Finished Mar 10 02:42:48 PM PDT 24
Peak memory 209388 kb
Host smart-917f4a15-d8f4-41a8-96f5-d1c37e93d423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609485582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1609485582
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3932099504
Short name T252
Test name
Test status
Simulation time 285697622 ps
CPU time 7.96 seconds
Started Mar 10 02:42:42 PM PDT 24
Finished Mar 10 02:42:50 PM PDT 24
Peak memory 211356 kb
Host smart-07c8a584-7580-4380-8cb0-1cb7ba9b6f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932099504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3932099504
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1244597146
Short name T455
Test name
Test status
Simulation time 165147494 ps
CPU time 2.79 seconds
Started Mar 10 02:42:43 PM PDT 24
Finished Mar 10 02:42:47 PM PDT 24
Peak memory 216044 kb
Host smart-d368191e-5241-4254-894c-7910ad9c7701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244597146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1244597146
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3164927328
Short name T608
Test name
Test status
Simulation time 230802259 ps
CPU time 7.56 seconds
Started Mar 10 02:42:43 PM PDT 24
Finished Mar 10 02:42:51 PM PDT 24
Peak memory 207820 kb
Host smart-1971bb78-0502-42b5-a82e-76d2a7dcc3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164927328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3164927328
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2067322376
Short name T447
Test name
Test status
Simulation time 160577364 ps
CPU time 5.96 seconds
Started Mar 10 02:42:40 PM PDT 24
Finished Mar 10 02:42:47 PM PDT 24
Peak memory 208496 kb
Host smart-b9fbd5f7-fdbb-47de-8fc2-9012ad6af6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067322376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2067322376
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.559100408
Short name T535
Test name
Test status
Simulation time 7165030630 ps
CPU time 42.28 seconds
Started Mar 10 02:42:40 PM PDT 24
Finished Mar 10 02:43:22 PM PDT 24
Peak memory 208380 kb
Host smart-9c5c9e08-c3f4-4cf3-b904-a53298249798
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559100408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.559100408
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3639692783
Short name T588
Test name
Test status
Simulation time 639812124 ps
CPU time 4.57 seconds
Started Mar 10 02:42:38 PM PDT 24
Finished Mar 10 02:42:43 PM PDT 24
Peak memory 207720 kb
Host smart-8a1e8ac2-e304-4db7-8b40-aa2606eb1e47
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639692783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3639692783
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.803998999
Short name T399
Test name
Test status
Simulation time 156820445 ps
CPU time 3.05 seconds
Started Mar 10 02:42:38 PM PDT 24
Finished Mar 10 02:42:41 PM PDT 24
Peak memory 206752 kb
Host smart-e2f8e12c-c272-4778-a201-f179cb841852
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803998999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.803998999
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1558622419
Short name T329
Test name
Test status
Simulation time 298767663 ps
CPU time 3.13 seconds
Started Mar 10 02:42:42 PM PDT 24
Finished Mar 10 02:42:47 PM PDT 24
Peak memory 220444 kb
Host smart-e86df99d-bf0c-4bd9-897f-268180682272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558622419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1558622419
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3643060219
Short name T609
Test name
Test status
Simulation time 377005498 ps
CPU time 3.39 seconds
Started Mar 10 02:42:39 PM PDT 24
Finished Mar 10 02:42:43 PM PDT 24
Peak memory 208428 kb
Host smart-63b7350d-238d-4133-85e0-a2d431cd3235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643060219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3643060219
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1872714154
Short name T182
Test name
Test status
Simulation time 721838112 ps
CPU time 27.81 seconds
Started Mar 10 02:42:43 PM PDT 24
Finished Mar 10 02:43:11 PM PDT 24
Peak memory 222640 kb
Host smart-acb23ee7-a2a9-4a0c-9906-c658eaf6de7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872714154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1872714154
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3453951199
Short name T688
Test name
Test status
Simulation time 161348975 ps
CPU time 5.66 seconds
Started Mar 10 02:42:44 PM PDT 24
Finished Mar 10 02:42:50 PM PDT 24
Peak memory 207460 kb
Host smart-698b355f-f80b-43d1-a516-fd10000eb739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453951199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3453951199
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.635012520
Short name T572
Test name
Test status
Simulation time 78698080 ps
CPU time 2.39 seconds
Started Mar 10 02:42:42 PM PDT 24
Finished Mar 10 02:42:46 PM PDT 24
Peak memory 210128 kb
Host smart-afa8e751-1746-4fb9-b240-67be9a5d8af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635012520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.635012520
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3593767600
Short name T802
Test name
Test status
Simulation time 36151742 ps
CPU time 0.74 seconds
Started Mar 10 02:42:51 PM PDT 24
Finished Mar 10 02:42:51 PM PDT 24
Peak memory 206060 kb
Host smart-6be2f5bf-8380-4a5b-9680-68947331b0bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593767600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3593767600
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1123956093
Short name T402
Test name
Test status
Simulation time 1806974965 ps
CPU time 9.84 seconds
Started Mar 10 02:42:49 PM PDT 24
Finished Mar 10 02:42:59 PM PDT 24
Peak memory 214564 kb
Host smart-9e373735-caa3-4081-834d-2230cd7108c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1123956093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1123956093
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3107896208
Short name T831
Test name
Test status
Simulation time 323854024 ps
CPU time 2.71 seconds
Started Mar 10 02:42:49 PM PDT 24
Finished Mar 10 02:42:52 PM PDT 24
Peak memory 210608 kb
Host smart-f8c26452-7b8f-42dc-8d28-e1552e96f69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107896208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3107896208
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3765611620
Short name T737
Test name
Test status
Simulation time 51392821 ps
CPU time 1.98 seconds
Started Mar 10 02:42:50 PM PDT 24
Finished Mar 10 02:42:52 PM PDT 24
Peak memory 209024 kb
Host smart-4e286af2-8a3f-4854-b1e4-6f07237023ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765611620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3765611620
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2887189554
Short name T232
Test name
Test status
Simulation time 738833191 ps
CPU time 4.13 seconds
Started Mar 10 02:42:49 PM PDT 24
Finished Mar 10 02:42:53 PM PDT 24
Peak memory 210504 kb
Host smart-84124e97-a254-4f75-b89b-6dba82fe99f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887189554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2887189554
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2901138889
Short name T393
Test name
Test status
Simulation time 63713019 ps
CPU time 3.25 seconds
Started Mar 10 02:42:53 PM PDT 24
Finished Mar 10 02:42:57 PM PDT 24
Peak memory 207268 kb
Host smart-bb03cf9f-957b-4a4c-ac96-2440997c91ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901138889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2901138889
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3351208365
Short name T278
Test name
Test status
Simulation time 3214177470 ps
CPU time 34.74 seconds
Started Mar 10 02:42:53 PM PDT 24
Finished Mar 10 02:43:28 PM PDT 24
Peak memory 209236 kb
Host smart-0419511b-875c-44bf-b6cc-872f688df0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351208365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3351208365
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2750487151
Short name T598
Test name
Test status
Simulation time 7942597860 ps
CPU time 59.8 seconds
Started Mar 10 02:42:51 PM PDT 24
Finished Mar 10 02:43:51 PM PDT 24
Peak memory 208364 kb
Host smart-f6593c00-9f3f-4810-a70e-5ae2549b6c22
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750487151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2750487151
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3815676204
Short name T499
Test name
Test status
Simulation time 40483918 ps
CPU time 2.44 seconds
Started Mar 10 02:42:49 PM PDT 24
Finished Mar 10 02:42:51 PM PDT 24
Peak memory 206908 kb
Host smart-e489fef7-8fa1-4414-99d4-76550fae8dec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815676204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3815676204
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.608425967
Short name T861
Test name
Test status
Simulation time 89762352 ps
CPU time 3.36 seconds
Started Mar 10 02:42:49 PM PDT 24
Finished Mar 10 02:42:52 PM PDT 24
Peak memory 208380 kb
Host smart-e20cd710-2901-4f03-8b8d-5f5da818e10d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608425967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.608425967
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.149091985
Short name T796
Test name
Test status
Simulation time 235809019 ps
CPU time 3.12 seconds
Started Mar 10 02:42:53 PM PDT 24
Finished Mar 10 02:42:56 PM PDT 24
Peak memory 215580 kb
Host smart-81b44e9a-1677-4f46-a103-fc71a02568d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149091985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.149091985
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3526404583
Short name T519
Test name
Test status
Simulation time 113751102 ps
CPU time 3.36 seconds
Started Mar 10 02:42:47 PM PDT 24
Finished Mar 10 02:42:50 PM PDT 24
Peak memory 208584 kb
Host smart-b13f62f5-e4d7-4cdb-b5ce-1cd9b580b62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526404583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3526404583
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1734970472
Short name T236
Test name
Test status
Simulation time 12572356708 ps
CPU time 225.92 seconds
Started Mar 10 02:42:49 PM PDT 24
Finished Mar 10 02:46:35 PM PDT 24
Peak memory 219584 kb
Host smart-d6a91fe9-ff12-4512-b1a6-e5f269f94b4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734970472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1734970472
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.322981675
Short name T444
Test name
Test status
Simulation time 92942046 ps
CPU time 3.1 seconds
Started Mar 10 02:42:48 PM PDT 24
Finished Mar 10 02:42:51 PM PDT 24
Peak memory 207212 kb
Host smart-6d7ac418-838e-4d42-b178-448d947d7edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322981675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.322981675
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1076136062
Short name T381
Test name
Test status
Simulation time 50496134 ps
CPU time 1.43 seconds
Started Mar 10 02:42:49 PM PDT 24
Finished Mar 10 02:42:51 PM PDT 24
Peak memory 210060 kb
Host smart-a027dae0-7e73-4dcb-8956-64fab6eb8aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076136062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1076136062
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.259396306
Short name T639
Test name
Test status
Simulation time 44048454 ps
CPU time 0.74 seconds
Started Mar 10 02:43:02 PM PDT 24
Finished Mar 10 02:43:02 PM PDT 24
Peak memory 206120 kb
Host smart-cf424e5c-d519-4542-aa99-8f5e3f6e5902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259396306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.259396306
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2266970698
Short name T792
Test name
Test status
Simulation time 248302943 ps
CPU time 3.41 seconds
Started Mar 10 02:42:54 PM PDT 24
Finished Mar 10 02:42:57 PM PDT 24
Peak memory 214524 kb
Host smart-46d212ab-ab52-4128-b644-c81518dbe4fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2266970698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2266970698
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.246613299
Short name T23
Test name
Test status
Simulation time 916514950 ps
CPU time 3.27 seconds
Started Mar 10 02:42:54 PM PDT 24
Finished Mar 10 02:42:58 PM PDT 24
Peak memory 214804 kb
Host smart-96d816a7-691f-447d-8024-88074139bcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246613299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.246613299
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1426406963
Short name T753
Test name
Test status
Simulation time 73797093 ps
CPU time 2.86 seconds
Started Mar 10 02:42:55 PM PDT 24
Finished Mar 10 02:42:58 PM PDT 24
Peak memory 207592 kb
Host smart-cebac23e-ab95-464b-b8d2-547d2cadc523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426406963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1426406963
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.209118500
Short name T257
Test name
Test status
Simulation time 1961273633 ps
CPU time 50.56 seconds
Started Mar 10 02:42:54 PM PDT 24
Finished Mar 10 02:43:44 PM PDT 24
Peak memory 222672 kb
Host smart-09095411-a3f1-4dff-9ce3-4f0b7d066ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209118500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.209118500
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3842950604
Short name T661
Test name
Test status
Simulation time 113558994 ps
CPU time 3.1 seconds
Started Mar 10 02:42:56 PM PDT 24
Finished Mar 10 02:43:00 PM PDT 24
Peak memory 209884 kb
Host smart-4aaf427e-3e7c-4ce0-bee8-46b641daca44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842950604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3842950604
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1609946226
Short name T811
Test name
Test status
Simulation time 112993514 ps
CPU time 5.14 seconds
Started Mar 10 02:42:53 PM PDT 24
Finished Mar 10 02:42:58 PM PDT 24
Peak memory 209292 kb
Host smart-afd805a1-7ac3-47c2-8707-5fb23793150b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609946226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1609946226
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2082137815
Short name T241
Test name
Test status
Simulation time 164867003 ps
CPU time 3.28 seconds
Started Mar 10 02:42:54 PM PDT 24
Finished Mar 10 02:42:57 PM PDT 24
Peak memory 206800 kb
Host smart-eb706551-b0c8-4bfb-939f-eca227872e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082137815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2082137815
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.892928759
Short name T685
Test name
Test status
Simulation time 19868285 ps
CPU time 1.8 seconds
Started Mar 10 02:42:55 PM PDT 24
Finished Mar 10 02:42:58 PM PDT 24
Peak memory 206920 kb
Host smart-55120d2c-dc60-4f63-a2d5-668a030d6f14
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892928759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.892928759
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.4208954963
Short name T103
Test name
Test status
Simulation time 220285964 ps
CPU time 2.85 seconds
Started Mar 10 02:42:54 PM PDT 24
Finished Mar 10 02:42:57 PM PDT 24
Peak memory 206868 kb
Host smart-a3d82efa-ec1e-4da0-8a03-885c10f8e83d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208954963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.4208954963
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1523370705
Short name T726
Test name
Test status
Simulation time 135951478 ps
CPU time 3.92 seconds
Started Mar 10 02:42:56 PM PDT 24
Finished Mar 10 02:43:00 PM PDT 24
Peak memory 208328 kb
Host smart-a2aeb3ac-e2ba-4a2a-b4b7-6f1637573559
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523370705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1523370705
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1550577158
Short name T876
Test name
Test status
Simulation time 22884125 ps
CPU time 1.99 seconds
Started Mar 10 02:42:59 PM PDT 24
Finished Mar 10 02:43:02 PM PDT 24
Peak memory 215600 kb
Host smart-124b8c16-5a2e-447a-8768-3cbc62b25030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550577158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1550577158
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1957779432
Short name T575
Test name
Test status
Simulation time 60148705 ps
CPU time 2.29 seconds
Started Mar 10 02:42:53 PM PDT 24
Finished Mar 10 02:42:55 PM PDT 24
Peak memory 206784 kb
Host smart-8e076e0c-ffce-4dce-a029-9a58b6e98cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957779432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1957779432
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2507690113
Short name T706
Test name
Test status
Simulation time 114372467 ps
CPU time 3.18 seconds
Started Mar 10 02:42:54 PM PDT 24
Finished Mar 10 02:42:57 PM PDT 24
Peak memory 208300 kb
Host smart-6634df0f-0346-4301-b1eb-d16d2bc9794e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507690113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2507690113
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.501117878
Short name T290
Test name
Test status
Simulation time 861030098 ps
CPU time 7.28 seconds
Started Mar 10 02:42:54 PM PDT 24
Finished Mar 10 02:43:02 PM PDT 24
Peak memory 208968 kb
Host smart-7c02453b-40fe-4dfb-a561-d01bee6b0b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501117878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.501117878
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3285519139
Short name T99
Test name
Test status
Simulation time 210349542 ps
CPU time 1.98 seconds
Started Mar 10 02:42:59 PM PDT 24
Finished Mar 10 02:43:01 PM PDT 24
Peak memory 209656 kb
Host smart-24778dde-f350-4112-8347-ab40b78689c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285519139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3285519139
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3721752739
Short name T595
Test name
Test status
Simulation time 43246767 ps
CPU time 1.03 seconds
Started Mar 10 02:43:07 PM PDT 24
Finished Mar 10 02:43:08 PM PDT 24
Peak memory 206396 kb
Host smart-8a98e08e-dba4-437a-b52d-596213655b0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721752739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3721752739
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.709288238
Short name T416
Test name
Test status
Simulation time 135696205 ps
CPU time 7.17 seconds
Started Mar 10 02:43:03 PM PDT 24
Finished Mar 10 02:43:11 PM PDT 24
Peak memory 215756 kb
Host smart-86e38cfa-cfd4-4f7d-a4a0-929280cf2aad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=709288238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.709288238
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1242621434
Short name T871
Test name
Test status
Simulation time 81033670 ps
CPU time 2.78 seconds
Started Mar 10 02:43:03 PM PDT 24
Finished Mar 10 02:43:06 PM PDT 24
Peak memory 207336 kb
Host smart-e6b08905-8abb-4c3e-a018-b462c6909e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242621434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1242621434
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.388984902
Short name T86
Test name
Test status
Simulation time 145123751 ps
CPU time 5.77 seconds
Started Mar 10 02:43:04 PM PDT 24
Finished Mar 10 02:43:10 PM PDT 24
Peak memory 214556 kb
Host smart-7d69e4f2-74a5-46f9-b885-c79fe4cc7f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388984902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.388984902
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2667823294
Short name T362
Test name
Test status
Simulation time 310153401 ps
CPU time 7.01 seconds
Started Mar 10 02:43:02 PM PDT 24
Finished Mar 10 02:43:09 PM PDT 24
Peak memory 214472 kb
Host smart-5a921e4c-9459-4bd8-80da-30d1c2c63a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667823294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2667823294
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1658957570
Short name T755
Test name
Test status
Simulation time 115164860 ps
CPU time 5.41 seconds
Started Mar 10 02:43:04 PM PDT 24
Finished Mar 10 02:43:10 PM PDT 24
Peak memory 222708 kb
Host smart-0ace4e2e-c168-401b-bb9c-7329e641ae09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658957570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1658957570
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.165442348
Short name T192
Test name
Test status
Simulation time 166482188 ps
CPU time 3.93 seconds
Started Mar 10 02:42:56 PM PDT 24
Finished Mar 10 02:43:01 PM PDT 24
Peak memory 208104 kb
Host smart-92f4b9e7-9626-4c9e-a434-b2eb621bc770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165442348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.165442348
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1901987974
Short name T725
Test name
Test status
Simulation time 119827753 ps
CPU time 3.75 seconds
Started Mar 10 02:42:57 PM PDT 24
Finished Mar 10 02:43:01 PM PDT 24
Peak memory 206780 kb
Host smart-c19b94de-fbc4-4bcc-a1d1-203d6d4e197f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901987974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1901987974
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2143370865
Short name T314
Test name
Test status
Simulation time 1084627805 ps
CPU time 11.32 seconds
Started Mar 10 02:42:57 PM PDT 24
Finished Mar 10 02:43:09 PM PDT 24
Peak memory 208380 kb
Host smart-fa5028c4-6abe-4db6-ab19-44928868a05a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143370865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2143370865
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1728482954
Short name T549
Test name
Test status
Simulation time 1079348941 ps
CPU time 15.35 seconds
Started Mar 10 02:43:00 PM PDT 24
Finished Mar 10 02:43:16 PM PDT 24
Peak memory 208620 kb
Host smart-9ebac1e0-a994-44de-8fc2-c89b2705848c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728482954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1728482954
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3090778442
Short name T83
Test name
Test status
Simulation time 183539519 ps
CPU time 5.31 seconds
Started Mar 10 02:42:59 PM PDT 24
Finished Mar 10 02:43:05 PM PDT 24
Peak memory 207804 kb
Host smart-f5fd34cd-e709-47a4-b9bd-7e9f326a0735
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090778442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3090778442
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1031670310
Short name T348
Test name
Test status
Simulation time 254395240 ps
CPU time 2.48 seconds
Started Mar 10 02:43:06 PM PDT 24
Finished Mar 10 02:43:09 PM PDT 24
Peak memory 208980 kb
Host smart-13b86750-6b86-41bc-8413-43e5bf7cd66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031670310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1031670310
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2536685655
Short name T425
Test name
Test status
Simulation time 173306622 ps
CPU time 4.65 seconds
Started Mar 10 02:42:58 PM PDT 24
Finished Mar 10 02:43:03 PM PDT 24
Peak memory 208376 kb
Host smart-708cc211-eb1a-4de0-aa5b-d40a20fce7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536685655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2536685655
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2768020314
Short name T179
Test name
Test status
Simulation time 230000772 ps
CPU time 8.69 seconds
Started Mar 10 02:43:04 PM PDT 24
Finished Mar 10 02:43:13 PM PDT 24
Peak memory 218884 kb
Host smart-e5bf4e01-cfef-4433-b9c2-b734b728d527
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768020314 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2768020314
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2084977349
Short name T736
Test name
Test status
Simulation time 68828161 ps
CPU time 2.85 seconds
Started Mar 10 02:43:03 PM PDT 24
Finished Mar 10 02:43:06 PM PDT 24
Peak memory 209336 kb
Host smart-08f3ed1b-28a9-4b11-8efa-e3264b4382ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084977349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2084977349
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1012154619
Short name T502
Test name
Test status
Simulation time 35183405 ps
CPU time 1.46 seconds
Started Mar 10 02:43:04 PM PDT 24
Finished Mar 10 02:43:06 PM PDT 24
Peak memory 209636 kb
Host smart-29bd75e6-24aa-4c62-90e6-d171fdffa8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012154619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1012154619
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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