Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4372956	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

585163

1

T1

3

T2

282

T3

373

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4563713	1			T1	1		T2	565		T3	1039
values[0x0]	195860	1			T1	3		T2	88		T3	114
values[0x1]	198546	1			T1	5		T2	75		T3	119

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2971403	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1986716

1

T1

4

T2

362

T3

611

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27315	1			T2	4		T3	4		T4	23
valid_sources[0x01]	13546	1			T2	2		T3	6		T4	18
valid_sources[0x02]	13887	1			T2	6		T3	15		T4	22
valid_sources[0x03]	13629	1			T2	4		T3	4		T4	32
valid_sources[0x04]	22786	1			T2	1		T3	7		T4	20
valid_sources[0x05]	17537	1			T2	6		T3	5		T4	18
valid_sources[0x06]	14386	1			T2	2		T3	6		T4	22
valid_sources[0x07]	15148	1			T2	4		T3	2		T4	28
valid_sources[0x08]	13848	1			T2	1		T3	10		T4	20
valid_sources[0x09]	15916	1			T1	2		T2	3		T3	13
valid_sources[0x0a]	20372	1			T2	4		T3	5		T4	20
valid_sources[0x0b]	14109	1			T2	3		T3	3		T4	34
valid_sources[0x0c]	13801	1			T2	2		T3	2		T4	24
valid_sources[0x0d]	14415	1			T2	2		T4	31		T5	39
valid_sources[0x0e]	14098	1			T2	1		T3	3		T4	16
valid_sources[0x0f]	14513	1			T2	3		T3	1		T4	12
valid_sources[0x10]	34841	1			T2	4		T3	7		T4	20
valid_sources[0x11]	13934	1			T3	3		T4	28		T5	16
valid_sources[0x12]	16032	1			T2	2		T3	8		T4	16
valid_sources[0x13]	20650	1			T2	3		T3	4		T4	19
valid_sources[0x14]	14685	1			T2	1		T3	11		T4	25
valid_sources[0x15]	15170	1			T2	1		T3	7		T4	29
valid_sources[0x16]	14125	1			T2	3		T3	10		T4	39
valid_sources[0x17]	14902	1			T2	4		T3	10		T4	21
valid_sources[0x18]	15102	1			T2	5		T3	1		T4	28
valid_sources[0x19]	14544	1			T2	3		T3	6		T4	27
valid_sources[0x1a]	13307	1			T2	2		T3	6		T4	21
valid_sources[0x1b]	20081	1			T2	2		T3	2		T4	35
valid_sources[0x1c]	13930	1			T2	4		T3	12		T4	29
valid_sources[0x1d]	14257	1			T2	4		T3	6		T4	27
valid_sources[0x1e]	14076	1			T2	1		T3	2		T4	17
valid_sources[0x1f]	16341	1			T2	4		T3	3		T4	29
valid_sources[0x20]	15503	1			T2	5		T3	6		T4	24
valid_sources[0x21]	14884	1			T2	1		T3	8		T4	42
valid_sources[0x22]	14033	1			T2	4		T3	6		T4	22
valid_sources[0x23]	13558	1			T2	2		T3	6		T4	37
valid_sources[0x24]	14256	1			T2	1		T3	7		T4	31
valid_sources[0x25]	13435	1			T2	2		T3	8		T4	15
valid_sources[0x26]	15364	1			T2	7		T3	3		T4	12
valid_sources[0x27]	13936	1			T2	2		T3	8		T4	25
valid_sources[0x28]	19564	1			T1	2		T2	4		T3	10
valid_sources[0x29]	14003	1			T2	3		T3	1		T4	30
valid_sources[0x2a]	33948	1			T2	4		T4	26		T5	36
valid_sources[0x2b]	18419	1			T2	1		T4	22		T5	51
valid_sources[0x2c]	53055	1			T2	4		T3	1		T4	18
valid_sources[0x2d]	14155	1			T2	3		T3	5		T4	26
valid_sources[0x2e]	15243	1			T2	3		T4	37		T5	11
valid_sources[0x2f]	15144	1			T2	3		T3	3		T4	15
valid_sources[0x30]	13573	1			T2	3		T3	10		T4	19
valid_sources[0x31]	15575	1			T2	4		T3	6		T4	27
valid_sources[0x32]	15384	1			T2	6		T3	6		T4	25
valid_sources[0x33]	14721	1			T2	4		T3	9		T4	39
valid_sources[0x34]	15031	1			T2	5		T3	8		T4	26
valid_sources[0x35]	14621	1			T2	2		T3	5		T4	24
valid_sources[0x36]	14565	1			T2	4		T3	8		T4	37
valid_sources[0x37]	22562	1			T2	5		T3	6		T4	32
valid_sources[0x38]	14332	1			T2	3		T3	9		T4	16
valid_sources[0x39]	15826	1			T2	1		T3	1		T4	21
valid_sources[0x3a]	14649	1			T1	1		T2	6		T3	6
valid_sources[0x3b]	392941	1			T2	4		T3	10		T4	22
valid_sources[0x3c]	15125	1			T3	3		T4	29		T5	12
valid_sources[0x3d]	13515	1			T2	4		T3	14		T4	36
valid_sources[0x3e]	16816	1			T3	8		T4	25		T5	46
valid_sources[0x3f]	16480	1			T2	8		T3	8		T4	25
valid_sources[0x40]	14712	1			T2	1		T3	2		T4	31
valid_sources[0x41]	13183	1			T2	5		T3	13		T4	28
valid_sources[0x42]	16857	1			T2	3		T3	2		T4	21
valid_sources[0x43]	14074	1			T2	4		T3	1		T4	24
valid_sources[0x44]	63355	1			T2	4		T3	6		T4	24
valid_sources[0x45]	14683	1			T2	1		T3	5		T4	30
valid_sources[0x46]	15506	1			T2	3		T3	4		T4	28
valid_sources[0x47]	15918	1			T2	5		T3	2		T4	17
valid_sources[0x48]	54613	1			T2	1		T3	3		T4	22
valid_sources[0x49]	14118	1			T2	4		T3	6		T4	27
valid_sources[0x4a]	14562	1			T2	1		T3	9		T4	27
valid_sources[0x4b]	15191	1			T2	3		T3	4		T4	34
valid_sources[0x4c]	14163	1			T2	3		T3	6		T4	40
valid_sources[0x4d]	14599	1			T2	1		T3	4		T4	31
valid_sources[0x4e]	13196	1			T2	1		T3	7		T4	27
valid_sources[0x4f]	13039	1			T2	3		T3	5		T4	25
valid_sources[0x50]	13389	1			T1	2		T2	4		T3	3
valid_sources[0x51]	13930	1			T2	1		T3	6		T4	33
valid_sources[0x52]	14485	1			T2	2		T4	22		T5	15
valid_sources[0x53]	15882	1			T2	5		T3	3		T4	28
valid_sources[0x54]	16600	1			T2	2		T3	8		T4	41
valid_sources[0x55]	14831	1			T2	7		T3	1		T4	31
valid_sources[0x56]	14895	1			T2	3		T3	1		T4	33
valid_sources[0x57]	14280	1			T2	3		T3	8		T4	31
valid_sources[0x58]	16714	1			T2	4		T3	6		T4	34
valid_sources[0x59]	24214	1			T3	2		T4	36		T5	34
valid_sources[0x5a]	13752	1			T2	3		T3	6		T4	20
valid_sources[0x5b]	13339	1			T2	3		T3	4		T4	18
valid_sources[0x5c]	21318	1			T2	4		T3	1		T4	30
valid_sources[0x5d]	15909	1			T2	5		T3	4		T4	23
valid_sources[0x5e]	15272	1			T2	1		T3	5		T4	22
valid_sources[0x5f]	14364	1			T2	2		T3	3		T4	33
valid_sources[0x60]	20204	1			T2	8		T3	6		T4	14
valid_sources[0x61]	14222	1			T2	3		T3	6		T4	25
valid_sources[0x62]	15790	1			T2	3		T3	5		T4	25
valid_sources[0x63]	18438	1			T2	5		T3	2		T4	32
valid_sources[0x64]	16274	1			T3	10		T4	22		T5	24
valid_sources[0x65]	14512	1			T2	2		T3	5		T4	15
valid_sources[0x66]	13728	1			T2	1		T3	9		T4	21
valid_sources[0x67]	13892	1			T2	4		T3	6		T4	21
valid_sources[0x68]	29634	1			T2	1		T3	5		T4	30
valid_sources[0x69]	15670	1			T3	6		T4	27		T5	8
valid_sources[0x6a]	14770	1			T2	2		T3	3		T4	29
valid_sources[0x6b]	14581	1			T2	5		T3	2		T4	15
valid_sources[0x6c]	45258	1			T2	2		T3	3		T4	18
valid_sources[0x6d]	15175	1			T2	5		T3	4		T4	33
valid_sources[0x6e]	15173	1			T2	3		T3	1		T4	37
valid_sources[0x6f]	14722	1			T2	2		T3	1		T4	18
valid_sources[0x70]	15285	1			T2	1		T3	5		T4	27
valid_sources[0x71]	51309	1			T2	1		T3	4		T4	21
valid_sources[0x72]	15017	1			T2	2		T3	2		T4	22
valid_sources[0x73]	14286	1			T2	2		T3	4		T4	21
valid_sources[0x74]	14769	1			T2	1		T3	2		T4	27
valid_sources[0x75]	42283	1			T2	2		T3	4		T4	22
valid_sources[0x76]	13537	1			T2	1		T3	4		T4	25
valid_sources[0x77]	21975	1			T2	1		T3	2		T4	18
valid_sources[0x78]	14169	1			T2	5		T3	1		T4	22
valid_sources[0x79]	17474	1			T2	4		T3	1		T4	17
valid_sources[0x7a]	19061	1			T2	4		T3	2		T4	34
valid_sources[0x7b]	15987	1			T2	2		T3	6		T4	21
valid_sources[0x7c]	14979	1			T2	2		T3	4		T4	24
valid_sources[0x7d]	14937	1			T2	1		T3	3		T4	24
valid_sources[0x7e]	13489	1			T3	3		T4	19		T5	40
valid_sources[0x7f]	13925	1			T2	3		T3	3		T4	25
valid_sources[0x80]	25171	1			T2	1		T3	6		T4	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

318154

1

T1

1

T2

229

T3

302

values[0x0]

all_enables

biggest_size

140605

1

T2

35

T3

45

T4

50

values[0x1]

all_enables

biggest_size

126404

1

T1

2

T2

18

T3

26