Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	29444472	12803	0	0
attest_sw_binding_0_rd_A	29444472	2909	0	0
attest_sw_binding_1_rd_A	29444472	2960	0	0
attest_sw_binding_2_rd_A	29444472	3016	0	0
attest_sw_binding_3_rd_A	29444472	2990	0	0
attest_sw_binding_4_rd_A	29444472	2909	0	0
attest_sw_binding_5_rd_A	29444472	2874	0	0
attest_sw_binding_6_rd_A	29444472	3028	0	0
attest_sw_binding_7_rd_A	29444472	2866	0	0
intr_enable_rd_A	29444472	3701	0	0
key_version_rd_A	29444472	2877	0	0
max_creator_key_ver_regwen_rd_A	29444472	2848	0	0
max_owner_int_key_ver_regwen_rd_A	29444472	3039	0	0
max_owner_key_ver_regwen_rd_A	29444472	3013	0	0
reseed_interval_regwen_rd_A	29444472	3103	0	0
salt_0_rd_A	29444472	2905	0	0
salt_1_rd_A	29444472	3140	0	0
salt_2_rd_A	29444472	2990	0	0
salt_3_rd_A	29444472	2937	0	0
salt_4_rd_A	29444472	2890	0	0
salt_5_rd_A	29444472	2841	0	0
salt_6_rd_A	29444472	2806	0	0
salt_7_rd_A	29444472	3050	0	0
sealing_sw_binding_0_rd_A	29444472	2862	0	0
sealing_sw_binding_1_rd_A	29444472	3063	0	0
sealing_sw_binding_2_rd_A	29444472	2957	0	0
sealing_sw_binding_3_rd_A	29444472	3058	0	0
sealing_sw_binding_4_rd_A	29444472	3109	0	0
sealing_sw_binding_5_rd_A	29444472	3085	0	0
sealing_sw_binding_6_rd_A	29444472	3078	0	0
sealing_sw_binding_7_rd_A	29444472	2759	0	0
sideload_clear_rd_A	29444472	3020	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	12803	0	0
T62	5559	0	0	0
T114	18382	287	0	0
T115	0	853	0	0
T116	0	576	0	0
T129	0	445	0	0
T130	0	228	0	0
T131	0	152	0	0
T133	0	255	0	0
T134	0	224	0	0
T135	0	63	0	0
T136	7083	0	0	0
T137	8289	0	0	0
T138	7239	0	0	0
T139	7287	0	0	0
T140	5806	0	0	0
T141	1234	0	0	0
T142	7957	0	0	0
T143	5613	0	0	0
T180	0	75	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	2909	0	0
T41	6220	0	0	0
T118	0	94	0	0
T119	0	174	0	0
T125	0	56	0	0
T130	38749	34	0	0
T131	0	52	0	0
T134	0	39	0	0
T135	0	34	0	0
T163	0	455	0	0
T180	0	4	0	0
T190	5760	0	0	0
T196	0	22	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	2960	0	0
T41	6220	0	0	0
T118	0	106	0	0
T119	0	188	0	0
T125	0	44	0	0
T130	38749	36	0	0
T131	0	53	0	0
T134	0	38	0	0
T135	0	31	0	0
T163	0	485	0	0
T180	0	20	0	0
T190	5760	0	0	0
T196	0	38	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	3016	0	0
T41	6220	0	0	0
T118	0	122	0	0
T119	0	206	0	0
T125	0	83	0	0
T130	38749	52	0	0
T131	0	56	0	0
T134	0	23	0	0
T135	0	36	0	0
T163	0	451	0	0
T180	0	22	0	0
T190	5760	0	0	0
T196	0	25	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	2990	0	0
T41	6220	0	0	0
T118	0	87	0	0
T119	0	211	0	0
T125	0	50	0	0
T130	38749	19	0	0
T131	0	71	0	0
T134	0	29	0	0
T135	0	37	0	0
T163	0	437	0	0
T180	0	38	0	0
T190	5760	0	0	0
T196	0	29	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	2909	0	0
T41	6220	0	0	0
T118	0	106	0	0
T119	0	187	0	0
T125	0	48	0	0
T130	38749	25	0	0
T131	0	52	0	0
T134	0	28	0	0
T135	0	20	0	0
T163	0	434	0	0
T180	0	33	0	0
T190	5760	0	0	0
T196	0	62	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	2874	0	0
T41	6220	0	0	0
T118	0	107	0	0
T119	0	180	0	0
T125	0	38	0	0
T130	38749	26	0	0
T131	0	42	0	0
T134	0	19	0	0
T135	0	29	0	0
T163	0	440	0	0
T180	0	30	0	0
T190	5760	0	0	0
T196	0	26	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	3028	0	0
T41	6220	0	0	0
T118	0	88	0	0
T119	0	230	0	0
T125	0	77	0	0
T130	38749	31	0	0
T131	0	48	0	0
T134	0	36	0	0
T135	0	25	0	0
T163	0	485	0	0
T180	0	30	0	0
T190	5760	0	0	0
T196	0	27	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	2866	0	0
T41	6220	0	0	0
T118	0	102	0	0
T119	0	215	0	0
T125	0	69	0	0
T130	38749	48	0	0
T131	0	49	0	0
T134	0	50	0	0
T135	0	18	0	0
T163	0	511	0	0
T180	0	16	0	0
T190	5760	0	0	0
T196	0	34	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	3701	0	0
T69	117419	10	0	0
T130	0	52	0	0
T131	0	83	0	0
T134	0	47	0	0
T204	0	23	0	0
T205	0	43	0	0
T206	0	34	0	0
T207	0	18	0	0
T208	0	104	0	0
T209	0	19	0	0
T210	18986	0	0	0
T211	3028	0	0	0
T212	5076	0	0	0
T213	15134	0	0	0
T214	21926	0	0	0
T215	3453	0	0	0
T216	81625	0	0	0
T217	3952	0	0	0
T218	12526	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	2877	0	0
T41	6220	0	0	0
T118	0	100	0	0
T119	0	203	0	0
T125	0	80	0	0
T130	38749	21	0	0
T131	0	41	0	0
T134	0	24	0	0
T135	0	27	0	0
T163	0	456	0	0
T180	0	30	0	0
T190	5760	0	0	0
T196	0	40	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	2848	0	0
T41	6220	0	0	0
T118	0	102	0	0
T119	0	207	0	0
T125	0	76	0	0
T130	38749	26	0	0
T131	0	45	0	0
T134	0	28	0	0
T135	0	18	0	0
T163	0	473	0	0
T180	0	26	0	0
T190	5760	0	0	0
T196	0	21	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	3039	0	0
T41	6220	0	0	0
T118	0	100	0	0
T119	0	197	0	0
T125	0	93	0	0
T130	38749	21	0	0
T131	0	37	0	0
T134	0	35	0	0
T135	0	15	0	0
T163	0	501	0	0
T180	0	30	0	0
T190	5760	0	0	0
T196	0	34	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	3013	0	0
T41	6220	0	0	0
T118	0	109	0	0
T119	0	188	0	0
T125	0	88	0	0
T130	38749	22	0	0
T131	0	43	0	0
T134	0	22	0	0
T135	0	30	0	0
T163	0	456	0	0
T180	0	16	0	0
T190	5760	0	0	0
T196	0	36	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	3103	0	0
T41	6220	0	0	0
T118	0	84	0	0
T119	0	196	0	0
T125	0	67	0	0
T130	38749	39	0	0
T131	0	77	0	0
T134	0	36	0	0
T135	0	35	0	0
T163	0	477	0	0
T180	0	34	0	0
T190	5760	0	0	0
T196	0	40	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	2905	0	0
T41	6220	0	0	0
T118	0	93	0	0
T119	0	216	0	0
T125	0	57	0	0
T130	38749	14	0	0
T131	0	32	0	0
T134	0	48	0	0
T135	0	22	0	0
T163	0	467	0	0
T180	0	26	0	0
T190	5760	0	0	0
T196	0	36	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	3140	0	0
T41	6220	0	0	0
T118	0	85	0	0
T119	0	219	0	0
T125	0	75	0	0
T130	38749	40	0	0
T131	0	54	0	0
T134	0	25	0	0
T135	0	21	0	0
T163	0	493	0	0
T180	0	14	0	0
T190	5760	0	0	0
T196	0	60	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	2990	0	0
T41	6220	0	0	0
T118	0	104	0	0
T119	0	172	0	0
T125	0	65	0	0
T130	38749	50	0	0
T131	0	38	0	0
T134	0	43	0	0
T135	0	23	0	0
T163	0	444	0	0
T180	0	28	0	0
T190	5760	0	0	0
T196	0	25	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	2937	0	0
T41	6220	0	0	0
T118	0	111	0	0
T119	0	192	0	0
T125	0	72	0	0
T130	38749	26	0	0
T131	0	62	0	0
T134	0	15	0	0
T135	0	16	0	0
T163	0	516	0	0
T180	0	20	0	0
T190	5760	0	0	0
T196	0	22	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	2890	0	0
T118	0	116	0	0
T119	0	221	0	0
T130	0	27	0	0
T131	0	34	0	0
T134	0	65	0	0
T135	0	23	0	0
T156	6345	0	0	0
T163	0	445	0	0
T180	0	35	0	0
T181	5791	0	0	0
T196	0	15	0	0
T204	173468	0	0	0
T219	8268	9	0	0
T220	6471	0	0	0
T221	50520	0	0	0
T222	9772	0	0	0
T223	878	0	0	0
T224	146424	0	0	0
T225	1563	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	2841	0	0
T41	6220	0	0	0
T118	0	114	0	0
T119	0	195	0	0
T125	0	65	0	0
T130	38749	40	0	0
T131	0	39	0	0
T134	0	25	0	0
T135	0	11	0	0
T163	0	444	0	0
T180	0	30	0	0
T190	5760	0	0	0
T196	0	33	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	2806	0	0
T41	6220	0	0	0
T118	0	87	0	0
T119	0	190	0	0
T125	0	60	0	0
T130	38749	32	0	0
T131	0	42	0	0
T134	0	40	0	0
T135	0	23	0	0
T163	0	457	0	0
T180	0	31	0	0
T190	5760	0	0	0
T196	0	31	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	3050	0	0
T41	6220	0	0	0
T118	0	89	0	0
T119	0	167	0	0
T125	0	57	0	0
T130	38749	26	0	0
T131	0	45	0	0
T134	0	35	0	0
T135	0	36	0	0
T163	0	520	0	0
T180	0	22	0	0
T190	5760	0	0	0
T196	0	18	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	2862	0	0
T41	6220	0	0	0
T118	0	88	0	0
T119	0	203	0	0
T125	0	56	0	0
T130	38749	25	0	0
T131	0	55	0	0
T134	0	53	0	0
T135	0	23	0	0
T163	0	476	0	0
T180	0	22	0	0
T190	5760	0	0	0
T196	0	24	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	3063	0	0
T41	6220	0	0	0
T118	0	106	0	0
T119	0	223	0	0
T125	0	56	0	0
T130	38749	21	0	0
T131	0	51	0	0
T134	0	21	0	0
T135	0	12	0	0
T163	0	485	0	0
T180	0	23	0	0
T190	5760	0	0	0
T196	0	16	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	2957	0	0
T41	6220	0	0	0
T118	0	101	0	0
T119	0	239	0	0
T125	0	60	0	0
T130	38749	19	0	0
T131	0	58	0	0
T134	0	17	0	0
T135	0	26	0	0
T163	0	456	0	0
T180	0	18	0	0
T190	5760	0	0	0
T196	0	47	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	3058	0	0
T41	6220	0	0	0
T118	0	112	0	0
T119	0	199	0	0
T125	0	53	0	0
T130	38749	20	0	0
T131	0	47	0	0
T134	0	42	0	0
T135	0	32	0	0
T163	0	525	0	0
T180	0	19	0	0
T190	5760	0	0	0
T196	0	26	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	3109	0	0
T41	6220	0	0	0
T118	0	93	0	0
T119	0	217	0	0
T125	0	48	0	0
T130	38749	27	0	0
T131	0	38	0	0
T134	0	40	0	0
T135	0	21	0	0
T163	0	459	0	0
T180	0	13	0	0
T190	5760	0	0	0
T196	0	53	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	3085	0	0
T41	6220	0	0	0
T118	0	95	0	0
T119	0	179	0	0
T125	0	64	0	0
T130	38749	24	0	0
T131	0	42	0	0
T134	0	43	0	0
T135	0	44	0	0
T163	0	507	0	0
T180	0	40	0	0
T190	5760	0	0	0
T196	0	26	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	3078	0	0
T41	6220	0	0	0
T118	0	92	0	0
T119	0	238	0	0
T125	0	74	0	0
T130	38749	21	0	0
T131	0	57	0	0
T134	0	33	0	0
T135	0	30	0	0
T163	0	556	0	0
T180	0	11	0	0
T190	5760	0	0	0
T196	0	42	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	2759	0	0
T41	6220	0	0	0
T118	0	86	0	0
T119	0	179	0	0
T125	0	58	0	0
T130	38749	25	0	0
T131	0	22	0	0
T134	0	30	0	0
T135	0	33	0	0
T163	0	417	0	0
T180	0	23	0	0
T190	5760	0	0	0
T196	0	27	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29444472	3020	0	0
T41	6220	0	0	0
T118	0	96	0	0
T119	0	228	0	0
T125	0	62	0	0
T130	38749	19	0	0
T131	0	37	0	0
T134	0	48	0	0
T135	0	15	0	0
T163	0	500	0	0
T180	0	32	0	0
T190	5760	0	0	0
T196	0	29	0	0
T197	116900	0	0	0
T198	5995	0	0	0
T199	1619	0	0	0
T200	10860	0	0	0
T201	94431	0	0	0
T202	67665	0	0	0
T203	6275	0	0	0