Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4230163	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

687084

1

T1

534

T2

363

T3

160

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4476186	1			T1	1829		T2	564		T3	2068
values[0x0]	219074	1			T1	192		T2	149		T3	41
values[0x1]	221987	1			T1	184		T2	156		T3	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2887029	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2030218

1

T1

1040

T2

504

T3

816

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27567	1			T1	9		T11	7		T14	5
valid_sources[0x01]	15419	1			T1	3		T11	1		T14	5
valid_sources[0x02]	16830	1			T1	8		T11	4		T14	3
valid_sources[0x03]	28242	1			T1	10		T11	1		T14	10
valid_sources[0x04]	16253	1			T1	3		T11	3		T14	6
valid_sources[0x05]	20916	1			T1	7		T11	1		T14	6
valid_sources[0x06]	16835	1			T1	11		T11	2		T14	1
valid_sources[0x07]	21168	1			T1	11		T11	3		T12	5337
valid_sources[0x08]	18020	1			T1	7		T11	2		T14	2
valid_sources[0x09]	17409	1			T1	7		T11	1		T14	12
valid_sources[0x0a]	16374	1			T1	8		T14	2		T15	1
valid_sources[0x0b]	18865	1			T1	7		T11	2		T14	2
valid_sources[0x0c]	15844	1			T1	13		T11	2		T14	2
valid_sources[0x0d]	17204	1			T1	6		T11	3		T14	5
valid_sources[0x0e]	15390	1			T1	6		T11	3		T14	5
valid_sources[0x0f]	22696	1			T1	7		T11	2		T14	13
valid_sources[0x10]	15452	1			T1	5		T11	3		T14	6
valid_sources[0x11]	15736	1			T1	8		T11	6		T14	2
valid_sources[0x12]	22937	1			T1	6		T14	3		T15	1
valid_sources[0x13]	16804	1			T1	10		T14	2		T15	7
valid_sources[0x14]	16637	1			T1	7		T11	2		T14	3
valid_sources[0x15]	15571	1			T1	10		T11	1		T14	6
valid_sources[0x16]	18766	1			T1	5		T11	5		T14	7
valid_sources[0x17]	15871	1			T1	14		T14	3		T15	1
valid_sources[0x18]	25450	1			T1	8		T11	1		T14	5
valid_sources[0x19]	22499	1			T1	10		T14	5		T15	2
valid_sources[0x1a]	17780	1			T1	15		T11	2		T14	5
valid_sources[0x1b]	17538	1			T1	5		T14	4		T15	2
valid_sources[0x1c]	19117	1			T1	14		T11	1		T14	4
valid_sources[0x1d]	26880	1			T1	8		T11	6		T14	4
valid_sources[0x1e]	38445	1			T1	3		T11	1		T14	1
valid_sources[0x1f]	16221	1			T1	11		T11	3		T14	3
valid_sources[0x20]	53291	1			T1	5		T11	5		T14	8
valid_sources[0x21]	19054	1			T1	8		T11	3		T14	1
valid_sources[0x22]	15397	1			T1	5		T11	1		T14	11
valid_sources[0x23]	16574	1			T1	9		T11	3		T14	5
valid_sources[0x24]	15599	1			T1	7		T11	1		T14	4
valid_sources[0x25]	15809	1			T1	7		T11	4		T14	2
valid_sources[0x26]	18451	1			T1	12		T11	2		T14	2
valid_sources[0x27]	17738	1			T1	10		T11	4		T14	3
valid_sources[0x28]	15496	1			T1	10		T14	4		T15	2
valid_sources[0x29]	17730	1			T1	9		T14	5		T16	6
valid_sources[0x2a]	19224	1			T1	9		T11	1		T14	11
valid_sources[0x2b]	16271	1			T1	6		T11	2		T14	1
valid_sources[0x2c]	16074	1			T1	16		T11	3		T14	6
valid_sources[0x2d]	25226	1			T1	9		T11	6		T14	3
valid_sources[0x2e]	20245	1			T1	9		T11	5		T14	9
valid_sources[0x2f]	25345	1			T1	11		T14	5		T15	4
valid_sources[0x30]	16149	1			T1	14		T11	2		T14	7
valid_sources[0x31]	17576	1			T1	12		T11	4		T14	5
valid_sources[0x32]	33216	1			T1	13		T11	9		T14	7
valid_sources[0x33]	16016	1			T1	10		T11	2		T14	4
valid_sources[0x34]	18853	1			T1	14		T11	1		T14	5
valid_sources[0x35]	17689	1			T1	9		T14	6		T15	1
valid_sources[0x36]	31637	1			T1	3		T14	3		T15	1
valid_sources[0x37]	15410	1			T1	7		T11	2		T14	7
valid_sources[0x38]	15878	1			T1	12		T11	3		T14	7
valid_sources[0x39]	15588	1			T1	11		T14	7		T15	2
valid_sources[0x3a]	16033	1			T1	9		T11	4		T14	2
valid_sources[0x3b]	19057	1			T1	7		T11	2		T14	4
valid_sources[0x3c]	18346	1			T1	8		T11	3		T14	4
valid_sources[0x3d]	15565	1			T1	10		T14	3		T15	4
valid_sources[0x3e]	17480	1			T1	8		T11	2		T14	6
valid_sources[0x3f]	15535	1			T1	6		T14	2		T15	1
valid_sources[0x40]	15845	1			T1	12		T11	3		T14	2
valid_sources[0x41]	18935	1			T1	7		T2	869		T11	2
valid_sources[0x42]	14979	1			T1	10		T14	7		T15	2
valid_sources[0x43]	18801	1			T1	6		T11	4		T16	3
valid_sources[0x44]	28739	1			T1	4		T11	2		T14	2
valid_sources[0x45]	16966	1			T1	11		T11	2		T14	5
valid_sources[0x46]	17016	1			T1	7		T11	2		T14	8
valid_sources[0x47]	17029	1			T1	3		T11	2		T14	2
valid_sources[0x48]	15846	1			T1	10		T11	6		T14	3
valid_sources[0x49]	16116	1			T1	5		T16	5		T22	10
valid_sources[0x4a]	19809	1			T1	8		T11	1		T14	4
valid_sources[0x4b]	76748	1			T1	13		T14	1		T15	2
valid_sources[0x4c]	17581	1			T1	10		T11	2		T14	6
valid_sources[0x4d]	20438	1			T1	6		T11	1		T14	6
valid_sources[0x4e]	19600	1			T1	10		T11	1		T14	6
valid_sources[0x4f]	31085	1			T1	4		T11	1		T14	5
valid_sources[0x50]	19288	1			T1	8		T11	3		T14	4
valid_sources[0x51]	15036	1			T1	12		T14	1		T15	4
valid_sources[0x52]	17112	1			T1	12		T11	4		T14	8
valid_sources[0x53]	16448	1			T1	8		T14	3		T15	1
valid_sources[0x54]	19895	1			T1	2		T11	1		T16	4
valid_sources[0x55]	15630	1			T1	8		T11	3		T14	7
valid_sources[0x56]	16786	1			T1	9		T11	6		T14	4
valid_sources[0x57]	20991	1			T1	7		T11	6		T14	5
valid_sources[0x58]	18013	1			T1	10		T11	3		T14	5
valid_sources[0x59]	25921	1			T1	7		T11	5		T14	3
valid_sources[0x5a]	20241	1			T1	10		T14	6		T15	11
valid_sources[0x5b]	15813	1			T1	10		T11	1		T14	9
valid_sources[0x5c]	18408	1			T1	4		T11	2		T14	4
valid_sources[0x5d]	17378	1			T1	10		T14	13		T15	3
valid_sources[0x5e]	16040	1			T1	9		T11	1		T14	10
valid_sources[0x5f]	18337	1			T1	9		T14	3		T16	3
valid_sources[0x60]	16275	1			T1	7		T11	2		T15	3
valid_sources[0x61]	18939	1			T1	10		T11	5		T14	7
valid_sources[0x62]	16805	1			T1	4		T14	11		T15	2
valid_sources[0x63]	15471	1			T1	6		T14	5		T15	1
valid_sources[0x64]	18198	1			T1	3		T11	3		T14	2
valid_sources[0x65]	15975	1			T1	12		T11	1		T14	4
valid_sources[0x66]	19146	1			T1	5		T11	4		T14	9
valid_sources[0x67]	16529	1			T1	7		T11	1		T14	5
valid_sources[0x68]	16871	1			T1	7		T11	1		T14	13
valid_sources[0x69]	16256	1			T1	10		T11	4		T14	10
valid_sources[0x6a]	15245	1			T1	14		T11	1		T14	2
valid_sources[0x6b]	16965	1			T1	7		T11	6		T14	2
valid_sources[0x6c]	25657	1			T1	7		T11	3		T14	4
valid_sources[0x6d]	14999	1			T1	8		T14	2		T15	3
valid_sources[0x6e]	16103	1			T1	13		T11	1		T14	7
valid_sources[0x6f]	20602	1			T1	7		T14	4		T15	1
valid_sources[0x70]	16816	1			T1	7		T11	6		T14	7
valid_sources[0x71]	18226	1			T1	17		T11	2		T14	3
valid_sources[0x72]	18686	1			T1	7		T11	5		T14	9
valid_sources[0x73]	16622	1			T1	9		T11	3		T14	3
valid_sources[0x74]	16207	1			T1	9		T11	1		T14	7
valid_sources[0x75]	16700	1			T1	6		T11	1		T14	7
valid_sources[0x76]	16079	1			T1	6		T14	1		T22	18
valid_sources[0x77]	17086	1			T1	6		T11	3		T14	5
valid_sources[0x78]	22097	1			T1	6		T11	1		T14	8
valid_sources[0x79]	16937	1			T1	9		T11	6		T14	7
valid_sources[0x7a]	31660	1			T1	13		T11	3		T14	5
valid_sources[0x7b]	15729	1			T1	13		T11	1		T14	6
valid_sources[0x7c]	15694	1			T1	9		T11	1		T14	6
valid_sources[0x7d]	15898	1			T1	6		T11	3		T14	8
valid_sources[0x7e]	20799	1			T1	9		T14	3		T15	1
valid_sources[0x7f]	16860	1			T1	10		T11	1		T14	10
valid_sources[0x80]	17513	1			T1	7		T14	9		T15	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

385533

1

T1

303

T2

169

T3

125

values[0x0]

all_enables

biggest_size

158236

1

T1

126

T2

111

T3

17

values[0x1]

all_enables

biggest_size

143315

1

T1

105

T2

83

T3

18