Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	31153682	14819	0	0
attest_sw_binding_0_rd_A	31153682	2206	0	0
attest_sw_binding_1_rd_A	31153682	2213	0	0
attest_sw_binding_2_rd_A	31153682	2311	0	0
attest_sw_binding_3_rd_A	31153682	2217	0	0
attest_sw_binding_4_rd_A	31153682	2175	0	0
attest_sw_binding_5_rd_A	31153682	2201	0	0
attest_sw_binding_6_rd_A	31153682	2061	0	0
attest_sw_binding_7_rd_A	31153682	2290	0	0
intr_enable_rd_A	31153682	2678	0	0
key_version_rd_A	31153682	2156	0	0
max_creator_key_ver_regwen_rd_A	31153682	2032	0	0
max_owner_int_key_ver_regwen_rd_A	31153682	2199	0	0
max_owner_key_ver_regwen_rd_A	31153682	2195	0	0
reseed_interval_regwen_rd_A	31153682	2133	0	0
salt_0_rd_A	31153682	2248	0	0
salt_1_rd_A	31153682	2226	0	0
salt_2_rd_A	31153682	2171	0	0
salt_3_rd_A	31153682	2120	0	0
salt_4_rd_A	31153682	2182	0	0
salt_5_rd_A	31153682	2110	0	0
salt_6_rd_A	31153682	2317	0	0
salt_7_rd_A	31153682	2253	0	0
sealing_sw_binding_0_rd_A	31153682	2240	0	0
sealing_sw_binding_1_rd_A	31153682	2275	0	0
sealing_sw_binding_2_rd_A	31153682	2139	0	0
sealing_sw_binding_3_rd_A	31153682	2248	0	0
sealing_sw_binding_4_rd_A	31153682	2323	0	0
sealing_sw_binding_5_rd_A	31153682	2215	0	0
sealing_sw_binding_6_rd_A	31153682	2300	0	0
sealing_sw_binding_7_rd_A	31153682	2136	0	0
sideload_clear_rd_A	31153682	2215	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	14819	0	0
T19	169641	0	0	0
T22	12122	286	0	0
T31	5877	0	0	0
T40	5763	0	0	0
T48	0	428	0	0
T69	0	1179	0	0
T102	5064	0	0	0
T105	20186	0	0	0
T106	22764	0	0	0
T107	4890	0	0	0
T108	10218	0	0	0
T109	25764	0	0	0
T110	0	204	0	0
T121	0	399	0	0
T122	0	244	0	0
T123	0	1008	0	0
T125	0	110	0	0
T126	0	474	0	0
T127	0	190	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2206	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	53	0	0
T127	0	45	0	0
T142	0	283	0	0
T177	0	11	0	0
T178	0	36	0	0
T179	0	29	0	0
T180	0	11	0	0
T181	0	239	0	0
T182	0	5	0	0
T183	0	3	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2213	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	66	0	0
T127	0	17	0	0
T142	0	229	0	0
T177	0	26	0	0
T178	0	18	0	0
T179	0	24	0	0
T180	0	1	0	0
T181	0	231	0	0
T182	0	12	0	0
T183	0	5	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2311	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	59	0	0
T127	0	23	0	0
T142	0	333	0	0
T177	0	33	0	0
T178	0	15	0	0
T179	0	2	0	0
T181	0	260	0	0
T182	0	1	0	0
T183	0	13	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0
T190	0	11	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2217	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	45	0	0
T127	0	35	0	0
T142	0	266	0	0
T177	0	34	0	0
T178	0	18	0	0
T179	0	35	0	0
T180	0	7	0	0
T181	0	234	0	0
T182	0	4	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0
T190	0	8	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2175	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	35	0	0
T127	0	28	0	0
T142	0	233	0	0
T177	0	31	0	0
T178	0	9	0	0
T179	0	22	0	0
T180	0	10	0	0
T181	0	261	0	0
T182	0	5	0	0
T183	0	6	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2201	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	40	0	0
T127	0	27	0	0
T142	0	258	0	0
T177	0	32	0	0
T178	0	11	0	0
T179	0	25	0	0
T180	0	1	0	0
T181	0	233	0	0
T182	0	3	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0
T190	0	28	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2061	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T116	0	23	0	0
T125	45741	46	0	0
T127	0	21	0	0
T142	0	307	0	0
T177	0	21	0	0
T178	0	14	0	0
T179	0	37	0	0
T181	0	252	0	0
T182	0	17	0	0
T183	0	7	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2290	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	58	0	0
T127	0	16	0	0
T142	0	254	0	0
T177	0	54	0	0
T178	0	15	0	0
T179	0	23	0	0
T180	0	10	0	0
T181	0	226	0	0
T182	0	7	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0
T190	0	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2678	0	0
T6	139010	17	0	0
T38	57434	0	0	0
T39	4217	0	0	0
T43	5541	0	0	0
T49	0	17	0	0
T54	4805	0	0	0
T58	9328	0	0	0
T67	0	4	0	0
T73	0	72	0	0
T98	1875	0	0	0
T125	0	95	0	0
T127	0	42	0	0
T133	3994	0	0	0
T177	0	17	0	0
T178	0	14	0	0
T191	0	38	0	0
T192	0	36	0	0
T193	9986	0	0	0
T194	26895	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2156	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	57	0	0
T127	0	24	0	0
T142	0	272	0	0
T177	0	21	0	0
T178	0	18	0	0
T179	0	30	0	0
T181	0	215	0	0
T182	0	16	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0
T190	0	6	0	0
T195	0	1	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2032	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	39	0	0
T127	0	18	0	0
T142	0	244	0	0
T177	0	20	0	0
T178	0	15	0	0
T179	0	27	0	0
T180	0	3	0	0
T181	0	254	0	0
T182	0	5	0	0
T183	0	19	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2199	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	66	0	0
T127	0	18	0	0
T142	0	282	0	0
T177	0	34	0	0
T178	0	22	0	0
T179	0	14	0	0
T180	0	5	0	0
T181	0	263	0	0
T182	0	9	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0
T190	0	1	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2195	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	46	0	0
T127	0	17	0	0
T142	0	213	0	0
T177	0	26	0	0
T178	0	10	0	0
T179	0	16	0	0
T180	0	11	0	0
T181	0	255	0	0
T182	0	4	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0
T190	0	8	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2133	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	72	0	0
T127	0	25	0	0
T142	0	285	0	0
T177	0	18	0	0
T178	0	18	0	0
T179	0	38	0	0
T181	0	264	0	0
T182	0	9	0	0
T183	0	11	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0
T190	0	6	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2248	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	49	0	0
T127	0	22	0	0
T142	0	234	0	0
T177	0	37	0	0
T178	0	17	0	0
T179	0	34	0	0
T180	0	7	0	0
T181	0	244	0	0
T182	0	8	0	0
T183	0	13	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2226	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	52	0	0
T127	0	35	0	0
T142	0	269	0	0
T177	0	31	0	0
T178	0	16	0	0
T179	0	32	0	0
T180	0	4	0	0
T181	0	268	0	0
T182	0	2	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0
T190	0	3	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2171	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T116	0	14	0	0
T125	45741	30	0	0
T127	0	14	0	0
T142	0	226	0	0
T177	0	36	0	0
T178	0	9	0	0
T179	0	31	0	0
T181	0	257	0	0
T182	0	8	0	0
T183	0	8	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2120	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	58	0	0
T127	0	18	0	0
T142	0	278	0	0
T177	0	44	0	0
T178	0	27	0	0
T179	0	21	0	0
T180	0	1	0	0
T181	0	216	0	0
T182	0	20	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0
T190	0	9	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2182	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	61	0	0
T127	0	35	0	0
T142	0	261	0	0
T177	0	36	0	0
T178	0	8	0	0
T179	0	30	0	0
T180	0	7	0	0
T181	0	243	0	0
T182	0	19	0	0
T183	0	9	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2110	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T116	0	37	0	0
T125	45741	43	0	0
T127	0	29	0	0
T142	0	247	0	0
T177	0	23	0	0
T178	0	7	0	0
T179	0	44	0	0
T181	0	256	0	0
T182	0	16	0	0
T183	0	2	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2317	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	66	0	0
T127	0	28	0	0
T142	0	274	0	0
T177	0	12	0	0
T178	0	12	0	0
T179	0	46	0	0
T180	0	3	0	0
T181	0	258	0	0
T182	0	8	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0
T190	0	2	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2253	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	72	0	0
T127	0	15	0	0
T142	0	260	0	0
T177	0	26	0	0
T178	0	16	0	0
T179	0	23	0	0
T181	0	236	0	0
T182	0	23	0	0
T183	0	11	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0
T190	0	1	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2240	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	59	0	0
T127	0	13	0	0
T142	0	323	0	0
T177	0	33	0	0
T178	0	15	0	0
T179	0	13	0	0
T180	0	6	0	0
T181	0	244	0	0
T182	0	3	0	0
T183	0	4	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2275	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	48	0	0
T127	0	23	0	0
T142	0	246	0	0
T177	0	22	0	0
T178	0	6	0	0
T179	0	14	0	0
T180	0	1	0	0
T181	0	258	0	0
T182	0	16	0	0
T183	0	18	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2139	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	61	0	0
T127	0	32	0	0
T142	0	216	0	0
T177	0	15	0	0
T178	0	25	0	0
T179	0	11	0	0
T180	0	9	0	0
T181	0	274	0	0
T182	0	10	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0
T190	0	9	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2248	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T116	0	29	0	0
T125	45741	39	0	0
T127	0	42	0	0
T142	0	284	0	0
T177	0	18	0	0
T178	0	11	0	0
T179	0	21	0	0
T181	0	278	0	0
T182	0	21	0	0
T183	0	15	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2323	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	49	0	0
T127	0	28	0	0
T142	0	231	0	0
T177	0	34	0	0
T178	0	14	0	0
T179	0	34	0	0
T180	0	5	0	0
T181	0	223	0	0
T182	0	21	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0
T190	0	6	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2215	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	37	0	0
T127	0	24	0	0
T142	0	260	0	0
T177	0	35	0	0
T178	0	21	0	0
T179	0	47	0	0
T180	0	2	0	0
T181	0	226	0	0
T182	0	4	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0
T190	0	12	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2300	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	71	0	0
T127	0	40	0	0
T142	0	270	0	0
T177	0	28	0	0
T178	0	16	0	0
T179	0	6	0	0
T180	0	15	0	0
T181	0	218	0	0
T183	0	8	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0
T190	0	16	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2136	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	39	0	0
T127	0	33	0	0
T142	0	242	0	0
T177	0	22	0	0
T178	0	25	0	0
T179	0	22	0	0
T180	0	9	0	0
T181	0	250	0	0
T182	0	11	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0
T190	0	3	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31153682	2215	0	0
T18	7700	0	0	0
T29	9422	0	0	0
T46	41069	0	0	0
T125	45741	50	0	0
T127	0	17	0	0
T142	0	280	0	0
T177	0	34	0	0
T178	0	24	0	0
T179	0	14	0	0
T181	0	217	0	0
T182	0	17	0	0
T183	0	4	0	0
T184	11178	0	0	0
T185	3809	0	0	0
T186	115596	0	0	0
T187	5307	0	0	0
T188	6037	0	0	0
T189	1381	0	0	0
T190	0	15	0	0