Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3862439	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

618779

1

T1

5

T2

651

T3

155

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4063627	1			T1	1		T2	5517		T3	407
values[0x0]	207729	1			T1	9		T2	224		T3	50
values[0x1]	209862	1			T1	10		T2	232		T3	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2635728	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1845490

1

T1

5

T2

2399

T3

246

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14429	1			T2	13		T3	10		T4	20
valid_sources[0x01]	16526	1			T2	35		T4	25		T16	2
valid_sources[0x02]	18107	1			T2	28		T4	19		T14	2
valid_sources[0x03]	14191	1			T2	18		T3	1		T4	17
valid_sources[0x04]	13457	1			T2	26		T3	1		T4	22
valid_sources[0x05]	14761	1			T1	1		T2	25		T4	30
valid_sources[0x06]	18273	1			T2	23		T4	24		T14	3
valid_sources[0x07]	27137	1			T2	19		T4	32		T14	8
valid_sources[0x08]	14380	1			T2	20		T4	14		T14	7
valid_sources[0x09]	14390	1			T2	29		T3	1		T4	17
valid_sources[0x0a]	14012	1			T2	20		T4	23		T14	10
valid_sources[0x0b]	14179	1			T2	29		T3	1		T4	29
valid_sources[0x0c]	15480	1			T2	27		T4	27		T14	5
valid_sources[0x0d]	23576	1			T2	22		T3	8		T4	19
valid_sources[0x0e]	16770	1			T2	30		T3	8		T4	24
valid_sources[0x0f]	14125	1			T2	15		T3	3		T4	20
valid_sources[0x10]	14393	1			T2	29		T3	13		T4	16
valid_sources[0x11]	14730	1			T2	24		T4	18		T5	1
valid_sources[0x12]	13945	1			T2	24		T3	10		T4	18
valid_sources[0x13]	13334	1			T2	24		T4	17		T5	6
valid_sources[0x14]	20126	1			T2	24		T4	25		T14	6
valid_sources[0x15]	14870	1			T2	24		T3	6		T4	28
valid_sources[0x16]	13832	1			T2	19		T3	1		T4	21
valid_sources[0x17]	39619	1			T2	28		T4	27		T5	19
valid_sources[0x18]	26058	1			T2	15		T3	3		T4	20
valid_sources[0x19]	15305	1			T2	23		T3	4		T4	20
valid_sources[0x1a]	15403	1			T2	24		T4	16		T14	4
valid_sources[0x1b]	15520	1			T1	1		T2	18		T4	20
valid_sources[0x1c]	15118	1			T2	25		T3	5		T4	18
valid_sources[0x1d]	32184	1			T2	32		T4	18		T5	4
valid_sources[0x1e]	26997	1			T2	18		T4	21		T14	3
valid_sources[0x1f]	14616	1			T2	23		T4	26		T5	5
valid_sources[0x20]	17196	1			T2	23		T3	1		T4	15
valid_sources[0x21]	13865	1			T2	28		T4	22		T6	2
valid_sources[0x22]	15305	1			T2	25		T4	29		T84	56
valid_sources[0x23]	14216	1			T2	23		T3	4		T4	14
valid_sources[0x24]	15968	1			T2	29		T3	3		T4	14
valid_sources[0x25]	17855	1			T2	23		T3	4		T4	19
valid_sources[0x26]	14872	1			T2	36		T4	17		T5	1
valid_sources[0x27]	19850	1			T2	26		T4	33		T14	8
valid_sources[0x28]	67563	1			T2	26		T3	1		T4	20
valid_sources[0x29]	14099	1			T2	24		T4	20		T14	3
valid_sources[0x2a]	16252	1			T2	15		T4	24		T14	2
valid_sources[0x2b]	29206	1			T2	24		T4	12		T14	1
valid_sources[0x2c]	13636	1			T2	24		T3	6		T4	15
valid_sources[0x2d]	29741	1			T2	28		T4	25		T14	4
valid_sources[0x2e]	13724	1			T2	32		T4	13		T14	6
valid_sources[0x2f]	14139	1			T2	20		T3	1		T4	19
valid_sources[0x30]	14278	1			T2	27		T3	1		T4	21
valid_sources[0x31]	13730	1			T2	18		T4	24		T14	4
valid_sources[0x32]	15415	1			T2	22		T3	2		T4	20
valid_sources[0x33]	18892	1			T2	22		T4	21		T14	6
valid_sources[0x34]	14286	1			T2	23		T3	5		T4	15
valid_sources[0x35]	17921	1			T2	9		T3	7		T4	20
valid_sources[0x36]	14608	1			T2	27		T3	9		T4	23
valid_sources[0x37]	38861	1			T2	14		T4	15		T14	4
valid_sources[0x38]	17454	1			T1	1		T2	28		T3	4
valid_sources[0x39]	15557	1			T2	32		T3	4		T4	20
valid_sources[0x3a]	14235	1			T2	23		T4	24		T14	3
valid_sources[0x3b]	14744	1			T2	25		T3	6		T4	17
valid_sources[0x3c]	22471	1			T2	28		T3	2		T4	20
valid_sources[0x3d]	21756	1			T2	22		T4	24		T14	2
valid_sources[0x3e]	21575	1			T2	24		T3	4		T4	17
valid_sources[0x3f]	20268	1			T2	17		T3	4		T4	15
valid_sources[0x40]	14971	1			T2	31		T3	5		T4	18
valid_sources[0x41]	14545	1			T2	13		T3	7		T4	24
valid_sources[0x42]	15994	1			T2	24		T4	27		T14	8
valid_sources[0x43]	36574	1			T1	1		T2	23		T4	23
valid_sources[0x44]	19879	1			T2	25		T4	16		T14	6
valid_sources[0x45]	15300	1			T2	22		T4	21		T14	3
valid_sources[0x46]	14437	1			T2	13		T4	18		T14	11
valid_sources[0x47]	13784	1			T2	16		T4	22		T5	3
valid_sources[0x48]	14198	1			T2	21		T4	26		T14	2
valid_sources[0x49]	23708	1			T2	20		T4	27		T14	2
valid_sources[0x4a]	17132	1			T2	25		T4	15		T14	6
valid_sources[0x4b]	16316	1			T2	29		T3	3		T4	22
valid_sources[0x4c]	16901	1			T1	1		T2	23		T4	18
valid_sources[0x4d]	13743	1			T2	18		T4	18		T5	5
valid_sources[0x4e]	17645	1			T2	22		T4	25		T5	9
valid_sources[0x4f]	15160	1			T2	21		T4	23		T5	8
valid_sources[0x50]	17054	1			T2	12		T4	18		T14	3
valid_sources[0x51]	15509	1			T2	29		T3	9		T4	19
valid_sources[0x52]	14418	1			T2	29		T4	17		T14	6
valid_sources[0x53]	14457	1			T2	21		T3	8		T4	10
valid_sources[0x54]	14341	1			T2	16		T4	22		T14	7
valid_sources[0x55]	13711	1			T2	25		T4	26		T14	7
valid_sources[0x56]	15273	1			T2	17		T4	23		T5	1
valid_sources[0x57]	13414	1			T2	29		T4	23		T5	1
valid_sources[0x58]	14609	1			T2	12		T4	18		T14	3
valid_sources[0x59]	18293	1			T1	1		T2	19		T3	19
valid_sources[0x5a]	17261	1			T2	18		T4	17		T14	5
valid_sources[0x5b]	17036	1			T2	22		T4	18		T14	8
valid_sources[0x5c]	14783	1			T2	17		T3	1		T4	23
valid_sources[0x5d]	16038	1			T2	22		T3	16		T4	20
valid_sources[0x5e]	13657	1			T2	25		T3	2		T4	22
valid_sources[0x5f]	18519	1			T2	25		T4	18		T14	5
valid_sources[0x60]	15881	1			T2	27		T4	24		T14	11
valid_sources[0x61]	14449	1			T2	25		T4	16		T14	5
valid_sources[0x62]	18779	1			T2	29		T3	1		T4	26
valid_sources[0x63]	17374	1			T2	24		T3	13		T4	21
valid_sources[0x64]	16444	1			T2	14		T4	18		T14	3
valid_sources[0x65]	13841	1			T2	17		T3	8		T4	19
valid_sources[0x66]	16878	1			T2	18		T3	10		T4	21
valid_sources[0x67]	14914	1			T2	20		T4	21		T5	4
valid_sources[0x68]	19233	1			T2	21		T4	29		T5	7
valid_sources[0x69]	14633	1			T2	27		T4	15		T14	1
valid_sources[0x6a]	14545	1			T2	34		T4	25		T5	10
valid_sources[0x6b]	14169	1			T2	27		T4	23		T14	4
valid_sources[0x6c]	15023	1			T2	28		T3	9		T4	15
valid_sources[0x6d]	15839	1			T2	21		T4	21		T5	3
valid_sources[0x6e]	15501	1			T2	27		T4	16		T14	5
valid_sources[0x6f]	21687	1			T2	29		T3	5		T4	20
valid_sources[0x70]	16596	1			T2	28		T3	4		T4	22
valid_sources[0x71]	16392	1			T2	22		T4	23		T14	8
valid_sources[0x72]	13819	1			T2	17		T4	17		T5	7
valid_sources[0x73]	14663	1			T2	25		T3	1		T4	28
valid_sources[0x74]	15246	1			T2	27		T3	11		T4	24
valid_sources[0x75]	16107	1			T2	20		T3	1		T4	21
valid_sources[0x76]	14684	1			T2	28		T3	4		T4	18
valid_sources[0x77]	18092	1			T2	16		T4	16		T14	2
valid_sources[0x78]	18330	1			T2	16		T3	2		T4	25
valid_sources[0x79]	14326	1			T2	18		T4	21		T14	4
valid_sources[0x7a]	14323	1			T2	26		T4	16		T14	6
valid_sources[0x7b]	24717	1			T2	27		T4	26		T5	7
valid_sources[0x7c]	14846	1			T2	23		T4	23		T14	1
valid_sources[0x7d]	13886	1			T2	24		T4	19		T14	5
valid_sources[0x7e]	14254	1			T2	24		T4	18		T14	1
valid_sources[0x7f]	14084	1			T2	26		T3	2		T4	23
valid_sources[0x80]	14035	1			T2	21		T4	23		T5	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

334791

1

T2

351

T3

125

T4

153

values[0x0]

all_enables

biggest_size

149477

1

T1

3

T2

156

T3

23

values[0x1]

all_enables

biggest_size

134511

1

T1

2

T2

144

T3

7