Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4221727	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

597033

1

T1

392

T2

707

T3

372

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4417631	1			T1	509		T2	1848		T3	25291
values[0x0]	199188	1			T1	188		T2	134		T3	183
values[0x1]	201941	1			T1	199		T2	151		T3	177

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2874542	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1944218

1

T1

505

T2

1122

T3

8704

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15701	1			T1	1		T2	2		T3	116
valid_sources[0x01]	39709	1			T1	4		T2	9		T3	82
valid_sources[0x02]	15430	1			T1	5		T2	18		T3	114
valid_sources[0x03]	17974	1			T1	1		T2	8		T3	114
valid_sources[0x04]	15396	1			T1	1		T2	4		T3	103
valid_sources[0x05]	15992	1			T1	5		T2	10		T3	74
valid_sources[0x06]	15710	1			T1	9		T2	6		T3	119
valid_sources[0x07]	22636	1			T1	4		T2	8		T3	119
valid_sources[0x08]	19811	1			T1	2		T2	8		T3	89
valid_sources[0x09]	16577	1			T1	2		T2	12		T3	140
valid_sources[0x0a]	14665	1			T1	4		T2	3		T3	124
valid_sources[0x0b]	14916	1			T1	3		T2	8		T3	83
valid_sources[0x0c]	15428	1			T1	1		T2	13		T3	107
valid_sources[0x0d]	15113	1			T1	7		T2	3		T3	124
valid_sources[0x0e]	19587	1			T1	1		T2	10		T3	126
valid_sources[0x0f]	14869	1			T1	7		T2	15		T3	129
valid_sources[0x10]	14826	1			T1	6		T2	6		T3	82
valid_sources[0x11]	16537	1			T1	4		T2	4		T3	94
valid_sources[0x12]	61969	1			T1	9		T2	17		T3	81
valid_sources[0x13]	15239	1			T1	2		T2	8		T3	104
valid_sources[0x14]	15708	1			T1	2		T2	7		T3	110
valid_sources[0x15]	17030	1			T1	6		T2	8		T3	63
valid_sources[0x16]	16701	1			T1	1		T2	14		T3	116
valid_sources[0x17]	14666	1			T1	6		T2	7		T3	126
valid_sources[0x18]	17512	1			T1	7		T2	12		T3	83
valid_sources[0x19]	18600	1			T1	1		T2	12		T3	63
valid_sources[0x1a]	15112	1			T1	2		T2	14		T3	90
valid_sources[0x1b]	15849	1			T1	4		T2	3		T3	90
valid_sources[0x1c]	15932	1			T1	6		T2	4		T3	100
valid_sources[0x1d]	21066	1			T1	1		T2	4		T3	97
valid_sources[0x1e]	17915	1			T1	10		T2	22		T3	91
valid_sources[0x1f]	16886	1			T1	2		T2	13		T3	67
valid_sources[0x20]	17464	1			T1	5		T2	18		T3	90
valid_sources[0x21]	15363	1			T1	2		T2	9		T3	101
valid_sources[0x22]	15028	1			T1	5		T2	11		T3	83
valid_sources[0x23]	16412	1			T1	3		T2	12		T3	76
valid_sources[0x24]	15000	1			T2	11		T3	111		T12	3
valid_sources[0x25]	20118	1			T1	3		T2	6		T3	115
valid_sources[0x26]	16154	1			T1	1		T2	4		T3	103
valid_sources[0x27]	57576	1			T1	2		T2	19		T3	91
valid_sources[0x28]	15242	1			T1	8		T2	13		T3	93
valid_sources[0x29]	15190	1			T1	2		T2	4		T3	90
valid_sources[0x2a]	32178	1			T1	5		T2	11		T3	104
valid_sources[0x2b]	19137	1			T1	1		T2	2		T3	109
valid_sources[0x2c]	15608	1			T1	3		T2	12		T3	84
valid_sources[0x2d]	16414	1			T1	3		T2	12		T3	137
valid_sources[0x2e]	14781	1			T1	5		T2	1		T3	113
valid_sources[0x2f]	18156	1			T1	6		T2	6		T3	107
valid_sources[0x30]	18870	1			T1	5		T2	4		T3	94
valid_sources[0x31]	15852	1			T1	3		T2	12		T3	118
valid_sources[0x32]	17225	1			T2	2		T3	121		T12	26
valid_sources[0x33]	15044	1			T1	1		T2	7		T3	85
valid_sources[0x34]	15465	1			T1	2		T2	12		T3	64
valid_sources[0x35]	16342	1			T1	4		T2	5		T3	107
valid_sources[0x36]	14651	1			T1	6		T2	3		T3	156
valid_sources[0x37]	18511	1			T1	6		T2	7		T3	109
valid_sources[0x38]	16376	1			T1	4		T2	11		T3	103
valid_sources[0x39]	68448	1			T1	4		T2	3		T3	61
valid_sources[0x3a]	15766	1			T1	13		T2	3		T3	123
valid_sources[0x3b]	154138	1			T1	5		T2	8		T3	91
valid_sources[0x3c]	15252	1			T1	8		T2	14		T3	114
valid_sources[0x3d]	17206	1			T1	2		T2	7		T3	89
valid_sources[0x3e]	14717	1			T1	2		T2	2		T3	87
valid_sources[0x3f]	33359	1			T1	3		T2	8		T3	118
valid_sources[0x40]	15535	1			T1	5		T2	8		T3	105
valid_sources[0x41]	15102	1			T1	6		T2	9		T3	131
valid_sources[0x42]	17261	1			T1	4		T2	8		T3	105
valid_sources[0x43]	15011	1			T1	6		T2	8		T3	81
valid_sources[0x44]	15473	1			T1	2		T2	10		T3	110
valid_sources[0x45]	16240	1			T1	2		T2	11		T3	129
valid_sources[0x46]	15019	1			T1	5		T2	12		T3	46
valid_sources[0x47]	14984	1			T1	13		T2	5		T3	86
valid_sources[0x48]	15460	1			T1	2		T2	7		T3	118
valid_sources[0x49]	15121	1			T1	2		T2	13		T3	111
valid_sources[0x4a]	15469	1			T1	3		T2	5		T3	68
valid_sources[0x4b]	18668	1			T1	2		T2	3		T3	132
valid_sources[0x4c]	15859	1			T1	2		T2	26		T3	98
valid_sources[0x4d]	16636	1			T1	4		T2	9		T3	115
valid_sources[0x4e]	17506	1			T1	5		T2	6		T3	110
valid_sources[0x4f]	15042	1			T1	2		T2	12		T3	65
valid_sources[0x50]	15061	1			T1	8		T2	4		T3	113
valid_sources[0x51]	46426	1			T1	2		T2	20		T3	122
valid_sources[0x52]	16877	1			T1	4		T2	8		T3	96
valid_sources[0x53]	17597	1			T1	6		T2	8		T3	113
valid_sources[0x54]	15980	1			T1	7		T2	13		T3	116
valid_sources[0x55]	22705	1			T1	2		T3	103		T12	6
valid_sources[0x56]	15473	1			T1	2		T2	6		T3	81
valid_sources[0x57]	39454	1			T1	3		T2	5		T3	94
valid_sources[0x58]	14835	1			T1	3		T2	5		T3	139
valid_sources[0x59]	18821	1			T1	2		T2	8		T3	106
valid_sources[0x5a]	15022	1			T1	4		T2	3		T3	74
valid_sources[0x5b]	26477	1			T1	2		T2	3		T3	76
valid_sources[0x5c]	15749	1			T1	5		T2	12		T3	79
valid_sources[0x5d]	17733	1			T1	1		T2	9		T3	113
valid_sources[0x5e]	16143	1			T1	3		T2	10		T3	95
valid_sources[0x5f]	15654	1			T1	2		T2	6		T3	102
valid_sources[0x60]	26520	1			T1	4		T2	6		T3	109
valid_sources[0x61]	24098	1			T1	3		T2	4		T3	107
valid_sources[0x62]	15692	1			T1	1		T2	9		T3	74
valid_sources[0x63]	14739	1			T1	3		T2	13		T3	75
valid_sources[0x64]	16621	1			T1	2		T2	11		T3	127
valid_sources[0x65]	21291	1			T1	4		T2	6		T3	105
valid_sources[0x66]	17401	1			T1	5		T2	6		T3	86
valid_sources[0x67]	15885	1			T1	3		T2	17		T3	128
valid_sources[0x68]	17635	1			T1	3		T2	7		T3	122
valid_sources[0x69]	17453	1			T1	2		T2	12		T3	100
valid_sources[0x6a]	17149	1			T1	4		T2	5		T3	80
valid_sources[0x6b]	15312	1			T1	5		T2	2		T3	105
valid_sources[0x6c]	20089	1			T1	6		T2	5		T3	91
valid_sources[0x6d]	19346	1			T1	7		T2	7		T3	108
valid_sources[0x6e]	15848	1			T1	2		T2	9		T3	124
valid_sources[0x6f]	15303	1			T1	3		T2	5		T3	98
valid_sources[0x70]	39501	1			T1	5		T2	11		T3	125
valid_sources[0x71]	15671	1			T2	6		T3	69		T12	7
valid_sources[0x72]	16299	1			T1	4		T2	7		T3	83
valid_sources[0x73]	14996	1			T1	1		T2	2		T3	123
valid_sources[0x74]	14746	1			T2	9		T3	73		T12	5
valid_sources[0x75]	14826	1			T1	1		T2	3		T3	103
valid_sources[0x76]	15636	1			T2	8		T3	116		T12	27
valid_sources[0x77]	15694	1			T1	3		T2	9		T3	128
valid_sources[0x78]	17144	1			T1	2		T2	5		T3	77
valid_sources[0x79]	22128	1			T1	2		T2	5		T3	93
valid_sources[0x7a]	15824	1			T1	4		T2	3		T3	111
valid_sources[0x7b]	16390	1			T1	6		T2	7		T3	111
valid_sources[0x7c]	15930	1			T1	1		T2	4		T3	96
valid_sources[0x7d]	17211	1			T1	4		T3	87		T12	25
valid_sources[0x7e]	16262	1			T1	3		T2	5		T3	106
valid_sources[0x7f]	21962	1			T1	7		T2	7		T3	92
valid_sources[0x80]	15662	1			T1	3		T3	162		T12	30

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

326002

1

T1

135

T2

500

T3

117

values[0x0]

all_enables

biggest_size

142531

1

T1

130

T2

103

T3

141

values[0x1]

all_enables

biggest_size

128500

1

T1

127

T2

104

T3

114