Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	32811643	14449	0	0
attest_sw_binding_0_rd_A	32811643	2994	0	0
attest_sw_binding_1_rd_A	32811643	2812	0	0
attest_sw_binding_2_rd_A	32811643	2929	0	0
attest_sw_binding_3_rd_A	32811643	3026	0	0
attest_sw_binding_4_rd_A	32811643	2901	0	0
attest_sw_binding_5_rd_A	32811643	2817	0	0
attest_sw_binding_6_rd_A	32811643	2952	0	0
attest_sw_binding_7_rd_A	32811643	3020	0	0
intr_enable_rd_A	32811643	3600	0	0
key_version_rd_A	32811643	2953	0	0
max_creator_key_ver_regwen_rd_A	32811643	2951	0	0
max_owner_int_key_ver_regwen_rd_A	32811643	2999	0	0
max_owner_key_ver_regwen_rd_A	32811643	3103	0	0
reseed_interval_regwen_rd_A	32811643	3081	0	0
salt_0_rd_A	32811643	3148	0	0
salt_1_rd_A	32811643	3025	0	0
salt_2_rd_A	32811643	3056	0	0
salt_3_rd_A	32811643	2873	0	0
salt_4_rd_A	32811643	2999	0	0
salt_5_rd_A	32811643	3029	0	0
salt_6_rd_A	32811643	3100	0	0
salt_7_rd_A	32811643	3089	0	0
sealing_sw_binding_0_rd_A	32811643	3123	0	0
sealing_sw_binding_1_rd_A	32811643	2974	0	0
sealing_sw_binding_2_rd_A	32811643	2903	0	0
sealing_sw_binding_3_rd_A	32811643	2905	0	0
sealing_sw_binding_4_rd_A	32811643	3154	0	0
sealing_sw_binding_5_rd_A	32811643	3040	0	0
sealing_sw_binding_6_rd_A	32811643	2965	0	0
sealing_sw_binding_7_rd_A	32811643	3002	0	0
sideload_clear_rd_A	32811643	3076	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	14449	0	0
T25	14095	0	0	0
T59	0	38	0	0
T68	0	307	0	0
T69	0	55	0	0
T95	158044	0	0	0
T111	18845	551	0	0
T112	0	480	0	0
T113	0	336	0	0
T116	3268	0	0	0
T131	0	630	0	0
T133	0	22	0	0
T134	0	679	0	0
T135	6384	0	0	0
T136	11176	0	0	0
T137	4950	0	0	0
T138	210711	0	0	0
T139	6221	0	0	0
T140	2868	0	0	0
T149	0	50	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	2994	0	0
T47	275617	0	0	0
T59	0	13	0	0
T61	4253	0	0	0
T69	0	47	0	0
T113	41848	35	0	0
T120	0	24	0	0
T133	0	22	0	0
T198	0	39	0	0
T199	0	66	0	0
T200	0	39	0	0
T201	0	37	0	0
T202	0	25	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	2812	0	0
T47	275617	0	0	0
T59	0	21	0	0
T61	4253	0	0	0
T69	0	39	0	0
T113	41848	40	0	0
T120	0	5	0	0
T133	0	42	0	0
T198	0	12	0	0
T199	0	63	0	0
T200	0	40	0	0
T201	0	28	0	0
T202	0	20	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	2929	0	0
T47	275617	0	0	0
T59	0	24	0	0
T61	4253	0	0	0
T69	0	35	0	0
T113	41848	36	0	0
T120	0	24	0	0
T133	0	14	0	0
T198	0	26	0	0
T199	0	58	0	0
T200	0	53	0	0
T201	0	16	0	0
T202	0	29	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	3026	0	0
T47	275617	0	0	0
T59	0	21	0	0
T61	4253	0	0	0
T69	0	64	0	0
T113	41848	46	0	0
T120	0	16	0	0
T133	0	21	0	0
T198	0	13	0	0
T199	0	56	0	0
T200	0	72	0	0
T201	0	11	0	0
T202	0	11	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	2901	0	0
T47	275617	0	0	0
T59	0	23	0	0
T61	4253	0	0	0
T69	0	34	0	0
T113	41848	58	0	0
T120	0	25	0	0
T133	0	28	0	0
T198	0	40	0	0
T199	0	63	0	0
T200	0	53	0	0
T201	0	31	0	0
T202	0	20	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	2817	0	0
T47	275617	0	0	0
T59	0	18	0	0
T61	4253	0	0	0
T69	0	41	0	0
T113	41848	45	0	0
T120	0	20	0	0
T133	0	43	0	0
T198	0	34	0	0
T199	0	51	0	0
T200	0	61	0	0
T201	0	43	0	0
T202	0	10	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	2952	0	0
T47	275617	0	0	0
T59	0	10	0	0
T61	4253	0	0	0
T69	0	56	0	0
T113	41848	35	0	0
T120	0	21	0	0
T133	0	19	0	0
T198	0	15	0	0
T199	0	54	0	0
T200	0	84	0	0
T201	0	18	0	0
T202	0	16	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	3020	0	0
T47	275617	0	0	0
T59	0	17	0	0
T61	4253	0	0	0
T69	0	75	0	0
T113	41848	70	0	0
T120	0	25	0	0
T133	0	28	0	0
T198	0	16	0	0
T199	0	56	0	0
T200	0	50	0	0
T201	0	37	0	0
T202	0	9	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	3600	0	0
T6	12418	0	0	0
T30	2936	0	0	0
T48	0	23	0	0
T49	0	20	0	0
T59	0	6	0	0
T60	6274	0	0	0
T65	85312	31	0	0
T69	0	116	0	0
T71	0	22	0	0
T90	21681	0	0	0
T113	0	60	0	0
T115	3990	0	0	0
T133	0	42	0	0
T198	0	64	0	0
T199	0	83	0	0
T210	8516	0	0	0
T211	12928	0	0	0
T212	15399	0	0	0
T213	1428	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	2953	0	0
T47	275617	0	0	0
T59	0	40	0	0
T61	4253	0	0	0
T69	0	44	0	0
T113	41848	32	0	0
T120	0	12	0	0
T133	0	22	0	0
T198	0	26	0	0
T199	0	69	0	0
T200	0	70	0	0
T201	0	24	0	0
T202	0	11	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	2951	0	0
T47	275617	0	0	0
T59	0	36	0	0
T61	4253	0	0	0
T69	0	46	0	0
T113	41848	39	0	0
T120	0	13	0	0
T133	0	43	0	0
T198	0	27	0	0
T199	0	53	0	0
T200	0	51	0	0
T201	0	37	0	0
T202	0	10	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	2999	0	0
T47	275617	0	0	0
T59	0	26	0	0
T61	4253	0	0	0
T69	0	64	0	0
T113	41848	56	0	0
T120	0	16	0	0
T133	0	15	0	0
T198	0	26	0	0
T199	0	81	0	0
T200	0	84	0	0
T201	0	24	0	0
T202	0	16	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	3103	0	0
T47	275617	0	0	0
T59	0	28	0	0
T61	4253	0	0	0
T69	0	42	0	0
T113	41848	31	0	0
T120	0	34	0	0
T133	0	60	0	0
T198	0	32	0	0
T199	0	69	0	0
T200	0	84	0	0
T201	0	34	0	0
T202	0	20	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	3081	0	0
T47	275617	0	0	0
T59	0	24	0	0
T61	4253	0	0	0
T69	0	75	0	0
T113	41848	47	0	0
T120	0	23	0	0
T133	0	43	0	0
T198	0	15	0	0
T199	0	48	0	0
T200	0	66	0	0
T201	0	24	0	0
T202	0	14	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	3148	0	0
T47	275617	0	0	0
T59	0	34	0	0
T61	4253	0	0	0
T69	0	47	0	0
T113	41848	21	0	0
T120	0	31	0	0
T133	0	44	0	0
T198	0	31	0	0
T199	0	60	0	0
T200	0	40	0	0
T201	0	41	0	0
T202	0	21	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	3025	0	0
T47	275617	0	0	0
T59	0	22	0	0
T61	4253	0	0	0
T69	0	74	0	0
T113	41848	52	0	0
T120	0	8	0	0
T133	0	21	0	0
T198	0	17	0	0
T199	0	84	0	0
T200	0	42	0	0
T201	0	33	0	0
T202	0	13	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	3056	0	0
T47	275617	0	0	0
T59	0	12	0	0
T61	4253	0	0	0
T69	0	49	0	0
T113	41848	46	0	0
T120	0	10	0	0
T133	0	21	0	0
T198	0	33	0	0
T199	0	75	0	0
T200	0	50	0	0
T201	0	19	0	0
T202	0	19	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	2873	0	0
T47	275617	0	0	0
T59	0	35	0	0
T61	4253	0	0	0
T69	0	59	0	0
T113	41848	84	0	0
T133	0	30	0	0
T198	0	27	0	0
T199	0	63	0	0
T200	0	61	0	0
T201	0	26	0	0
T202	0	28	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0
T214	0	6	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	2999	0	0
T47	275617	0	0	0
T59	0	29	0	0
T61	4253	0	0	0
T69	0	60	0	0
T113	41848	52	0	0
T120	0	8	0	0
T133	0	12	0	0
T198	0	24	0	0
T199	0	57	0	0
T200	0	66	0	0
T201	0	31	0	0
T202	0	28	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	3029	0	0
T47	275617	0	0	0
T59	0	20	0	0
T61	4253	0	0	0
T69	0	52	0	0
T113	41848	51	0	0
T120	0	15	0	0
T133	0	37	0	0
T198	0	22	0	0
T199	0	69	0	0
T200	0	64	0	0
T201	0	16	0	0
T202	0	27	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	3100	0	0
T47	275617	0	0	0
T59	0	18	0	0
T61	4253	0	0	0
T69	0	46	0	0
T113	41848	60	0	0
T120	0	19	0	0
T133	0	25	0	0
T198	0	32	0	0
T199	0	64	0	0
T200	0	47	0	0
T201	0	36	0	0
T202	0	12	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	3089	0	0
T47	275617	0	0	0
T59	0	33	0	0
T61	4253	0	0	0
T69	0	35	0	0
T113	41848	20	0	0
T120	0	18	0	0
T133	0	47	0	0
T198	0	19	0	0
T199	0	52	0	0
T200	0	49	0	0
T201	0	16	0	0
T202	0	10	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	3123	0	0
T47	275617	0	0	0
T59	0	35	0	0
T61	4253	0	0	0
T69	0	56	0	0
T113	41848	52	0	0
T120	0	10	0	0
T133	0	35	0	0
T198	0	42	0	0
T199	0	70	0	0
T200	0	77	0	0
T201	0	19	0	0
T202	0	17	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	2974	0	0
T47	275617	0	0	0
T59	0	20	0	0
T61	4253	0	0	0
T69	0	26	0	0
T113	41848	45	0	0
T120	0	24	0	0
T133	0	27	0	0
T198	0	28	0	0
T199	0	42	0	0
T200	0	77	0	0
T201	0	45	0	0
T202	0	25	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	2903	0	0
T47	275617	0	0	0
T59	0	21	0	0
T61	4253	0	0	0
T69	0	51	0	0
T113	41848	61	0	0
T120	0	20	0	0
T133	0	41	0	0
T198	0	33	0	0
T199	0	62	0	0
T200	0	55	0	0
T201	0	27	0	0
T202	0	12	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	2905	0	0
T47	275617	0	0	0
T59	0	29	0	0
T61	4253	0	0	0
T69	0	49	0	0
T113	41848	47	0	0
T120	0	25	0	0
T133	0	29	0	0
T198	0	19	0	0
T199	0	40	0	0
T200	0	63	0	0
T201	0	34	0	0
T202	0	10	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	3154	0	0
T47	275617	0	0	0
T59	0	21	0	0
T61	4253	0	0	0
T69	0	37	0	0
T113	41848	34	0	0
T133	0	19	0	0
T198	0	17	0	0
T199	0	58	0	0
T200	0	52	0	0
T201	0	34	0	0
T202	0	8	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0
T215	0	2	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	3040	0	0
T47	275617	0	0	0
T59	0	33	0	0
T61	4253	0	0	0
T69	0	47	0	0
T113	41848	49	0	0
T120	0	35	0	0
T133	0	22	0	0
T198	0	30	0	0
T199	0	60	0	0
T200	0	61	0	0
T201	0	19	0	0
T202	0	20	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	2965	0	0
T47	275617	0	0	0
T59	0	25	0	0
T61	4253	0	0	0
T69	0	49	0	0
T113	41848	42	0	0
T120	0	22	0	0
T133	0	23	0	0
T198	0	17	0	0
T199	0	75	0	0
T200	0	76	0	0
T201	0	18	0	0
T202	0	19	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	3002	0	0
T47	275617	0	0	0
T59	0	24	0	0
T61	4253	0	0	0
T69	0	40	0	0
T113	41848	43	0	0
T120	0	5	0	0
T133	0	28	0	0
T198	0	27	0	0
T199	0	80	0	0
T200	0	58	0	0
T201	0	33	0	0
T202	0	15	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32811643	3076	0	0
T47	275617	0	0	0
T59	0	17	0	0
T61	4253	0	0	0
T69	0	52	0	0
T113	41848	69	0	0
T120	0	30	0	0
T133	0	35	0	0
T198	0	26	0	0
T199	0	71	0	0
T200	0	62	0	0
T201	0	37	0	0
T202	0	6	0	0
T203	17216	0	0	0
T204	8655	0	0	0
T205	5765	0	0	0
T206	7742	0	0	0
T207	15931	0	0	0
T208	11596	0	0	0
T209	232993	0	0	0